Previous Report No.

3: “Complementary Symmetry Amplifier”

Universidad Nacional de Ingeniería
Facultad de Ingeniería Eléctrica y Electrónica
Laboratorio de Electrónica II (EE442-M) 2020-I
Christian Guillermo Segura Chavesta
csegurac@uni.pe
Silvana Maria Chacón Culqui
schaconc@uni.pe
Yosmar Anderson Flores Arteaga
yosmar.flores.a@uni.pe
Erick Alessandro Villegas Tito
evillegast@uni.pe

OBJECTIVES: Design, simulate, implement and analyze an

complementary symmetric amplifier.
I. INTRODUCTION
A push pull amplifier is an amplifier which has an output stage
that can drive a current in either direction through through the
load. The output stage of a typical push pull amplifier consists
of of two identical BJTs or MOSFETs one sourcing current
through the load while the other one sinking the current from
the load. Push pull amplifiers are superior over single ended
amplifiers (using a single transistor at the output for driving
the load) in terms of distortion and performance. A single
ended amplifier, how well it may be designed will surely
introduce some distortion due to the non-linearity of its
dynamic transfer characteristics. Push pull amplifiers are
commonly used in situations where low distortion, high
efficiency and high output power are required. The basic
operation of a push pull amplifier is as follows: The signal to
be amplified is first split into two identical signals 180° out of
phase. Generally, this splitting is done using an input coupling
transformer. The input coupling transformer is so arranged that
one signal in applied to the input of one transistor and the
other signal is applied to the input of the other transistor.
Advantages of push pull amplifier are low distortion, absence
of magnetic saturation in the coupling transformer core, and
cancellation of power supply ripples which results in the
absence of hum while the disadvantages are the need of two
identical transistors and the requirement of bulky and costly
coupling transformers.
The circuit of Fig. 1 uses a center-tapped input transformer to
produce opposite polarity signals to the two transistor inputs
and an output transformer to drive the load in a push-pull
mode of operation described next. During the first half-cycle
of operation, transistor Q1 is driven into conduction whereas
transistor Q2 is driven off. The current I1 through the
transformer results in the first half-cycle of signal to the load.
During the second half-cycle of the input signal, Q2 conducts
whereas Q1 stays off, the current I2 through the transformer
resulting in the second half-cycle to the load. The overall
signal developed across the load then varies over the full cycle
of signal operation.
Fig 1. Push pull circuit
Complementary-Symmetry Circuits
Using complementary transistors (npn and pnp) it is possible
to obtain a full cycle output across a load using half-cycles of
operation from each transistor, as shown in Fig.2 While a
single input signal is applied to the base of both transistors, the
transistors, being of opposite type, will conduct on opposite
half-cycles of the input. The npn transistor will be biased into
conduction by the positive half-cycle of signal, with a resulting
half-cycle of signal across the load as shown in Fig. 3. During
the negative half-cycle of signal, the pnp transistor is biased
into conduction when the input goes negative, as shown in Fig.
4. During a complete cycle of the input, a complete cycle of
output signal is developed across the load. One disadvantage
of the circuit is the need for two separate voltage supplies.
Another, less obvious disadvantage with the complementary
circuit is shown in the resulting crossover distortion in the
output signal (see Fig. 5). Crossover distortion refers to the
fact that during the signal crossover from positive to negative
(or vice versa) there is some nonlinearity in the output signal.
This results from the fact that the circuit does not provide
exact switching of one transistor off and the other on at the
zero-voltage condition. Both transistors may be partially off so
that the output voltage does not follow the input around the
zero-voltage condition. Biasing the transistors in class AB
improves this operation by biasing both transistors to be on for
more than half a cycle. A more practical version of a push-pull
circuit using complementary transistors is shown in Fig. 6
Note that the load is driven as the output of an emitter follower
so that the load resistance of the load is matched by the low
output resistance of the driving source. The circuit uses
complementary Darlington-connected transistors to provide
higher output current and lower output resistance
V i ≈ 0V
The transistors are biased in such a way that each transistor
conducts for a small quiescent current I Q at V i =0V .

A biasing circuit is shown in Fig. 6. A biasing voltage V BB is

applied between the bases of Q N and Q P. For V i =0V , a
voltage V BB /2 appears across the B-E junction of each Q N
V BB
and Q P. Choosing =V BEN =V EBPwill ensure that both
2
transistors will be on the verge of conducting. That is,
V 0=0for V i=0. A small positive input voltage V i will then
Fig 2. Complementary symmetry circuit
cause Q N to conduct; similarly, a small negative input voltage
will cause Q P to conduct.

Fig 3. Positive half cycle

Fig 6. Class AB output

TRANSFER CHARACTERISTIC

The output voltage V o is given by

Fig 4. Negative half cycle

V BB
V O =V i+ −V BEN
If the transistors Q1 and Q 2 do not turn on and off a t exactly 2
the same time, then there is a gap in the output voltage. Fig 5.
Shows this, it is called crossover distortion. which, for identical transistors of V BEN =V EBP and
V BB
=V BEN , gives V O =V i .Therefore, most of the
2
crossover distortion is eliminated. The transfer characteristic is
shown in Fig. 7.

Fig 5. Crossover distortion

The crossover distortion of a complementary class B push-pull

amplifier is minimized or eliminated in a class AB amplifier, Fig 7. Transfer characteristic
in which the transistors operate in the active region when the
input voltage V i is small. For positive V O , a current i O flows through R L: that is:
i N =i P +i O
Any increase in i N will cause a corresponding increase in
V BEN above the quiescent value of V BB /2. Since V BB must
remain constant, the increase in V BEN will cause an equal
decrease in V EBP and hence in i P . Thus,
V BB =V BEN +V EBP

which, expressed in terms of saturation current I S, becomes

IQ iN iP
2 V T ln ( )
IS
=V T ln ( )
IS
+V T ( )
IS

After simplification, we get

I 2Q =i N i P

which can be solved for the current i N for a given quiescent

I i i
current Q. Thus, as N increases, P decreases by the same
ratio. However, their product remains constant. As V i
becomes positive, Q N acts as an emitter follower delivering
output power, and Q P conducts only a very small current.
When V i becomes negative, the opposite occurs: i N acts as an
emitter follower, and V O follows the input signal V i . The
circuit operates in class AB mode because both transistors
remain on and operate in the active region.
BIASING WITH DIODES
The biasing circuit in Fig. 6. has a serious problem when the
temperatures of Q N and Q P increase as a result of their power
dissipation. Recall that the value of V BE for a given current
falls with temperature at approximately 2.5 mV⁄ °C. Thus, if
the biasing voltage V BB /2 remains constant with temperature,
V BE ¿ ¿) is also held constant, and the collector current will
increase as temperature increases. The increase in the collector
current increases the power dissipation, in turn increasing the
collector current and causing the temperature to rise further.
This phenomenon, in which a positive feedback mechanism
leads to excessive temperature rise, is called thermal runaway
Fig 8. Diode implementation
To avoid thermal runaway, the biasing voltages must decrease
as the temperature increases. One solution is to use diodes that
have a compensating effect, as shown in Fig. 8. The diodes
must be in close contact with the output transistors so that their
temperature will increase by the same amount as that of Q N
and Q P. Therefore, in discrete circuits, the diodes should be
mounted on the metal of Q N or Q P. Since resistances R1 and
R2 provide the quiescent current IQ for the transistors and also
ensure that the diodes conduct, to guarantee the base biasing
current for Q N when the load current becomes maximum, we
must have
iN I +i
I R =I D1 + ≈ I D 1+ Q O
hfe 1+ hfe
Thus, the values of R1 and R2 can be found from
V BB
I R =I D 1=
(
V CC −V D 1 ¿ V D 2=
2 )
I D (min) +( I ¿ ¿Q+i O (max) )/(1+h fe )¿
where IQ = IS exp (VBB ⁄ 2VT) and ID1(min) is the minimum
current needed to ensure diode conduction. Because IQ is
usually smaller than iO(max), IQ can often be neglected in
finding the values of R1 and R2.

Quasi-Complementary Push–Pull Amplifier

In pracical power amplifier circuits, it is preferable to use npn

transistors for both high-current-output devices. Since the
push-pull connection requires complementary devices, a pnp
high-power transistor must be used. A practical means of
obtaining complementary operation while using the same,
matched npn transistors for the output is provided by a quasi-
complementary circuit, as shown in Fig.6. The push pull
operation is achieved by using complementary transistors (Q1
and Q2) before the matched npn output transistors (Q3 and
Q4). Notice that transistors Q1 and Q3 form a Darlington
connection that provides output from a low-impedance
emitter-follower. The connection of transistors Q2 and Q4
forms a feedback pair, which similarly provides a low-
impedance drive to the load. Resistor R2 can be adjusted to
minimize crossover distortion by adjusting the dc bias
condition. The single input signal applied to the push-pull
stage then results in a full cycle output to the load. The quasi
complementary push-pull amplifier is presently the most
popular form of power amplifier.
Fig 10. Hybrid model in low frequency

V OX 1.52 x 10−3 s
=G1=−10.81( )
V th 1.52 x 10−3 s+1

1
f L= =104.70 Hz
2 π x 1.52 x 10−3

G0=10.81

For high frequency

Fig 9. Quasi-complementary push pull amplifier As we know in high frequency a transistor exhibit capacitance
between each of its terminals (i.e., base, emitter, collector).
These capacitances ultimately limit amplifier bandwidth.

I. THEORETICAL ANALYSIS These capacitances are usually in order of pF, compare to C2

(12nF) the parasites capacitances can be missed when
calculating high cutoff frequency.

Using a pi hybrid model

Fig 9. First stage. Class A amplifier

In Fig 9. we see a class A amplifier, this circuit will define the

cutoff frequency

For low frequency

Fig 9. Pi model in high frequency

V OX
=RCM =1 KΩ
V th
 Power transistors Q1 and Q2 are the most important
1 components of the circuit, these transistors are expensive, then
FH= we need to find a way to protect them from overcurrent and
2 π (1 Kx 12 n) short-circuits.

If there´s no overcurrent, current that flows through Q5 is in

G0=10.81 order of pA and all current that RL needs is being transmitted
Then: by Q2.
F L =104.70 Hz
If there´s overcurrent, current through Q5 increase and current
F H =1 3.26 K Hz through Q2 decrease. If the overcurrent remains for a long
period of time, the resistors R6 and R7 open because they
cannot withstand the power they must dissipate and Q2 ,Q4
For second stage: Class AB amplifier transistors stop operating.

II. SIMULATIONS

First stage: analysis Class A amplifier:

Fig 11. Second stage. Class AB amplifier

e i=V d 1+V d 2 +(0.56+ 0.82) β 1 β 2 i b 1

Fig 13. Transient analysis Class A amplifier
e o=0.82 β 1 β 2 ib 1
Like we see in theoretical analysis in first stage the gain is
10.81 and in Fig 12 we have a gain approximately of 10.
Then, gain:

eo
=G 2=0.94
ei

Overcurrent protection
Cutoff frequency

Fig 15. Bode diagram

Theoretical Simulation
Fl 104.70 Hz 94.054Hz
Fh 13.26kHz 15.866kHZ

Second stage: analysis Class AB amplifier:

 Fig 15. Transient analysis Class AB amplifier

Otherwise like we see in theoretical analysis in second stage

the gain is 0.94 and in Fig 13 we have a gain approximately of
1. It is almost like a emitter follower. Remembering, the
complementary symmetric amplifier is not a voltage amplifier,
but rather is a current amplifier.

In Fig 16. Current flows through Q1 and Q3 is in order of uA.

Then:

Fig 16. Current in Q1 and Q3

( I 0−I B ) . R5 +3 V D =6 V be
I 0 R5 +3 V D −6 V be
In Fig 17. Current flows through RL is in order of A.
→ I B=
R5
Expressing d I B as a function of temperature we have:
d IB d I B d I CBO d I B d V be d IB d VD
= . + . +γ .
dT d I CBO dT d V be dT d V D dT
d V be dV D
−6 . +3 γ
d IB dT dT
→ =
dT R5
Fig 17. Transient analysis in RL Also
d Ic d IB d I CBO
III. PREVIOUS REPORT =β +( β+1)
dT dT dT
1. Obtain the equation dIc/dT for the power amplifier; d Ic β dV D d V be dI
estimate that Q1, Q2, Q3 and Q4 they have roughly equal
temperatures.
→ =
dT R5
3γ( dT
−6 .
dT )
+ ( β +1 ) . CBO
dT
Let’s analyze this figure
2. Design the amplifier circuit ARGOS 2 under the
following requirements.
Operation source ± 12V
LOAD 8Ω
Active elements Q1, Q7: BD135
Q3: BD136
Q5: 2N2222A
Q2: TIP41
Q4: TIP42
Q6: 2N2907
Signal prove 1Vp, 1KHz
Currents I CQ greater than or equal to 8mA NODE DC VOLTAGE
Cutoff frequency fi=100Hz and fs=15KHz V7 1.647 V
Mid frequency gain 10 (approx.) V(4,3) 10.435 V
Overcurrent protection 1A on load V(2,14) 1.658 V
V11 0.393852 V
AC (BODE PLOTS):
-V2/V3

-V10/V11

v(10)/v(11)
3. Simulate the ARGOS 3 circuit in Micro-Cap and print x1(Hz) 58.158k
the diagrams of the following parameters. y1(dB) 0.562018
DC: x2(Hz) 4.295G
-V7 -V(4,3) -V (2,14) -V11 y2(dB) -2.436
dx(Hz) 4294.942M
dy(dB) 2.998
dy/dx 0.698n
1/dx 0.2328n

-V7

v(7)
x1(Hz) 95.104
y1(dB) 16.195
x2(Hz) 15.068k
y2(dB) 16.190
 dx(Hz) 14.973k the most efficient configuration for transforming
DC power from the power supply to the AC power
dy(dB) 0.005
driving the load.
dy/dx 0.3339u
1/dx 0.0667m
 The diodes, in conjunction with resistors R3 and R5,
constitute the biasing network to make sure these is
-V11 always a VBE approx 0.7V across both transistors.
That way one BJT is always on, and the cross-over
region is eliminated.

V. BIBLIOGRAPHY
 Rashid, M., 2011. Microelectronic Circuits. 2nd
ed. Stamford: Cengage Learning
 Boylestad, R. and Nashelsky, L.,
v(11) 2013. Electronic Devices And Circuit Theory.
x1(Hz) 95.353 11th ed. Upper Saddle River, N.J.: Pearson
y1(dB) 14.674 Prentice Hall.
x2(Hz) 15.038k
y2(dB) 14.664
dx(Hz) 14.943k
dy(dB) 0.010
dy/dx 0.6692u
1/dx 0.06692m

4. Obtain the maximum operating at junction B-E of Q1,

Q2, Q3, Q4 and Q7

B-E DC VOLTAGE
Q1 0.641 V
Q2 0.584965 V
Q3 0.59056 V
Q4 0.428351 V
Q7 0.719 V

IV. CONCLUSIONS
 The frequency response is affected by the
temperature of the transistors. At high temperatures
the circuit loses all its gain properties.

 Needs to choose carefully the transistors for the AB

class amplifier. We must check the maximum
current supported for each transistor.

 Resistors R6 , R7 and transistors Q5 , Q6 works like

a overcurrent protection circuit.

 In most applications where AC power is driving a

load, a complementary symmetry (push-pull) power
amplifier is employed. This amplifier usually has a
voltage gain of one, and a large current gain. It is