HRISHIKESH DESHPANDE

Contact Career Objective

Address: To be a part of an esteemed Organization and apply my skills into
Plot No. 8A Veershiav Nagar Vijapur action towards education by utilizing my educational background
Road, Solapur-413004 and to expand my knowledge.

Phone:
+91- 9420246590
Academics
Email: Qualification Institute name Year of passing CGPA/Percent
deshpandehrishikesh23@gmail.com
M.tech(VLSI V.I.T. Chennai 2020 8.30
Linkedin: Design)
https://www.linkedin.com/in/hrishikesh-
deshpande-50a47bb6/ B.E.(E&TC) University of 2016 64.67%
Pune
Skype: live:deshpandehrishikesh23 H.S.C Maharashtra 2012 68.50%
Board
S.S.C Maharashtra 2010 89.27%
Board

Tools/OS Experience
Languages: C,Verilog.
Role: Project Intern – 01/08/2019 to29/05/2020.
Tools: Cadence Virtuoso , Eldo ,
® Company: ST Microelectronics, Greater Noida
Calibre, Xillinx, Quartus. Standard Cell Back End Team (TR&D
Group).
OS: Microsoft Windows, Unix(RedHat). Layouts of different standard cells at 28nm and
40nm Technology.

Validation of standard cells using Calibre tool (DRC,

LVS checks).
Technical Skills PMB: Validaton of different process monitoring sensor like
Areas of Interest:
CPR(Crictical Path Replica):Behaviour analysis of
different logics and longest path of circuit
Standard Cell Layouts
GO1 & GO2 Sensors: For Behavior annaysis of Pmos and
Physical Verification (DRC,
Nmos and there leakage
LVS Checks).

Physical Design
Projects
STA
1. Title: Design Kit Covalidation of standard cell
DFT libraries ,2019-present

Description: The main objective of the project is to

improve the shape of MOSFET before fabrication.
During abutment the shapes were improved.
Tool used: Cadence Virtuoso®.
Workshops /Training Projects
Attended “VLSI Make-a-thon III” based on 2. Title: Design of low power true single phase clocking
Cadence tools organized by school of flip-flop 2019
Electronics Engineering (SENSE) at VIT-
Description: The main objective of the project is to
Chennai during and March, 2019.
minimize power consumption and delay of the design
Participated in Value Added programme on
of D-flipflop. The power consumption is even more
“System Verilog Design, Development and
reduced and also reducing the number of transistors.
Verification” organized by school of Electronics
Engineering (SENSE) at VIT-Chennai from Tool used: Cadence Virtuoso®.
14.02.2019 to 16.02.2019.
3. Title: Energy Efficient Shift register using adiabatic
Attended workshop on “Layout design,
logic
verification and post layout simulation using
®
CADENCE Tools “organized by school of Description: In order to reduce the power dissipation
Electronics Engineering (SENSE) at VIT-Chennai and reuse the energy in more proper order we go design
during January, 2019. of shift register using adiabatic logic. And energy
consumption was pretty much less compared to
Attended “Contest on Verilog conventional circuit.
Programming and FPGA based System
Design” organized by school of Electronics
Tool used: Cadence Virtuoso®.
Engineering (SENSE) at VIT-Chennai
during and October, 2018.
4 . Title: Design of various adiabatic logic families,2018
Vocational training at Doordarshan
Description: In this project , we have compared all the
Kendra Mumbai(Worli) during 24th
logic families of adiabatic logics .We estimated the
November 2015 to 1st december 2015.
power, energy, delay performance of the adiabatic

Achievements circuits.
Tool used: Cadence Virtuoso®.
Won the interdeparmental cricket championship
at S.I.T Lonavala. B.E(E&TC).

Won cricket champioship for three

consecutive years 2008,2009,2010. Declaration
Won 2nd Prize in reading Competition I hereby declare that all the particulars furnished above are true,
(Marathi) at 10th Standard.
genuine and reliable to the best of my knowledge.

Won Certifiacte of merit for all India Quiz

Competetion.
Signature:Hrishikesh Deshpande
Won runner’s up for throwball competition.
Date:
Place: Solapur
Personal details
Date Of Birth: 23rd November 1994
Blood group: B positive
Languages: English, Hindi, Marathi
Marital: Single

Strength: Self Motivated, Adaptive,

Quick Learner, Time management