1.

A power-aware signed 2-dimensional bypassing multiplier for video/image processing

Gang-Neng Sung Yu-Cheng Lu Chua-Chin Wang
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

This paper appears in: Consumer Electronics (ICCE), 2010 Digest of Technical Papers
International Conference on
Issue Date: 9-13 Jan. 2010
On page(s): 511 - 512
Location: Las Vegas, NV
Print ISBN: 978-1-4244-4314-7
INSPEC Accession Number: 11146234
Digital Object Identifier: 10.1109/ICCE.2010.5418863
Date of Current Version: 22 February 2010

ABSTRACT This paper presents a power-aware signed digital multiplier design by taking
advantage of a 2-dimensional bypassing method dedicated for local multiplications widely used
in FFT/IFFT operations of video/image processing. The proposed low power multiplier is carried
out by Baugh-Wooley algorithm using novel 2-dimensional bypassing cells. The proposed
bypassing cells constituting the multiplier skip redundant signal transitions when the horizontally
(row) partial product or the vertically (column) operand is zero.

FPGA implementation of pipelined 2D-DCT and quantization architecture for JPEG image
compression
Kusuma, E.D. Widodo, T.S.
Electr. Eng. Dept., Gadjah Mada Univ., Yogyakarta, Indonesia

This paper appears in: Information Technology (ITSim), 2010 International Symposium in
Issue Date: 15-17 June 2010
Volume: 1
On page(s): 1 - 6
Location: Kuala Lumpur
ISSN: 2155-897
Print ISBN: 978-1-4244-6715-0
INSPEC Accession Number: 11513646
Digital Object Identifier: 10.1109/ITSIM.2010.5561411
Date of Current Version: 02 September 2010

ABSTRACT
Two dimensional DCT takes important role in JPEG image compression. Architecture and VHDL
design of 2-D DCT, combined with quantization and zig-zag arrangement, is described in this
paper. The architecture is used in JPEG image compression. DCT calculation used in this paper is
made using scaled DCT. The output of DCT module needs to be multiplied with post-scaler value
to get the real DCT coefficients. Post-scaling process is done together with quantization process.
2-D DCT is computed by combining two 1-D DCT that connected by a transpose buffer. This
design aimed to be implemented in cheap Spartan-3E XC3S500 FPGA. The 2-D DCT
architecture uses 3174 gates, 1145 Slices, 21 I/O pins, and 11 multipliers of one Xilinx Spartan-
3E XC3S500E FPGA and reaches an operating frequency of 84.81 MHz. One input block with 8
× 8 elements of 8 bits each is processed in 2470 ns and pipeline latency is 123 clock cycles.

Low-cost low-power bypassing-based multiplier design

Jin-Tai Yan; Zhi-Wei Chen;
Dept. of Comput. Sci. & Inf., Chung-Hua Univ., Hsinchu, Taiwan

This paper appears in: Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International
Symposium on
Issue Date: May 30 2010-June 2 2010
On page(s): 2338 - 2341
Location: Paris
Print ISBN: 978-1-4244-5308-5
INSPEC Accession Number: 11463201
Digital Object Identifier: 10.1109/ISCAS.2010.5537190
Date of Current Version: 03 August 2010

Data acquisition and VGA display controller based on NiosII

Enrang Zheng Zelin Song Lingkun Ma
Coll. of Electr. & Commun. Eng., Shaanxi Univ. of Sci. & Technol., Xi'an, China

This paper appears in: Signal Processing Systems (ICSPS), 2010 2nd International Conference
on
Issue Date: 5-7 July 2010
Volume: 3
On page(s): V3-417 - V3-421
Location: Dalian
Print ISBN: 978-1-4244-6892-8
INSPEC Accession Number: 11516475
Digital Object Identifier: 10.1109/ICSPS.2010.5555721
Date of Current Version: 23 August 2010

The design of image acquisition and display system

Song Gu; Zhou Hulin;
Dept. of Electron. Eng., Univ. of Electron. Sci. & Technol. of China, Zhongshan, China

This paper appears in: Education Technology and Computer (ICETC), 2010 2nd International
Conference on
Issue Date: 22-24 June 2010
On page(s): V5-23 - V5-26
Location: Shanghai
Print ISBN: 978-1-4244-6367-1
INSPEC Accession Number: 11523100
Digital Object Identifier: 10.1109/ICETC.2010.5529954
Date of Current Version: 29 July 2010
Investigation on Antenna Systems for Car-to-Car Communication
Pontes, Juan; Reichardt, Lars; Zwick, Thomas;
Institute fur Hochfrequenztechnik und Elektronik (IHE), Karlsruhe Institute of Technology
(KIT), 76127 Karlsruhe, Germany

This paper appears in: Selected Areas in Communications, IEEE Journal on

Issue Date: January 2011
Volume: 29 Issue:1
On page(s): 7 - 14
ISSN: 0733-8716
Digital Object Identifier: 10.1109/JSAC.2011.110102
Date of Current Version: 30 December 2010

Wideband Near-Field Data Transmission Using Pulse Harmonic Modulation

Inanlou, F.; Ghovanloo, M.;
GT-Bionics Lab, School of Electrical and Computer Engineering at the Georgia Institute of
Technology, Atlanta, GA, USA

This paper appears in: Circuits and Systems I: Regular Papers, IEEE Transactions on
Issue Date: Jan. 2011
Volume: 58 Issue:1
On page(s): 186 - 195
ISSN: 1549-8328
Digital Object Identifier: 10.1109/TCSI.2010.2055351
Date of Publication: 03 August 2010
Date of Current Version: 30 December 2010
Sponsored by: IEEE Circuits and Systems Society

Performance of DCSK Cooperative Communication Systems Over Multipath Fading

Channels
Xu, W.; Wang, L.; Chen, G.;
Dept. of Communication Engineering, Xiamen University, Fujian, China

This paper appears in: Circuits and Systems I: Regular Papers, IEEE Transactions on
Issue Date: Jan. 2011
Volume: 58 Issue:1
On page(s): 196 - 204
ISSN: 1549-8328
Digital Object Identifier: 10.1109/TCSI.2010.2071730
Date of Publication: 11 November 2010
Date of Current Version: 30 December 2010
Sponsored by: IEEE Circuits and Systems Society