VLSI DESIGN

Unit- IV
Bits

1. Static complimentary gates are static because they don’t depend on stored charge for their operation.
2. The two important characteristics of a logic circuit are layout area and delay
3. A static complimentary gate is divided into pull up network made of p-type transistor and a pull down
network made of n-type transistor.
4. Delay is generally used to mean the time it takes for a gate’s output to arrive at 50% of its final value.
5. Transition time is generally used to mean the time it takes for a gate to arrive at 10% or 90% of its final
value.
6. The first model used to compute delay and transition time is RC model.
7. The equation for delay time is td = 0.69(Rn+Rl)CL .
8. The speed power product is also known as power delay product.
9. The speed power product for static CMOS is independent of the operating frequency of the circuit.
10. The equation for speed power product is SP = CV2.
11. The method for power consumption reduction is voltage scaling.
12. Layout is designed to maximize performance and minimize area.
13. Cascaded inverter drive large capacitive load.
14. Transmission gate is the way to build switches from MOS transistors.
15. The difference between VOL and VIL is called noise margin.
16. The majority of chip designs are limited more by speed than by area.
17. We can also construct the pull up network of an arbitrary logic gate from its pull down network because
they are duals.
18. The two problems that are important to logic design are completeness and irredundancy.
19. Parallel transistors or sub networks implement OR function.
20. Series transistors or sub networks implement AND function.

Choose the correct option from following

21. Effective gate voltage Vg is____
a. 0
b. b.Vgs - Vt
c. c. Vgs+ Vt
d. d. none
22. Switch logic is based on _____
a. Pass transistor
b. Transmission gate
c. Both a & b
d. None
23. Load capacitance effects ____
a. Power consumption
b. Delay
c. Area
d. None
24. Thin film resistors have _______
a. High temperature coefficient
b. Low temperature coefficient
 VLSI DESIGN
Unit- IV
Bits

c. Both a & b
d. None
25. Gate delay is scaled by _____
a. β/α2
b. α/β2
c. β+α
d. α-β
26. Sheet resistance of epitaxial resistor is ____ohm/sqr
a. 32-40K
b. 32-35K
c. 56-60K
d. 1-10K
27. Transit time is the difference between ____ and ____
a. Rise time and conversion time
b. Rise time and fall time
c. Conversion time and fall time
d. None
28. The sheet resistance [ohm/sqr] as 5& mum process technology for n-diffusion is____
a. 10-50
b. 23-35
c. 70-80
d. 56-66
29. _____ is most effected by load capacitance in CMOS logic gate delays
a. Rise time
b. Fall time
c. Transition time
d. Conversion time
30. Transit time Tsd =____
a. L2/µVds
b. L3/µVds
c. Vds
d. None
31. Speed power product is also known as_____
a. Speed delay product
b. Power delay product
c. Power consumption product
d. Both a & b
32. In static complimentary gate + and GND stands for____
a. VDD and VGG
b. VDD and VSS
c. VGS and VDD
d. None
33. The formula used for speed power product is SP=________
a. CV
 VLSI DESIGN
Unit- IV
Bits

b. C/V
c. C*v
d. None
34. Logic delay increases as the _____ attached to the logic’s output become larger
a. Inductance
b. Capacitance
c. Resistance
d. Conductance
35. The transmission gate is the way to build switches from _____ transistors.
a. BJT
b. MOS
c. Bi-CMOS
d. None
36. Voltage scaling is a method to reduce _____
a. Speed
b. Delay
c. Power consumption
d. None
37. RC model is used to calculate______
a. Delay time
b. Transition time
c. Both a & b
d. None
38. Parallel circuit implements the _____ function
a. NAND
b. OR
c. AND
d. XOR
39. Series circuit implements the _____ function
a. NAND
b. OR
c. AND
d. XOR
40. The number of outputs that can drive from a transistor is known as______
a. Fan in
b. Fan out
c. Both a & b
d. None