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Published in IET Power Electronics
Received on 5th May 2010
Revised on 1st June 2011
doi: 10.1049/iet-pel.2010.0370

ISSN 1755-4535

Analysis of an asymmetric modulation method

for cascaded multilevel inverters
K. Ding1 K.W.E. Cheng1 Y.P. Zou2
1
Department of Electrical Engineering, The Hong Kong Polytechnic University, Hung Hom, Kowloon, Hong Kong,
People’s Republic of China
2
Department of Electrical Engineering, Huazhong University of Science and Technology, Hubei, Wuhan,
People’s Republic of China
E-mail: eekding@polyu.edu.hk

Abstract: Traditional means for implementing the switching of the power switches in multilevel converters is subharmonic pulse
width modulation (SHPWM) or triangulation approach involving a comparison between a target reference waveform and several
high-frequency carrier waveforms where all the power switches usually work at high switching frequency. The asymmetric
modulation method (AMM) which is derived from hybrid modulation method is illustrated. The contribution of asymmetric
modulation is to provide a general method of finding the locus of the output stepped-wave for the hybrid modulation method.
This study also provides an illustration of the ‘Mathematic expression of modulation process’ of SHPWM and AMM where it
is easy to see how the two techniques are related, and the output expression of the AMM method can be easily obtained from
the general N-level double-Fourier output expressions of SHPWM where cumbersome mathematical work has been avoided.
Through the analysis of modulation process for SHPWM and AMM, results show that the AMM is an improved version of
SHPWM method with optimised switching combination. Theoretical analysis, simulation and experimental results are
provided to validate the feasibility of the proposed analysis method.

1 Introduction In principle, all modulation methods aim to generate trains

The continuous growing of energy demand places increasing
pressure on the environment. Low-voltage inverters (below
380 VAC) are widely used in many areas. However, high-
voltage and high-power equipment, such as high-power
motor, high-power fan, compressed water pump and so on,
has lack of speed regulation and wastes a huge amount of
power. Multilevel converters promise to extend the well-
known advantages of low- and medium-power PWM
converter technologies into high-power applications. The
research on multilevel converters has received wide
attention, and is a hot point in power electronics for several
applications, such as medium-voltage motor drive, high-
voltage high-power inverter, dynamic voltage restorer, high-
power filter etc. The general concept of multilevel to
produce AC waveforms from small-voltage steps is to
utilise isolated DC sources or a bank of series capacitors.
The small-voltage steps yield waveforms with low
harmonic distortion as well as low dv/dt. The advantages of
multilevel converters compared with conventional two-level
converters are well known [1 – 4]. They present the
capability of increasing output voltage magnitude and
reducing the output voltage and current harmonic content.
The switching frequency and the voltage rating of each
power semiconductor are also reduced [4]. Three
main types of multilevel converters, that is, diode-clamp
[5], flying-capacitor [6, 7] and cascade converter with
separated DC sources [1, 2], have been reported.
of pulses with a time average that approximates a target
reference waveform at any instant [8, 9]. The performance
of the output multilevel voltage principally depends on the
capability of the electronic control circuit to define the
switching instants of the power stage. The controller
outputs a train of pulses with a time average that
approximates a sinusoid [10]. Based on the conventional
carrier-based sinusoidal PWM (SPWM) method, several
multilevel modulation methods have been proposed to
reduce the distortion in multilevel inverters [11 – 13]. Up to
now, a number of modulation methods have been proposed
for multilevel inverters: they are subharmonic PWM
(SHPWM) [14], space-vector PWM, selective harmonic
elimination, space-vector control [15 – 17], hybrid
modulation methods [16, 18– 21] etc.
The asymmetric modulation method (AMM) is derived
from the hybrid modulation method [16, 18 – 20]. The basic
concept of the AMM is to use minimal- or less-power cells
to generate high-frequency PWM waveforms, whereas the
other cells just generate low-frequency stepped waveform,
and to ensure that the overall output synthesised voltage to
be full PWM-modulated waveform. For SHPWM method,
all the power cells need to be operated at high frequency.
This paper proposes an analytical method for AMM based
on the topology of cascaded multilevel inverters [1, 2].
SHPWM method [14], which is a branch of carrier-based
sinusoidal PWM method, is described and compared with
the proposed asymmetric method. Theoretical analysis and

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& The Institution of Engineering and Technology 2011 doi: 10.1049/iet-pel.2010.0370
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derivation, based on an example of a seven-level cascade
multilevel inverter, have been conducted. By the analysis of
modulation process and experiments for SHPWM and
AMM, results show that the synthesised output waveforms
by using the two modulation approaches contain the same
harmonic content.

1.1 Traditional seven-level cascade multilevel

inverter

A traditional single-phase seven-level cascade multilevel

inverter [1, 2] is composed of three H-bridge power
converters that are connected in series where each of the
converter processes the separated DC sources. This is
illustrated in schematic diagram as shown in Fig. 1. The
output voltage is calculated by adding up the output of each
of the individual converters. For example, assuming the DC
voltage for each DC source is E, and by synthesising the
output voltage levels, the voltage level of +3E, +2E, +E,
0, 2E, 22E, 23E levels can be generated by switching
process. The seven-level output voltage can be
approximated to a sinusoidal waveform with the application
of proper control method to the topology.
The output voltage of a given multilevel converter can be
calculated [3] from Fig. 2 Principle of subhamonic PWM method for seven-level
  cascade inverter (carrier disposition: PH)
N −1
Vout = S− E (1)
2
the carrier set. The modulation wave is a sinusoid of
frequency f0 and amplitude A0 . At every instant each carrier
where Vout is the output of the multilevel converter, N is the is compared with the modulation waveform. Comparison
number of the output levels; S the switching state that operation triggers to switch the device on if the reference
ranges from 0 to N 2 1 and E is the minimum voltage level signal is greater than the triangular carrier assigned to that
that the multilevel converter can produce. device level; otherwise, the device is switched off. The
following illustrates the procedure of obtaining the
1.2 SHPWM method switching states:
A seven-level inverter is considered in Fig. 1 where the
Traditional means for implementing the switching algorithm output voltage Vout of the inverter is the summation of the
of the multilevel power converters is ‘Subharmonic PWM power cell outputs V1 , V2 and V3 . Six triangular carriers in
(SHPWM) [14]’ or ‘triangulation’ approach involving a PH disposition are compared with a sinusoid modulation
comparison between only one modulation wave per phase waveform shown in Fig. 2. The amplitude of the triangle
and several high-frequency carrier signals as illustrated by carrier waveform is E, then
Fig. 2. Three carrier dispositions are normally applied: the
phase homology (PH), alternative phase (APO) and phase ⎧
opposition (PO). For an N-level inverter, N 2 1 triangular ⎪
⎪ V = Vtri+2 + E
⎪ tri+3
⎪
carrier of the same frequency fc and the same peak-to-peak ⎨ Vtri+2 = Vtri+1 + E
amplitude E, are disposed so that the bands they occupy are Vtri+1 = Vtri−1 + E (2)
contiguous. The zero reference is placed in the middle of ⎪
⎪
⎪
⎪ V = Vtri−2 + E
⎩ tri−1
Vtri−2 = Vtri−3 + E

From (1) and Fig. 2, when Vo(desired) . Vtri+3 the switching

state S is 6, the output voltage of the converter Vout is +3E,
when Vtri+3 ≥ Vsin . Vtri+2 , the switching state S is 5, Vout
is +2E, when Vsin ≤ Vtri23 , the switching state S is 0, the
output voltage Vout is 23E. So, the switching states in the
seven-level cascaded inverter can be defined as

⎧
⎪
⎪ 0 Vtri−31 ≥ Vo(desired)
⎪
⎪ Vtri−2 ≥ Vo(desired) . Vtri−3
⎪
⎪ 1
⎪
⎪ Vtri−1 ≥ Vo(desired) . Vtri−2
⎨2
S= 3 Vtri+1 ≥ Vo(desired) . Vtri−1 (3)
⎪
⎪ Vtri+2 ≥ Vo(desired) . Vtri+1
⎪
⎪ 4
⎪
⎪
⎪
⎪ 5 Vtri+3 ≥ Vo(desired) . Vtri+2
Fig. 1 Single-phase seven-level cascade multilevel inverter ⎩
SHPWM method for seven-level cascade inverter 6 Vo(desired) . Vtri+3

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So, the output voltage for seven-level cascaded multilevel
converter using the SHPWM method can be expressed as
 
7−1
Vout = S− E = (S − 3)E (4)
2
Different switching combinations can be selected according
to the switching state ‘S ’.
2 Asymmetric modulation method
When applying the switching combinations by the SHPWM
method to power devices of the seven-level inverter, all the
switches are operating at high frequency. Based on the
study of a seven-level cascaded multilevel converter
(Fig. 1), an AMM which is derived from the hybrid
modulation method [16, 18– 21] is illustrated. The
contribution of asymmetric modulation is to provide a
general method of finding the locus of the output stepped-
wave for the hybrid modulation method where ‘Magnitude
Condition’ and ‘Level Condition’ are used for defining the
boundary of the output waveforms of each cell.
2.1 Level resolution and the definition of the
basic cells
As shown in Fig. 2, assuming the desired output voltage
Vo(desired) is sinusoidal waveform, V1 , V2 and V3 are the
output voltage of cell one, cell two and cell three,
respectively. V1(desired), V2(desired) and V3(desired) are the
desired output voltage of three cells, respectively.
Obviously, the output voltage Vout of the inverter is the
summation of V1 , V2 and V3 . The minimum step voltage of
the whole inverter output voltage is the minimum-level
resolution, in brief ‘level resolution’. As shown in Fig. 2,
the level resolution of the seven-level inverter is E. A basic
cell with a single voltage source E can output 2E, 0 and
+E voltage levels. Obviously, cell one, cell two and cell
three in Fig. 1 are all the basic cells.
2.2 Synthesised stepped waveform locus of cell
one and cell two
The basic operation of the AMM method in a converter, as
shown in Fig. 1 is as follows. The power switches of cell
three is operated at high-frequency and output high-
frequency PWM waveforms; whereas the stepped waveform
is acquired by synthesising the output of cell one and cell
two. As cell one and cell two both output stepped voltage
and no modulation process is needed, the desired output
voltage is the same as output voltage of the two cells, that is

V1 = V1(desired)
(5)
V2 = V2(desired)
Because of the symmetrical characteristic, only a quarter of a
cycle will be analysed below and overmodulation is not
considered herein.
Obviously, V3(desired) can be obtained by subtracting the
desired stepped waveform of V1 + V2 from the command
sinusoidal waveform of Vo(desired) . V3(desired) is also used to
compare with the triangle waveform Vtri+1 and Vtri21 . As
the output voltage of V3 can only output 2E, 0, E, three
levels, a value larger than E of V3(desired) will lead to
overmodulation. To avoid such conditions, the range of
76
& The Institution of Engineering and Technology 2011
V3(desired) is limited such that its magnitude must be equal to
or smaller than level resolution E. So, there are some
limitations of the selection for the shape or the locus of
synthesised stepped waveform of summation of V1 and V2 ,
V1 + V2 . The resultant waveform V3(desired) , which is
acquired by subtracting the selected stepped waveform from
the command waveform, must be equal to or smaller than
E, namely
Condition I
|Vo(desired) − (V1(desired) + V2(desired) )| ≤ E (6)
Condition I is called ‘Magnitude Condition’, and the output
synthesised stepped waveform of V1 + V2 can only be
limited to 22E, 2E, 0, +E, +2E, five levels. So,
Condition II can be acquired.
Condition II: The desired output levels of the synthesised
stepped waveform of V1 + V2 are limited to the ranges of
22E, 2E, 0, +E, +2E, five levels. The locus of the
synthesised stepped waveform can be changed among all
the five levels, 22E, 2E, 0, +E, +2E, or just some of
them, such as 22E, 0, +2E. Condition II can be called
‘Level Condition’.
Based on the two conditions mentioned above, the scope of
the desired output synthesised stepped locus of V1 + V2 can
be easily acquired, as shown in the shaded area (including
borderline) in Figs. 3a – c. For easy analysis, the intercept
point of horizontal line of levels 0, +E, +2E with
sinusoidal waveform are marked, viz. point A, B, C in Fig. 3.
As shown in Fig. 2, assuming the desired output voltage of
the inverter is
Vo(desired) = M × 3E sin vt (7)
where M is the modulation index range from 0 to 1.
Based on the satisfactory scope of the stepped locus as
shown in Fig. 3, Fig. 4a gives the first quarter stepped
locus or output stepped waveforms of V1 + V2 that meets
the magnitude and level condition mentioned above. In the
figure, ( y1 , u1) is the crossing point of the stepped
waveform at the first jump edge with the sinusoidal
waveform. ( y2 , u2) is the second-crossing point of the
stepped waveform at the second jump edge with
the sinusoidal waveform. Obviously, when y1 ¼ y2 ¼ E, the
stepped waveform only jump one time in the first quarter-
cycle as illustrated in Fig. 4c. Subtracting the stepped
waveform from the sinusoidal command waveform, the
command waveforms of V3(desired) shown in Figs. 4b and d
are yielded.
3 Comparison of the modulation process of
the SHPWM method and the asymmetric
method
It is interesting to note that investigations and comparison of
PWM modulation strategies are always involved with
considerable mathematical works [18, 20, 22– 26]. For
many modulation methods, it has the possibility that the
so-called ‘new’ or ‘improved’ PWM techniques are often
only a straightforward variation or a subset of the previous
approach [8, 17]. In this paper, by using the ‘Mathematic
expression of modulation process’, it can be very easy to
see how the AMM and SHPWM techniques are related.
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Fig. 3 Locus of V1 + V2 output stepped wave

2
a ,M ≤1
3
1 2
b ,M ≤
3 3
1
c 0≤M ≤
3

Fig. 4 V1 + V2 output step waveform and command voltage of

V3(desired)
a V1 + V2 output step waveform (0 ≤ y1 , E, E ≤ y2 , 2E)
b Command voltage of V3(desired) (0 ≤ y1 , E, E ≤ y2 , 2E)
c V1 + V2 output step waveform (y1 ¼ y2 ¼ E)
d Command voltage of V3(desired) (y1 ¼ y2 ¼ E) Fig. 5 First quarter-cycle of the modulation process for the
SHPWM method
a Output desired voltage and high frequency triangle carrier waveforms
3.1 Modulation process of the SHPWM method b Output step waveform

Considering the first quarter-cycle of the sinusoidal waveform

of the SHPWM method as illustrated in Fig. 2, the amplitude
of the triangle carrier waveform is E. In the first quarter part as
shown in Fig. 5, and from Fig. 5 and from (3) and (4), one
3.2 Modulation process of the asymmetric PWM
obtains
⎧ method with y1 ¼ E, y2 ¼ 2E
⎪
⎪ 3 V ≥V .V
⎨ 4 Vtri+1 ≥ Vo(desired) . Vtri−1 The first quarter-cycle of the modulation process for AMM
S= tri+2 o(desired) tri+1
(8) when y1 ¼ E, y2 ¼ 2E is shown in Fig. 6, oblique line
⎪
⎪ 5 V ≥ V . V
⎩6 tri+3
V
o(desired)
.V
tri+2
region shows the stepped waveform synthesised by power
o(desired) tri+3 cell one and cell two.
and As can be seen from Fig. 6, the output voltage of the whole
converter and the desired output voltage of V3 in different
Vout = (S − 3)E (9) ranges are
for the period 0 ≤ vt ≤ u1
In terms of switching at the intersection of the desired voltage
and high-frequency triangle carrier waveforms, substituting 
(8) into (9) gives the output voltage modulation expression Vout = V3
(11)
of the whole cascaded converter when using SHPWM Vo1 = Vo(desired)
method in the first quarter-cycle.
⎧ for the period u1 ≤ vt ≤ u2
⎪
⎪ 0 V ≥V .V
⎨ +E Vtri+1 ≥ Vo(desired) . Vtri−1
Vout = tri+2 o(desired) tri+1
(10) 
⎪
⎪ +2E Vtri+3 ≥ Vo(desired) . Vtri+2 Vout = V3 + E
⎩ +3E V .V Vo2 = Vo(desired) − E
(12)
o(desired) tri+3

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From (2) and substituting (13) into (18), and for the period
u2 ≤ vt ≤ p/2, gives

+2E Vtri+2 , Vo(desired) ≤ Vtri+3
Vout = (19)
+3E Vtri+3 , Vo(desired)

Thus, from (15), (17) and (19), for the period of the first
quarter-cycle, the output voltage modulation expression in
terms of triangle carrier waveforms can be expressed as
⎧
⎪
⎪ 0 Vtri+1 ≥ Vo(desired) . Vtri−1
⎨ +E Vtri+2 ≥ Vo(desired) . Vtri+1
Vout = (20)
⎪ +2E
⎪ Vtri+3 ≥ Vo(desired) . Vtri+2
⎩
+3E Vo(desired) . Vtri+3

3.3 Modulation process of the asymmetric PWM

method when 0 ≤ y1 , E, E ≤ y2 , 2E
As can be seen from Fig. 7, the output voltage of whole
converter and the desired output voltage of V3 in different
ranges are
for the period 0 ≤ vt ≤ u1

Vout = V3
Fig. 6 First quarter of modulation process for AMM when y1 ¼ E, (21)
Vo1 = Vo(desired)
y2 ¼ 2E
a Stepped output waveforms of V1 + V2 and desired output voltage of the
whole converter, Vo(desired)
for the period u1 ≤ vt ≤ u2
b Desired output voltage of cell three, V3(desired) 
c Output voltage of cell three, V3 Vout = V3 + E
(22)
d Output voltage of the whole converter, Vout Vo2 = Vo(desired) − E

and for the period u2 ≤ vt ≤ p/2


Vout = V3 + 2E
(13)
Vo3 = Vo − 2E

In terms of switching at the intersection of a target reference

waveform and a high-frequency carrier, from Fig. 6, and for
the period 0 ≤ vt ≤ u1

0 Vtri−1 , Vo1 ≤ Vtri+1
V3 = (14)
+E Vtri+1 , Vo1 ≤ Vtri+2

Substituting (11) into (14), and for the period 0 ≤ vt ≤ u1 ,

gives

0 Vtri−1 , Vo(deisred) ≤ Vtri+1
Vout = (15)
+E Vtri+1 , Vo(deisred) ≤ Vtri+2

For the period u1 ≤ vt ≤ u2


0 Vtri−1 , Vo2 ≤ Vtri+1
V3 = (16)
+E Vtri+1 , Vo2 ≤ Vtri+2

From (2) and substituting (12) into (16), and for the period
u1 ≤ vt ≤ u2 , gives

+E Vtri+1 , Vo(deisred) ≤ Vtri+2
Vout = (17)
+2E Vtri+2 , Vo(deisred) ≤ Vtri+3 Fig. 7 First quarter of modulation process for AMM when
0 ≤ y1 , E, E ≤ y2 , 2E
For the period u2 ≤ vt ≤ p/2 a Stepped output waveforms of V1 + V2 and desired output voltage of the
 whole converter, Vo(desired)
0 Vtri−1 , Vo3 ≤ Vtri+1 b Desired output voltage of cell three, V3(desired)
V3 = } (18) c Output voltage of cell three, V3
+E Vtri+1 , Vo3 ≤ Vtri+2 d Output voltage of the whole converter, Vout

78 IET Power Electron., 2012, Vol. 5, Iss. 1, pp. 74– 85

& The Institution of Engineering and Technology 2011 doi: 10.1049/iet-pel.2010.0370
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and for the period u2 ≤ vt ≤ p/2 Thus, from (25), (27) and (29), for the period of the first
quarter, the output voltage expression in terms of triangle
 carrier waveforms can be expressed as
Vout = V3 + 2E
(23)
Vo3 = Vo(desired) − 2E
⎧
⎪
⎪ 0 Vtri+1 ≥ Vo(desired) . Vtri−1
⎨ +E Vtri+2 ≥ Vo(desired) . Vtri+1
In terms of switching at the intersection of a target reference Vout = (30)
waveform and a high-frequency carrier, from Fig. 7 and for ⎪ +2E
⎪ Vtri+3 ≥ Vo(desired) . Vtri+2
⎩ +3E
the period 0 ≤ vt ≤ u1 Vo(desired) . Vtri+3


0 Vtri−1 , Vo1 ≤ Vtri+1
V3 = (24) As it can be seen from (10), (20) and (30), and in terms of
+E Vtri+1 , Vo1 ≤ Vtri+2 switching at the intersection of the desired voltage and a
high-frequency triangle carrier waveforms, the AMM and
Substituting (21) into (24) and for the period 0 ≤ vt ≤ u1 the SHPWM method share the same output expression of
gives modulation process which obviously leads to identical
output waveform expression, even under double Fourier
approaches.

0 Vtri−1 , Vo(deisred) ≤ Vtri+1
Vout = (25)
+E Vtri+1 , Vo(deisred) ≤ Vtri+2

4 Double Fourier integral analysis of SHPWM

For the period u1 ≤ vt ≤ u2
method and the AMM method
⎧ Spectral analysis of the output voltage provides essential
⎨ −E Vtri−2 , Vo2 ≤ Vtri−1
information for design and optimisation of the whole
V3 = 0 Vtri−1 , Vo2 ≤ Vtri+1 (26)
⎩ multilevel system. The determination of the harmonic
+E Vtri+1 , Vo2 ≤ Vtri+2 frequency components of a PWM output is quite complex
and is often done by using a fast Fourier transformer
From (2) and substituting (22) into (26) gives analysis. Spectral analysis of the output voltage provides
essential information for design and optimisation of the
⎧ whole multilevel system.
⎪
⎨ 0 Vtri−2 , Vo(deisred) − E ≤ Vtri−1 As it can be seen from modulation expressions (10), (20)
Vout = E Vtri−1 , Vo(deisred) − E ≤ Vtri+1 and (30), the modulation process of AMM and the
⎪
⎩ +2E SHPWM method share the same modulation process which
Vtri+1 , Vo(deisred) − E ≤ Vtri+2 results in the same harmonic spectral of the converter’s
⎧
⎪
⎨ 0 Vtri−1 , Vo(deisred) ≤ Vtri+1 output voltage. From [8], the general solution for N-level
multilevel PH PWM under both linear and overmodulation
= E Vtri+1 , Vo(deisred) ≤ Vtri+2 (27)
⎪
⎩ +2E conditions is
Vtri+2 , Vo(deisred) ≤ Vtri+3

For the period u2 ≤ vt ≤ p/2 N ′E

vaz (t) = {M (p − 2x∗ − sin 2x∗ ) + 4 sin x∗ } cos(v0 t)
p
⎧ 1 
⎨ −E Vtri−2 , Vo3 ≤ Vtri−1 N ′E 4
V3 = 0 Vtri−1 , Vo3 ≤ Vtri+1 + sin([2n − 1]x∗ )
⎩
(28) p n=2 2n − 1
+E Vtri+1 , Vo3 

sin 2nx∗ sin(2[n − 1]x∗

−M + cos([2n − 1]v0 t)
From (2) and substituting (23) into (28), and for the period n [n − ]
u2 ≤ vt ≤ p/2, gives
8E 1
1 1
+ C cos([2m − 1]vc t)
Vout = V3 + 2E p2 m=1 2m − 1 k=1 m0
⎧
⎨ +E
⎪ Vtri−2 , Vo3 ≤ Vtri−1 2E 1
1 1
+ C cos([2mvc t + [2n + 1]v0 t)
= +2E Vtri−1 , Vo3 ≤ Vtri+1 p m=1 2m n=−1 meven nodd
2
⎪
⎩
+3E Vtri+1 , Vo3
⎧ 4E 1
1 1 1
+
⎨ +E
⎪ Vtri−2 , Vo(desired) − 2E ≤ Vtri−1 C
p2 m=1 2m − 1 n=−1 k=1 modd neven
= +2E Vtri−1 , Vo(desired) − 2E ≤ Vtri+1 (n=0)
⎪
⎩ +3E Vtri+1 , Vo(desired) − 2E × cos([2m − 1]vc t + 2nv0 t) (31)
⎧
⎨ +E
⎪ Vtri+1 , Vo(desired) ≤ Vtri+2
= +2E Vtri+2 , Vo(desired) ≤ Vtri+3 (29)
⎪
⎩ +3E where vc is the carrier angular frequency, v0 is the
Vtri+3 , Vo(desired) fundamental (sinusoid) angular frequency, m, n is the

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harmonic index variables. Noted that v0 , vc . Herein, N ¼ 7(N ′ ¼ 3) is considered. For linear
region, x∗ ¼ 0, substitute N ′ ¼ 3, and x∗ ¼ 0 in (31), gives
1 (see (32))
Cm0 = J ([2m − 1]N ′ pM ) cos k p
2k − 1 2k−1 where M ≥ 2/3 (to maintain seven-level modulation) [8].
 The most important modulation index ranges from 2/3 to 1
× cos k p − cos N ′ p sin([2k − 1]x∗ ) where a seven-level switched waveform can be acquired.
Otherwise, when modulation index below 2/3, the output
′     voltage level is smaller than 7, such as, when M ranges

N −1
h −1 from 0 to 1/3, three levels is acquired. When M ranges from
−2 sin [2k − 1] cos ′ cosh p 1/3 – 2/3, five-level output is obtained.
h=1
NM
Herein, modulation range 2/3–1 is considered, the harmonic
components P10(vc), P23(2vc + 3v0), P21(2vc + v0),
P12(vc + 2v0) and P32(3vc + 2v0) are investigated, where
fc ¼ 10 kHz, f0 ¼ 50 Hz vc ¼ 2pfc and v0 ¼ 2pf0 , P10(vc)
Cmeven nodd = J2n+1 (2mN ′ pM ) is the amplitude of the fundamental and directly proportional

to the modulation index M(M , 1), P23(2vc + 3v0),
sin(2[2n + 1]x∗ P21(2vc + v0), P12(vc + 2v0) and P32 (3vc + 2v0) are the
× cos np p − 2x∗ −
[2n + 1] amplitude of important sideband components at harmonics of

1 the modulating frequency of integer frequency ratio. Plots of
+ J2k−1 (2mN ′ pM ) the calculated harmonic values in terms of modulation index
k=1 M are given in Fig. 8.
(k=−n)
(k=n+1)
  5 Simulation validation
sin(2[k + n]x∗ sin(2[k − n − 1]x∗
× cos k p +
[k + n] [k − n − 1] Simulation research on switching waveforms is also responsible
for spectral analysis so as to avoid complicated mathematical
(see equation at the bottom of the page) derivation and operation. Simulation of seven-level cascade
and inverter using SHPWM and proposed asymmetric method are
investigated. Ideal switches and ideal DC-bus voltage sources
⎧   are assumed in the simulation in which deadtime and DC-bus
⎨ 1
voltage ripple have been ignored. The simulation conditions
arccos for M . 1(overmodulation)
x∗ = M for time-domain transient and Fourier analysis are the same in
⎩
0 for M ≤ 1(linearregin) both SHPWM method and AMM. Harmonic magnitude of
certain harmonics is shown in Table 1.
N ′ (N 2 1/2), where N is the number of voltage levels of the As it can be seen in the simulation results, magnitude of
cascaded multilevel converter. harmonic components, for SHPWM method under the

Cmodd neven = J2k−1 ([2m − 1]N ′ pM )


N ′ −1
[cos([n − k]p − cos N ′ p sin([2k − 1 − 2n]x∗ − 2Sh=1 sin{[2k − 2n − 1] arccos (h/N ′ M )} cosh p
× cos k p
[2k − 1 − 2n]

N ′ −1
[cos([n + k]p + cos N ′ p sin([2k − 1 + 2n]x∗ − 2Sh=1 sin{[2k − 1 + 2n] arccos(h/N ′ M )} cosh p
+
[2k − 1 + 2n]

    
8E 1
1 1
1 1
vaz (t) = 3ME cos (v0 t) + 2 J2k−1 ([2m − 1]3M p) 1 + 2 sin [2k − 1] arccos cos k p
p m=1 2m − 1 k=1 2k − 1 3M
   
2 2E 1
1 1
−2 sin [2k − 1] arccos cos k p cos ([2m − 1]vc t) + J (6mM p)
3M p m=1 2m n=−1 2n+1
1 
4E
1
1 1
× cos np cos ([2mvc t + [2n + 1]v0 t) + 2 J ([2m − 1]3M p)
p m=1 2m − 1 n=−1 k=1 2k−1
(n=0)


cos([n − k]p) + 2 sin([2k − 1 − 2n]arccos [(1/3M )]) cosk p − 2 sin([2k − 2n − 1] arccos [(2/3M )])
× cos k p
2k − 1 − 2n

cos ([n + k]p) + 2sin([2k − 1 + 2n] arccos [(1/3M )]) cos k p − 2 sin ([2k + 2n − 1] arccos [(2/3M )])
+
2k − 1 + 2n
× cos ([2m − 1]vc t + 2nv0 t) (32)

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 www.ietdl.org

Fig. 8 Harmonic magnitude against modulation index

a Magnitude of fundamental component P10(vc)
b Magnitude of sideband component P23 (2vc + 3v0)
c Magnitude of sideband component P21 (2vc + v0)
d Magnitude of sideband component P12 (vc + 2v0)
e Magnitude of sideband component P32 (3vc + 2v0)

Table 1 Simulated harmonic magnitude in terms of modulation index

Modulation Magnitude, V
index
P10 10 kHz P12 10.1 kHz P21 20.05 kHz P23 20.15 kHz P32 30.1 kHz

simulated harmonic magnitude by M ¼ 0.9 228.59 22.533 17.432 26.748 12.179

the subharmonic method M ¼ 0.8 206.04 12.866 33.045 27.962 2.3897
M ¼ 0.7 165.62 25.288 1.6989 5.0376 9.9589
simulated harmonic magnitude by M ¼ 0.9 228.59 22.533 17.432 26.748 12.179
the asymmetric method with M ¼ 0.8 206.04 12.866 33.045 27.962 2.3897
y1 ¼ E, y2 ¼ 2E M ¼ 0.7 165.62 25.288 1.6989 5.0376 9.9589
simulated harmonic magnitude M ¼ 0.9 228.59 22.533 17.432 26.748 12.179
by the asymmetric method with M ¼ 0.8 206.04 12.866 33.045 27.962 2.3897
y1 ¼ 0.63662E, y2 ¼ 1.5876E M ¼ 0.7 165.62 25.288 1.6989 5.0376 9.9589

asymmetric approach are all the same which verify the same
output expression of these modulation methods. Also, as it
can be seen from Fig. 8, mathematical calculation results by
using double Fourier output expression agrees very well
with simulation results.
6 Experimental validation
The seven-level cascaded inverter shown in Fig. 1 has been
built in the laboratory where experiments have been carried
out to verify the feasibility of the approach with using

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doi: 10.1049/iet-pel.2010.0370 & The Institution of Engineering and Technology 2011
www.ietdl.org
SHPWM and proposed asymmetric method. The DC bus
voltage of each inverter cell is 100 V. The load is an
inductive load with 100 V resistance and 4 mH inductance.
The modulation parameters for this study were M ¼ 0.9,
Fig. 9 Measured output PWM waveform for the seven-level
cascade inverter (SHPWM) Y: 100 V/div, X: 10 ms/div
a M ¼ 0.7
b M ¼ 0.8
c M ¼ 0.9
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& The Institution of Engineering and Technology 2011
0.8, 0.7, the modulating frequency fm ¼ 50 Hz, and the
triangle carrier frequency fc ¼ 10 kHz.
In relation to the modulation depths, the waveforms of the
output voltage in synthesis produced by the converter with
Fig. 10 Measured output PWM waveform for the seven-level
cascade inverter (AMM, M ¼ 0.7, y1 ¼ E, y2 ¼ 2E). Y: 100 V/div,
X: 10 ms/div
a M ¼ 0.7
b M ¼ 0.8
c M ¼ 0.9
IET Power Electron., 2012, Vol. 5, Iss. 1, pp. 74– 85
doi: 10.1049/iet-pel.2010.0370

Fig. 11 Spectral analysis for SHPWM method for experimental waveform in Fig. 9
a M ¼ 0.7
b M ¼ 0.8
c M ¼ 0.9
SHPWM method and AMM are shown in Figs. 9 and 10,
respectively. Figs. 11 and 12 show the spectral analysis of
corresponding waveforms, and in terms of the spectra of
the output voltage. Although practical experimental error
may cause error in the output harmonic components, still
we can see the results have strongly complimented the
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doi: 10.1049/iet-pel.2010.0370
www.ietdl.org
theoretical predictions of identical output expressions of
the two methods. As an example, The SHPWM of
M ¼ 0.8 shows THD ¼ 20.87% as illustrated in Fig. 11b.
The AMM of M ¼ 0.8 shows THD ¼ 20.98% as shown
in Fig. 12b. They are almost the same in THD and
spectrum.
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Fig. 12 Spectral analysis for asymmetric method for experimental waveforms in Fig. 10, (AMM, y1 ¼ E, y2 ¼ 2E)
a M ¼ 0.7
b M ¼ 0.8
c M ¼ 0.9

7 Conclusions illustrated. Magnitude and level conditions are employed to

analyse the output stepped locus of each power cell. To
An AMM has been studied and verified in this paper. avoid the circulating problem among cells, constraint
Definition of the basic cell and level resolution based on condition of the locus parameters of stepped waveforms
the study of a seven-level cascaded multilevel inverter is have been investigated. Theoretical analysis and derivation

84 IET Power Electron., 2012, Vol. 5, Iss. 1, pp. 74– 85

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of the AMM based on an example of a seven-level cascade
multilevel inverter has been demonstrated. In practical
application, the proposed AMM method can also be used in
design of multilevel cased converter for a number of
applications, such as medium-voltage inverter for motor
drive or solar-based multilevel grid-connected inverter
where only one cell of the inverter needs to be operated at
higher-switching frequency. The modulation process
expressions of SHPWM and AMM are illustrated.
Mathematical calculation and simulation study of the AMM
and SHPWM method have been conducted under the same
test conditions. Calculated harmonics magnitudes, simulated
and experimental results verified the proposed analytical
method for the asymmetric multilevel inverter.
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