ECE 4263/6263 Principles of VLSI Design: Irsim Tutorial (VER. 1.2)

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ECE 4263/6263

Principles of VLSI Design


UNIVERSITY
ELECTRICAL AND COMPUTER ENGINEERING

IRSIM TUTORIAL1 (VER. 1.2)


This document gives a very brief tutorial on the switch level simulator IRSIM. Refer to the IRSIM man
pages and documentation online for additional info.

Starting IRSIM
Make sure that you have defined the environment variable to point to the base IRSIM directory. This is
done on the MSU computer system by using the software environment utility “swsetup”. The command
is
swsetup ecad

IRSIM has the following usage:


IRSIM [-s] prm_file {sim_file} [-cmd file]
-s instructs IRSIM to stack series resistors
prm_file is the process dependent file describing FET electrical parameters
sim_file is the file that contains the circuit in an IRSIM netlist format
cmd_file is a file that contains IRSIM commands to execute

At the unix prompt type:


irsim c5n.prm myfile.irs

c5n.prm is a fabrication technology file (provided by the lab TA) and the .irs file is any IRSIM file. The
explicit path to the .prm file is not required if your ECAD environment variables are set correctly.
Alternately, you can make sure the .prm file is in the current directory. For example, if your .irs file is
named demo.irs type:
irsim c5n.prm demo.irs

IRSIM will tell you how many transistors you have and then display the IRSIM prompt shown below.
IRSIM>

Creating IRSIM files


IRSIM files are just text files that contain information about a circuit. They have the extension
.irs. The first time you use IRSIM, you will probably have to create the .irs file yourself using your
favorite text editor. Later you'll create it from schematic or layout generated in the ECAD tools.
This tutorial will simulate a static CMOS logic gate to perform AB + ABC . The NFETs are
connected ( A || B || C ) ↔ ( A || B ) and the PFETs are connected ( A ↔ B ↔ C ) || ( A ↔ B ) . Fig. 1 shows the
CMOS circuit that performs the required function.

1. Based, in part, on the tutorial located at http://velox.stanford.edu/

ECE 4263/6263 - PRINCIPLES OF VLSI DESIGN


The first step in creating a .irs file for this circuit is to label all the nodes. Label the power node
Vdd and the ground node Gnd. IRSIM is not case sensitive so vdd and gnd will work also. You can
label the other nodes anyway you want. Use any method you wish. For the circuit above, the inputs are
labeled a, b, c, and the output node is labeled f. Other internal nodes are labeled n1, n2, n3, and n4.
When using IRSIM, it is helpful to have the labeled circuit schematic available so that you know the
names of the nodes that you want to probe. The .irs file for the above circuit is shown below.
| units: 30 tech: scmos
| The line above must be included to define the size of lambda
|
| CMOS static logic for f = (A Bbar) + (Abar B Cbar)
|
p abar Vdd n2 2 12
p b n2 f 2 12
p a Vdd n3 2 12
p bbar n3 n4 2 12
p c n4 f 2 12
n a Gnd n1 2 4
n bbar Gnd n1 2 4
n c Gnd n1 2 4
n abar n1 f 2 4
n b n1 f 2 4
|
| inverter to create Abar
|
n a Gnd abar 2 4
p a Vdd abar 2 12
|
| inverter to create Bbar
|
n b Gnd bbar 2 4
p b Vdd bbar 2 12
|
| inverter to create Cbar
|

A
A
N4
B N2
N3
C B

f = AB + ABC
A B
N1

A B C

Figure 1 CMOS logic gate to perform AB + ABC

ECE 4263/6263 - PRINCIPLES OF VLSI DESIGN 2


n c Gnd cbar 2 4
p c Vdd cbar 2 12

The first line is a comment. Any line that begins with the vertical bar ’|’ is a comment. This first line says
that the technology used is scalable cmos. Transistors are specified as follows:
type g s d l w

where type is p for pmos and n for nmos. The g refers to the gate’s node name. Similarly, s refers to
the source’s node name, and d refers to the drain’s node name. This is why you need a labeled circuit
schematic to create a .irs file by hand. It is important that you get the connections correct. The l is the
transistor’s channel length and the w is the transistor’s channel width, both in lambda.
The first transistor specified in the example above is the top-left pmos transistor in the
corresponding schematic. Study the rest of the IRSIM file and the circuit. It is easy to see how the two
match. You can also enter in resistors and capacitors. See the IRSIM manual for the proper format to
create these elements. Considering just transistors, you are now ready to run IRSIM.

Creating IRSIM files from the Mississippi State University Cadence ECAD flow
Except for trivially small gates, IRSIM netlist will be machine generated by the MSU Cadence ECAD
tool suite. To create IRSIM compatible netlist, do the following steps:
1. Create a schematic in the Cadence tools. Be sure to create pins for circuit inputs and outputs. Create
“input/output” pins for the power supplies. IRSIM requires the power supply node and ground node
to be named “Vdd” and “Gnd”, respectively. It is good habit to always name your “digital” supplies
with these abbreviations.

Do NOT use the “bang” (!) suffix on node names. This practice leads to a high probabil-
ity of “floating” supply nodes as your designs become more hierarchical.

2. Extract your schematic to a HSPICE netlist using the Cadence tools.


3. At the unix prompt, use the sp2sim script to convert the newly created Cadence HSPICE netlist into a
more user-friendly HSPICE netlist and an IRSIM netlist.

! Information
sp2sim will give basic help using the command “sp2sim -h”.
Power supply nodes can be “renamed” to the IRSIM compatible names by
sp2sim -pVddNodeName -gGndNodeName

The steps above can be used to generate HSPICE and IRSIM netlists from layout views.

Running IRSIM
You can enter in commands interactively at the IRSIM prompt or you can run a script from a .cmd file.
The .cmd files contain commands that are exactly what you would type in at the IRSIM prompt.
Here is an example IRSIM session. The IRSIM> prompt precedes commands that were entered
interactively. Text preceded by the vertical bar | is output from IRSIM.

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*** IRSIM version 9.5 *** @ Tue Feb 6 16:05:30 2001
Read demo.irs lambda:0.30u format:MIT
13 nodes; transistors: n-channel=8 p-channel=8
parallel txtors:none
irsim> stepsize 1

The basic idea of IRSIM is that you tell it which nodes to pull high, which nodes to pull low, which nodes
to tristate, and then you tell IRSIM to run the simulation for a certain period of time. This period of time
is the stepsize. The above command tells IRSIM that the stepsize is 1ns. The default stepsize is 10ns.
irsim> w a abar

The command “w” tells IRSIM to watch the following nodes. So the above command tells it to watch the
nodes a and abar. IRSIM displays the nodes in the reverse order in the above command. Therefore the
output order will be abar a. Enter the watch nodes in any order you like.
irsim> d

“d” displays all the nodes that are being watched. You can also enter in something like “d a abar” which
tells IRSIM to only display nodes a and abar
a=X abar=X
time = 0.0ns

At time zero, the values of the nodes are all undefined. Now let’s set the value of the input a to logical
zero and “step” the simulator. The “s” command tells IRSIM to simulate for a certain period of time
previously defined by the stepsize command. The default value is 10 ns, but we set it to 1ns above.
irsim> l a
irsim> s
abar=1 a=0
time = 1.00ns

IRSIM displays the values of the nodes after each step because of the previous “w” command. The
current time is also displayed. Notice that a equals 0 and abar equals 1, as we would expect. Also, note
that time=1ns. This is the current simulation time now. Now let’s set the value of a to logical one and step
the simulator again.
irsim> h a
irsim> s
abar=0 a=1
time = 2.00ns

h sets the following nodes to a logic high value, and now abar equals 0. Finally, we will “high
impedence” the input a and step the simulator once more.
irsim> x a
irsim> s
abar=0 a=1
time = 3.00ns

ECE 4263/6263 - PRINCIPLES OF VLSI DESIGN 4


The value of a is still logical one because that was its previous state before we quit “driving” it. Thus,
abar still equals logical zero. To demonstrate, consider driving a to logical zero, stepping the simulator,
setting a to high impedence and stepping again. This is shown below:
irsim> l a
irsim> s
abar=1 a=0
time = 4.00ns
irsim> x a
irsim> s
abar=1 a=0
time = 5.00ns
irsim>

Exiting IRSIM
To exit IRSIM, simply type “exit” at the prompt.
irsim> exit
%

IRSIM will close all of its windows and return to the unix prompt.

Getting help in IRSIM


IRSIM has a very simple online help system. To obtain a list of IRSIM commands, type “help” at the
IRSIM prompt.
irsim> help
available commands:
! < << > ? @ activity alias ana analyzer assert assertWhen back c changes
clear clock d debug decay display dumph exit flush h has_coords help hist
inputs ires isim l logfile model p path powlogfile powstep powtrace print
printp printx q R readh report s set setlog setpath stats stepsize stop sumcap
t tcap time u unitdelay until V vector vsupply w wnet x Xdisplay

You can get help on a specific command by typing “help” followed by the command. For example, to get
help on the “h”, “l”, “x”, and “R” commands, type
irsim> help h
h node/vector... -> drive node/vector(s) to 1 (high)
irsim> help l
l node/vector... -> drive node/vector(s) to 0 (low)
irsim> help x
x node/vector... -> make node/vector(s) undriven (non-input)
irsim> help R
R [n] -> simulate for ’n’ cycles (default: longest sequence)
irsim>

Vectors in IRSIM
If you have a long list of inputs, it can be tiresome to keep using the “l” and “h” commands to set the
logic values. The “vector” command lets you group inputs together so that you can set them all quickly.
For example, using our demo.irs circuit in Fig. 1 again, consider the following IRSIM commands
*** IRSIM version 9.5 *** @ Tue Feb 6 16:13:07 2001
Read demo.irs lambda:0.30u format:MIT
13 nodes; transistors: n-channel=8 p-channel=8
parallel txtors:none
irsim> stepsize 10

ECE 4263/6263 - PRINCIPLES OF VLSI DESIGN 5


irsim> vector ins a b c
irsim> vector outs abar bbar cbar
irsim> l a b c
irsim> w outs ins
irsim> s
ins=000 outs=111
time = 10.00ns

The vector command creates a vector variable called ins. The ins is three bits consisting of a, b, and c.
The “l” command tells IRSIM to set the vector ins to 000. Therefore, a equals 0, b equals 0, and c
equals 0. The outs vector consists of the negated versions of a, b, and c. Therefore, the outs variable
equals 111. Now let’s set the middle bit of ins to logical one and step the simulator.

irsim> h b
irsim> s
ins=010 outs=101
time = 20.00ns

Now, outs equals 101 as we would expect. Using the “l” and “h” comamand repeatedly is getting old.
Let’s set the ins vector all at once. Use the “set” command to do this.
irsim> set ins 100
irsim> s
ins=100 outs=011
time = 30.00ns
irsim> inputs
h inputs: a
l inputs: c b
u inputs:
irsim>

Finally, the “inputs” command lists all of the driven inputs in IRSIM and shows which are driven high (h)
and which are driven low (l). It also shows which inputs are undefined (u).

Finding path delays in IRSIM


The path command shows the critical path for the last transition of a node. Using our demo.irs circuit
once more, try the following commands
*** IRSIM version 9.5 *** @ Tue Feb 6 16:22:01 2001
Read demo.irs lambda:0.30u format:MIT
13 nodes; transistors: n-channel=8 p-channel=8
parallel txtors:none
irsim> vector ins a b c
irsim> w a b c f
irsim> l a b c
irsim> s
f=0 c=0 b=0 a=0
time = 10.00ns
irsim> set ins 010
irsim> s
f=1 c=0 b=1 a=0
time = 20.00ns
irsim> path f
critical path for last transition of f:
b -> 1 @ 10.00ns , node was an input

ECE 4263/6263 - PRINCIPLES OF VLSI DESIGN 6


bbar -> 0 @ 10.04ns (0.04ns)
f -> 1 @ 10.05ns (0.01ns)

The path command shows the critical path for the last transition of a node f. The output shows that an
input node b changed to logic 1 at time = 10 ns. The node bbar then transitioned to logical low at time
= 10.4 ns. Finally, node f went to logical one at 10.05ns. Therefore, it took 0.05 ns to go from low to high
for the given input changes. Let’s try that again with node f going from high to low.
irsim> set ins 111
irsim> s
f=0 c=1 b=1 a=1
time = 30.00ns
irsim> path f
critical path for last transition of f:
a -> 1 @ 20.00ns , node was an input
f -> 0 @ 20.01ns (0.01ns)
irsim>

This time, the logic path that caused the output node f to change stages was shorted. This path delay was
0.01ns.
Sometimes you may want to find the worst case T plh or T phl . The path command helps you find
this number. You do this by setting the circuit to some state and then force inputs to change that will
cause a transition at the output. Some intelligence is required to figure out what the worst state is and
what combination of input changes will cause the slowest output transition.

Using the analyzer window


IRSIM has a built in graphical logic analyzer which runs under Xwindows to let you view
waveforms. The 'analyzer' command sets up the analyzer window
IRSIM> analyzer a b c f

This tells IRSIM to display the nodes a, b, c, and f in the analyzer window Go ahead and experiment
with the analyzer window. It's pretty easy to use. Here are some of the things that you can do.

Print the waveforms to a postscript file


Go to the “print” menu and select “file”. You will be asked for a filename. Hitting return selects
the filename shown in the parentheses at the bottom of the analyzer window. Once you have the
postscript file, you can print it out on one of the network printers using unix command “lpr”.

Setting the width


You can set the width of the view from either the menus or the slider on the bottom. From the
menus, select “window” and then “set width”. You will be asked to enter the width in time steps. Use the
“move to” option under the “window” menu to move to the desired time. You can also use the “zoom”
menu to zoom in and out.
The best way to get a feel for the slider on the bottom is to play with it. Using the left mouse
button expands the view or shortens the view to the left depending on where you click. Clicking using

ECE 4263/6263 - PRINCIPLES OF VLSI DESIGN 7


the right mouse button expands or shortens the view to the right depending on where you click. You can
grab the slider with the middle button and move it around.

Changing the order of the nodes


If you don’t like the order that the nodes are displayed, you can click on a nodename with the left mouse
button, and drag it to a new place. Play around with this to see how it works.

Changing the number system basis for a vector


If you have the analyzer show you a vector (like ins in the earlier example), you can change its number
system base. To do so, highlight the vector by clicking on it with the left mouse button. Then, use the
“base” menu to change the display. Play around with this to see how it works.

Finding the time of an event


You can click inside the analyzer window where the waveforms are to get a vertical line. The time where
this vertical line is is displayed above. This is useful if you want to find out when a rising edge occurs.
The resolution is best when you are zoomed in.

Other IRSIM features


Combining the analyzer and the other IRSIM commands (see help) can make IRSIM a powerful digital
simulator.

Creating clocks nodes


IRSIM can create a clock node (or vector) that can be used to generate system clocks or input test
sequences. The “clock” command instructs IRSIM to cycle through the given node through the specified
states. Using the demo.irs file again, try the following commands:
*** IRSIM version 9.5 *** @ Wed Feb 7 08:57:06 2001
Read demo.irs lambda:0.30u format:MIT
13 nodes; transistors: n-channel=8 p-channel=8
parallel txtors:none
irsim> stepsize 1
irsim> vector ins a b c
irsim> w a b c ins f
irsim> l a b
irsim> clock c 0 1
irsim> ana a b c ins f
irsim> l a b
irsim> c
ins=001 f=0 c=1 b=0 a=0
time = 2.00ns

This sequence of commands creates a “clock” on the input c. The “c” command instructs IRSIM to step
the clock variable c throught the two state, 0 and 1. The remaining circuit outputs can be simulated with
irsim> h b
irsim> c
ins=011 f=0 c=1 b=1 a=0
time = 4.00ns
irsim> l b
irsim> h a
irsim> c

ECE 4263/6263 - PRINCIPLES OF VLSI DESIGN 8


ins=101 f=1 c=1 b=0 a=1
time = 6.00ns
irsim> h b
irsim> c
ins=111 f=0 c=1 b=1 a=1
time = 8.00ns
irsim>

Creating clock vectors


IRSIM can create a clock vector that can be used to generate system clock, multiphase clocks, or complex
input test sequences. The “clock” command is called with a defined vector as its argument. Using the
demo.irs file again, try the following commands:
*** IRSIM version 9.5 *** @ Wed Feb 7 08:59:00 2001
Read demo.irs lambda:0.30u format:MIT
13 nodes; transistors: n-channel=8 p-channel=8
parallel txtors:none
irsim> stepsize 1
irsim> vector ins a b c
irsim> w a b c ins f
irsim> clock ins 000 001 010 011 100 101 110 111
irsim> ana a b c ins f
irsim> c 2
ins=111 f=0 c=1 b=1 a=1
time = 16.00ns
irsim>

The “c 2” command tells IRSIM to cycle through the clock vectors states twice instead of just once. Now
redefine the clock vector to cycle through a gray code three times instead of counting in normal binary.
irsim> clock ins 000 001 011 010 110 111 101 100
irsim> c 3
ins=100 f=1 c=0 b=0 a=1
time = 40.00ns
irsim>

Creating IRSIM logs


IRSIM lets you keep a log of your commands and the outputs. To start recording, type
irsim> logfile mylogfile

Anything that you see in irsim from now on will be into the file called “mylogfile”. When you're done
recording, type
irsim> logfile

Using IRSIM command files


IRSIM can read IRSIM command from another file. Any IRSIM interactive command is valid. Use your
favorite text editor to create your command file. At the unix prompt, create a file called “example.cmd”.
Inside this file, place the following lines:
stepsize 5
vector ins a b c
vector bar abar bbar cbar
ana -h a b c ins abar bbar cbar bar n1 n2 n3 n4 f

ECE 4263/6263 - PRINCIPLES OF VLSI DESIGN 9


clock ins 000 111 001 110 010 101 011 100
c 8
clock ins 111 000 111 001 111 010 111 011 100 111 101 111 110
c 16
| end of example; do not type this comment in

This example runs through all many different possible combinations of inputs. The waveforms will be
displayed in an analyzer window. You can run a .cmd file from the command line or within IRSIM. To
run the command file directly upon starting IRSIM, type
% irsim c5n.prm demo.irs -example.cmd

Or from the IRSIM prompt, type (make sure you place a white space between the ampersand and the
filename)
irsim> @ example.cmd

and watch IRSIM fly!

Node name expansion


IRSIM has shortcut notation to represent and expand related node names. For example, consider the
circuit possessing nodes with names
pin1, pin2, pin3, pin4, pin5, pin6, pin7, pin8, pin9, pin10, pin11, pin12
pin1b, pin2b, pin3b, pin4b, pin5b, pin6, pin7b, pin8b, pin9b, pin10b, pin11b, pin12b

If all nodes are to be viewed with the analyzer window, the IRSIM command is
analyzer pin1, pin2, pin3, pin4, pin5, pin6, pin7, pin8, pin9, pin10, pin11, pin12, pin1b,
pin2b, pin3b, pin4b, pin5b, pin6, pin7b, pin8b, pin9b, pin10b, pin11b, pin12b

IRSIM can create the same expression using its node name expansion operator {start:stop}, where
start is the first number of the expansion sequence, and stop is the last number of the expansion
sequence. For example, the verbose IRSIM command above is equivalent to the shortened IRSIM
command
analyzer pin{1:12}, pin{1:12}b

ECE 4263/6263 - PRINCIPLES OF VLSI DESIGN 10

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