Compal Confidential: Schematics Document PAW20

A B C D E
ZZZ1 ZZZ2 ZZZ3 ZZZ4 ZZZ5
PCB LA-7012P LS-7012P LS-7013P LS-7014P

15"DAZ@ 15"DA@ 15"DA@ 15"DA@ 15"DA@
1 1
Compal Confidential
Schematics Document
2 2
PAW20
Montevina
3
with Intel Cantiga + ICH9 core logic 3
REV:1.0A
2010-12-24
4 4
Security Classification Compal Secret Data Compal Electronics,Ltd.

Issued Date 2010/09/10 Deciphered Date 2010/08/19 Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA7012P
Date: Friday, December 24, 2010 Sheet 1 of 41
A B C D E
A B C D E
Compal confidential
File Name : For 14" For 15"
Clock Generator LS-7011P 4PIN PWR/B LS-7012P 8PIN PWR/B
SLG8SP556VTR Mobile Penryn LS7013P Audio/B LS7013P Audio/B
LS7014P Touch/B LS7014P Touch/B
page16
uPGA-478 CPU
1 1
page4,5,6
H_A#(3..35) FSB
H_D#(0..63) 667/800MHz
CRT Connector
page21
Intel Cantiga GMCH DDR3-SO-DIMM X2
GM45 BANK 0, 1, 2, 3 page 14,15
LVDS Dual Channel
Connector page22 uFCBGA 1329 DDR3-667/800(1.5V) up to 4G
page 7,8,9,10,11,12,13
DMI 点4 C-Link 2Channel Speaker

page26
2 2
AZALIA Audio Codec Analog MIC_Int

page26
CONEXTAN
CX20671 page26
Wire Less Mini
card Slot 1 6*PCI-E BUS Intel ICH9-M 14*USB2.0 CMOS Camera
page23
page22
SPI ROM 6*SATA serial BlueTooth CONN

page 17,18,19,20 page30
BIOS
USB CONN X1(Right)
page29
LPC BUS
3
USB PORT X1(Left) 3
page29
AR8151/8152 EC USB PORT X1(Left)

ENE KB926 E0
page29
10/100/Giga LAN page27 Audio Jack SB CONN
page24
HP X 1+
MIC_Ext X1 page30
Card Reader RTS5139

RJ45 CONN Int.KBD
page25 page32
SPI ROM
BIOS page28 SATA HDD CONN
page28
4 Touch Pad SATA ODD CONN 4

page32
page32
Security Classification Compal Secret Data Compal Electronics, Inc.

MB Block Diagram
Custom 1.0
LA7012P
A B C D E
A B C D E
DDR3 Voltage Rails

SMBUS Control Table
+5VS
SOURCE BATT KB926 SODIMM CLK CHIP WLAN
WWAN
ICH9 Therml
power
plane
+3VS
+1.5VS
EC_SMB_CK1
EC_SMB_DA1 KB926
+3VALW
V
+3VALW
X X X X X X
1
+5VALW +1.5V
+CPU_CORE
+VGA_CORE
EC_SMB_CK2
EC_SMB_DA2 KB926
+3VALW
X X X X X X V
+3VS 1
+B
+3VALW
+1.8VS ICH_SMBCLK
ICH_SMBDATA ICH
+3VALW
X X V
+3VS
V
+3VS V
+3VALW X X
+0.75VS
+1.05VS
State
S0
O O O O
S3
I2C / SMBUS ADDRESSING
O O O X
2
S5 S4/AC
O O
DEVICE HEX ADDRESS 2
X X
DDR SO-DIMM A0 10100000
S5 S4/ Battery only
O 0DDR SO-DIMM A4 10100100
X X X 1CLOCK GENERATOR (EXT.) D2 11010010
S5 S4/AC & Battery
don't exist X X X X
@ FUNCTION
Structure Description NON-USE
45@ 45 BOM
BT@ Blue Tooth function
CMOS@ CMOS CAMERA function
PCIE PORT LIST USB PORT LIST
3 PORT DEVICE PORT DEVICE 3
1 LAN 0 RIGHT SIDE

2 1 LEFT SIDE
3 WLAN 2 CMOS
4 3
5 4 CARD READER
6 5 WIRELESS
7 6 BT
8 7 USB PORT(ESATA)
8
9
10
11
12
13
4 4

MB Notes List
B 1.0
LA7012P
A B C D E
A B C D E
PVT ESD solution.

ME@ Please close to R715
JCPU1A
H_A#3 J4 H1 H_ADS#
<7> H_A#[3..16] A[3]# ADS# H_ADS# <7> +1.05VS +1.05VS
ADDR GROUP_0
H_A#4 L5 E2 H_BNR#
H_A#5 A[4]# BNR# H_BPRI# H_BNR# <7>
L4 A[5]# BPRI# G5 H_BPRI# <7>
H_A#6 K5 H_IERR# R714 1 2 56_0402_5%
H_A#7 A[6]# H_DEFER#
M3 A[7]# DEFER# H5 H_DEFER# <7> 1
H_A#8 N2 F21 H_DRDY# H_PROCHOT# R715 1 2 68_0402_5%
H_A#9 A[8]# DRDY# H_DBSY# H_DRDY# <7>
J1 E1 C864
H_A#10 A[9]# DBSY# H_DBSY# <7>
N3 0.1U_0402_16V4Z
H_A#11 A[10]# H_BR0# 2
P5 F1 H_BR0# <7>
H_A#12 A[11]# BR0#
P2
A[12]#
CONTROL
1 H_A#13 H_IERR# 1
L2 D20
H_A#14 A[13]# IERR# H_INIT#
P4 B3 H_INIT# <18>
H_A#15 A[14]# INIT#
P1
H_A#16 A[15]# H_LOCK#
R1 H4 H_LOCK# <7>
H_ADSTB#0 A[16]# LOCK#
<7> H_ADSTB#0 M1
ADSTB[0]# H_RESET#
C1 H_RESET# <7>
H_REQ#0 RESET# H_RS#0
<7> H_REQ#0 K3 F3 H_RS#0 <7>
H_REQ#1 REQ[0]# RS[0]# H_RS#1
<7> H_REQ#1 H2 F4 H_RS#1 <7>
H_REQ#2 REQ[1]# RS[1]# H_RS#2
<7> H_REQ#2 K2 G3 H_RS#2 <7>
H_REQ#3 REQ[2]# RS[2]# H_TRDY#
<7> H_REQ#3 J3 G2 H_TRDY# <7>
H_REQ#4 REQ[3]# TRDY#
<7> H_REQ#4 L1
REQ[4]# H_HIT#
HIT# G6 H_HIT# <7>
H_A#17 Y2 E4 H_HITM#
H_A#18 A[17]# HITM# H_HITM# <7>
<7> H_A#[17..35] U5 A[18]#
H_A#19 R3 AD4
A[19]# BPM[0]#
ADDR GROUP_1
H_A#20 W6 AD3
H_A#21 A[20]# BPM[1]#
U4 A[21]# BPM[2]# AD1
H_A#22 Y5 AC4
A[22]# BPM[3]#
XDP/ITP SIGNALS
H_A#23 U1 AC2
H_A#24 A[23]# PRDY#
R4 A[24]# PREQ# AC1
H_A#25 T5 AC5 XDP_TCK
H_A#26 A[25]# TCK XDP_TDI
T3 A[26]# TDI AA6
H_A#27 W2 AB3 XDP_TDO
H_A#28 A[27]# TDO XDP_TMS
W5 A[28]# TMS AB5
H_A#29 Y4 AB6 XDP_TRST#
H_A#30 A[29]# TRST# XDP_DBRESET# +3VS +3VS
U2 A[30]# DBR# C20 XDP_DBRESET# <19>
H_A#31 V4
H_A#32 A[31]#
W3 A[32]#
1
H_A#33 AA4 THERMAL 1
H_A#34 A[33]# H_PROCHOT#
AB2 A[34]#
H_A#35 AA3 D21 C831 U1 R713
H_ADSTB#1 A[35]# PROCHOT# H_THERMDA 0.1U_0402_16V4Z 10K_0402_5%
<7> H_ADSTB#1 V1 ADSTB[1]# THERMDA A24
2
B25 H_THERMDC 2 2
2
H_A20M# THERMDC EC_SMB_CK2
<18> H_A20M# A6 A20M# ICH 1 VDD SMCLK 8 EC_SMB_CK2 <27>
H_FERR# A5 C7 H_THERMTRIP#
<18> H_FERR# H_IGNNE# FERR# THERMTRIP# H_THERMTRIP# <8,18> H_THERMDA EC_SMB_DA2
<18> H_IGNNE# C4 IGNNE# 2 DP SMDATA 7 EC_SMB_DA2 <27>
H_STPCLK# D5 1 2 H_THERMDC 3 6
<18> H_STPCLK# H_INTR STPCLK# DN ALERT#
C6 H CLK C832 2200P_0402_50V7K
<18> H_INTR LINT0
H_NMI B4 A22 CLK_CPU_BCLK THERM# 4 5
<18> H_NMI LINT1 BCLK[0] CLK_CPU_BCLK <16> THERM# GND
H_SMI# A3 A21 CLK_CPU_BCLK#
<18> H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# <16>
M4 +3VS 1 2
RSVD[01] R716 10K_0402_5% EMC1402-1-ACZL-TR_MSOP8
N5
RSVD[02]
T2
RSVD[03] H_THERMDA, H_THERMDC routing together,
V3
RSVD pins on the CPU B2
RSVD[04] Trace width / Spacing = 10 / 10 mil Address:100_1100
RESERVED
RSVD[05]
should be left as NO D2
D22
RSVD[06]
RSVD[07]
CONNECT D3
F6
RSVD[08]
RSVD[09]
Penryn
10/01 Add for reduce noise 09/16 Add C834 For ESD
H_RESET#
XDP_DBRESET#
3 XDP Reserve for debug , Please close to CPU side C651

@
1
1
3
100P_0402_50V8J C834
+3VS 2 0.1U_0402_16V4Z
2
XDP_DBRESET# R7181 2 @ 1K_0402_5%
+1.05VS
XDP_TDI
Place closely pin C1 Place closely pin C20
R8 1 2 54.9_0402_1%
XDP_TMS R9 1 2 54.9_0402_1%
XDP_TDO R10 1 2 @ 54.9_0402_1%
XDP_TRST# R11 1 2 54.9_0402_1%
XDP_TCK R12 1 2 54.9_0402_1%
4 4

Penryn(1/3)-AGTL+THM,FAN
Custom 1.0
LA7012P
A B C D E
5 4 3 2 1
ME@
JCPU1D
A4 VSS[001] VSS[082] P6
ME@ A8 P21
JCPU1B VSS[002] VSS[083]
<7> H_D#[0..15] H_D#[32..47] <7> A11 VSS[003] VSS[084] P24
H_D#0 E22 Y22 H_D#32 A14 R2
H_D#1 D[0]# D[32]# H_D#33 VSS[004] VSS[085]
F24 D[1]# D[33]# AB24 A16 VSS[005] VSS[086] R5
H_D#2 E26 V24 H_D#34 A19 R22
D[2]# D[34]# VSS[006] VSS[087]
DATA GRP 0
H_D#3 G22 V26 H_D#35 A23 R25
DATA GRP 2
H_D#4 D[3]# D[35]# H_D#36 VSS[007] VSS[088]
F23 D[4]# D[36]# V23 AF2 VSS[008] VSS[089] T1
H_D#5 G25 T22 H_D#37 B6 T4
H_D#6 D[5]# D[37]# H_D#38 VSS[009] VSS[090]
E25 D[6]# D[38]# U25 B8 VSS[010] VSS[091] T23
H_D#7 E23 U23 H_D#39 B11 T26
H_D#8 D[7]# D[39]# H_D#40 VSS[011] VSS[092]
K24 D[8]# D[40]# Y25 B13 VSS[012] VSS[093] U3
H_D#9 G24 W22 H_D#41 B16 U6
D H_D#10 D[9]# D[41]# H_D#42 VSS[013] VSS[094] D
J24 D[10]# D[42]# Y23 B19 VSS[014] VSS[095] U21
H_D#11 J23 W24 H_D#43 B21 U24
H_D#12 D[11]# D[43]# H_D#44 VSS[015] VSS[096]
H22 D[12]# D[44]# W25 B24 VSS[016] VSS[097] V2
H_D#13 F26 AA23 H_D#45 C5 V5
H_D#14 D[13]# D[45]# H_D#46 VSS[017] VSS[098]
K22 D[14]# D[46]# AA24 C8 VSS[018] VSS[099] V22
H_D#15 H23 AB25 H_D#47 C11 V25
H_DSTBN#0 D[15]# D[47]# H_DSTBN#2 VSS[019] VSS[100]
<7> H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 <7> C14 VSS[020] VSS[101] W1
H_DSTBP#0 H26 AA26 H_DSTBP#2 C16 W4
<7> H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 <7> VSS[021] VSS[102]
H_DINV#0 H25 U22 H_DINV#2 C19 W23
<7> H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 <7> VSS[022] VSS[103]
C2 VSS[023] VSS[104] W26
<7> H_D#[16..31] H_D#[48..63] <7> C22 VSS[024] VSS[105] Y3
H_D#16 N22 AE24 H_D#48 C25 Y6
H_D#17 D[16]# D[48]# H_D#49 VSS[025] VSS[106]
K25 D[17]# D[49]# AD24 D1 VSS[026] VSS[107] Y21
H_D#18 P26 AA21 H_D#50 D4 Y24
H_D#19 D[18]# D[50]# H_D#51 VSS[027] VSS[108]
R23 D[19]# D[51]# AB22 D8 VSS[028] VSS[109] AA2
H_D#20 L23 AB21 H_D#52 D11 AA5
D[20]# D[52]# VSS[029] VSS[110]
DATA GRP 1
H_D#21 M24 AC26 H_D#53 D13 AA8
DATA GRP 3
H_D#22 D[21]# D[53]# H_D#54 VSS[030] VSS[111]
L22 D[22]# D[54]# AD20 D16 VSS[031] VSS[112] AA11
H_D#23 M23 AE22 H_D#55 D19 AA14
H_D#24 D[23]# D[55]# H_D#56 VSS[032] VSS[113]
P25 D[24]# D[56]# AF23 D23 VSS[033] VSS[114] AA16
H_D#25 P23 AC25 H_D#57 D26 AA19
H_D#26 D[25]# D[57]# H_D#58 VSS[034] VSS[115]
P22 D[26]# D[58]# AE21 E3 VSS[035] VSS[116] AA22
H_D#27 T24 AD21 H_D#59 E6 AA25
H_D#28 D[27]# D[59]# H_D#60 VSS[036] VSS[117]
R24 D[28]# D[60]# AC22 E8 VSS[037] VSS[118] AB1
H_D#29 L25 AD23 H_D#61 E11 AB4
H_D#30 D[29]# D[61]# H_D#62 VSS[038] VSS[119]
T25 D[30]# D[62]# AF22 E14 VSS[039] VSS[120] AB8
H_D#31 N25 AC23 H_D#63 E16 AB11
H_DSTBN#1 D[31]# D[63]# H_DSTBN#3 VSS[040] VSS[121]
<7> H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 <7> E19 VSS[041] VSS[122] AB13
H_DSTBP#1 M26 AF24 H_DSTBP#3 E21 AB16
<7> H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 <7> VSS[042] VSS[123]
H_DINV#1 N24 AC20 H_DINV#3 E24 AB19
<7> H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 <7> VSS[043] VSS[124]
F5 VSS[044] VSS[125] AB23
+CPU_GTLREF AD26 R26 COMP0 R719 1 2 27.4_0402_1% F8 AB26
C R14 GTLREF COMP[0] VSS[045] VSS[126] C
1 2 @ 1K_0402_5% TEST1 C23 TEST1 MISC COMP[1] U26 COMP1 R15 1 2 54.9_0402_1% F11 VSS[046] VSS[127] AC3
R16 1 2 @ 1K_0402_5% TEST2 D25 AA1 COMP2 R720 1 2 27.4_0402_1% F13 AC6
T1 TEST3 TEST2 COMP[2] COMP3 R18 54.9_0402_1% VSS[047] VSS[128]
C24 TEST3 COMP[3] Y1 1 2 F16 VSS[048] VSS[129] AC8
T2 TEST4 AF26 F19 AC11
T3 TEST5 TEST4 H_DPRSTP# VSS[049] VSS[130]
AF1 TEST5 DPRSTP# E5 H_DPRSTP# <8,18,40> F2 VSS[050] VSS[131] AC14
T4 TEST6 A26 B5 H_DPSLP# F22 AC16
TEST6 DPSLP# H_DPSLP# <18> VSS[051] VSS[132]
T157 TEST7 C3 D24 H_DPWR# F25 AC19
TEST7 DPWR# H_DPWR# <7> VSS[052] VSS[133]
CPU_BSEL0 B22 D6 H_PWRGOOD G4 AC21
<16> CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGOOD <18> VSS[053] VSS[134]
CPU_BSEL1 B23 D7 H_CPUSLP# G1 AC24
<16> CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# <7> VSS[054] VSS[135]
CPU_BSEL2 C21 AE6 H_PSI# G23 AD2
<16> CPU_BSEL2 BSEL[2] PSI# H_PSI# <40> VSS[055] VSS[136]
G26 VSS[056] VSS[137] AD5
Penryn H3 AD8
VSS[057] VSS[138]
H6 VSS[058] VSS[139] AD11
H21 VSS[059] VSS[140] AD13
H24 VSS[060] VSS[141] AD16
TRACE CLOSELY CPU < 0.5' J2 VSS[061] VSS[142] AD19
J5 VSS[062] VSS[143] AD22
COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) J22 VSS[063] VSS[144] AD25
J25 AE1
COMP1, COMP3 layout : Width 5mils and Space 25mils (55Ohms) K1
VSS[064] VSS[145]
AE4
VSS[065] VSS[146]
FSB BCLK BSEL2 BSEL1 BSEL0 layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs K4 VSS[066] VSS[147] AE8
K23 VSS[067] VSS[148] AE11
K26 VSS[068] VSS[149] AE14
533 133 0 0 1 L3 VSS[069] VSS[150] AE16
L6 VSS[070] VSS[151] AE19
L21 VSS[071] VSS[152] AE23
667 166 0 1 1 L24 VSS[072] VSS[153] AE26
M2 VSS[073] VSS[154] A2
M5 VSS[074] VSS[155] AF6
800 200 0 1 0 M22 VSS[075] VSS[156] AF8
M25 VSS[076] VSS[157] AF11
N1 VSS[077] VSS[158] AF13
B B
1067 266 0 0 0 N4 VSS[078] VSS[159] AF16
N23 VSS[079] VSS[160] AF19
N26 VSS[080] VSS[161] AF21
P3 VSS[081] VSS[162] A25
VSS[163] AF25
Penryn
.
Layout note: Z0=55 ohm
0.5" max for GTLREF.
+1.05VS
09/29 Add for power noise

1
PVT for ESD solution

R19
1K_0402_1%
2
+CPU_GTLREF H_DPRSTP# H_DPRSTP# H_DPSLP# H_PSI#

H_PWRGOOD
1
1 1 1 1
1
R20 C652 C630 C636 C642
2K_0402_1% 470P_0402_50V7K 470P_0402_50V7K 100P_0402_50V8J 470P_0402_50V7K C637
2 2 2 2
330P_0402_50V7K
2
Close to CPU pin E5 Close to CPU pin B5

A Close to CPU pin AD26 Close to Power IC within 500mils. within 500mils. Close to Power IC Close to CPU pin D6 A
within 500mils. (PU9.12) within within 500mils.

500mils.

Penryn(2/3)-AGTL+GND
Custom 1.0
LA7012P
5 4 3 2 1
5 4 3 2 1
+1.05VS Place these inside socket cavity on L8

+CPU_CORE
+CPU_CORE +CPU_CORE (North side Secondary)
ME@
JCPU1C 330U_D2E_2.5VM_R9M 330U_D2E_2.5VM_R9M
A7 VCC[001] VCC[068] AB20 1 1 1 1 1 1 1 1 1 1
A9 AB7 C8 C9 C10 C11 C12 C835
VCC[002] VCC[069] C81 + + C86 + C82 + C94
A10 VCC[003] VCC[070] AC7
A12 AC9 330U_D2E_2.5VM_R9M 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
VCC[004] VCC[071] @ 2 2 2 2 2 2
A13 AC12
VCC[005] VCC[072] 2 2 2 2
A15 AC13
D VCC[006] VCC[073] 330U_D2E_2.5VM_R9M D
A17 AC15
VCC[007] VCC[074]
A18 AC17
VCC[008] VCC[075]
A20 AC18
VCC[009] VCC[076]
B7 AD7
VCC[010] VCC[077]
B9 AD9
VCC[011] VCC[078]
B10
VCC[012] VCC[079]
AD10 PVT Change C82 and C94 from SF000002O00 to SGA19331D10
B12 AD12
VCC[013] VCC[080]
B14 AD14
VCC[014] VCC[081]
B15 AD15
VCC[015] VCC[082]
B17 AD17
VCC[016] VCC[083] +CPU_CORE
B18 AD18
VCC[017] VCC[084]
B20 VCC[018] VCC[085] AE9
C9 VCC[019] VCC[086] AE10
C10 VCC[020] VCC[087] AE12 1 1 1 1 1 1 1 1
C12 AE13 C18 C19 C20 C21 C22 C23 C24 C836
VCC[021] VCC[088] Place these capacitors on L1
C13 VCC[022] VCC[089] AE15
C15 AE17 (North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VCC[023] VCC[090] 2 2 2 2 2 2 2 2
C17 VCC[024] VCC[091] AE18
C18 VCC[025] VCC[092] AE20
D9 VCC[026] VCC[093] AF9
D10 VCC[027] VCC[094] AF10
D12 AF12 +CPU_CORE
VCC[028] VCC[095]
D14 VCC[029] VCC[096] AF14
D15 VCC[030] VCC[097] AF15
D17 VCC[031] VCC[098] AF17 1 1 1 1 1 1 1 1
D18 AF18 C26 C27 C28 C29 C30 C31 C32 C837
VCC[032] VCC[099] +1.05VS Place these capacitors on L1
E7 VCC[033] VCC[100] AF20
E9 (North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VCC[034] 2 2 2 2 2 2 2 2
E10 VCC[035] VCCP[01] G21
E12 VCC[036] VCCP[02] V6 1
E13 VCC[037] VCCP[03] J6
E15 K6 + C60
C VCC[038] VCCP[04] 330U_D2E_2.5VM_R9M +CPU_CORE C
E17 VCC[039] VCCP[05] M6
E18 VCC[040] VCCP[06] J21
2
E20 VCC[041] VCCP[07] K21
F7 VCC[042] VCCP[08] M21 1 1 1 1 1 1 1 1
F9 N21 C35 C36 C37 C38 C39 C40 C41 C42
VCC[043] VCCP[09] Place these capacitors on L1
F10 VCC[044] VCCP[10] N6
F12 R21 (South side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VCC[045] VCCP[11] 2 2 2 2 2 2 2 2
F14 R6
VCC[046] VCCP[12]
F15 T21
VCC[047] VCCP[13]
F17
VCC[048] VCCP[14]
T6 NEAR PIN B26
F18 V21
VCC[049] VCCP[15] +CPU_CORE
F20 W21
VCC[050] VCCP[16]
AA7
VCC[051] 20mils
AA9 B26
VCC[052] VCCA[01] +1.5VS
0.01U_0402_16V7K
AA10 C26 1 1 1 1 1 1 1 1
VCC[053] VCCA[02]
10U_0805_10V4Z
AA12 C43 C44 C45 C46 C47 C48 C49 C50

VCC[054] Place these capacitors on L1
AA13 AD6 CPU_VID0 <40>
VCC[055] VID[0] (South side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
AA15 AF5 CPU_VID1 <40> 1 1
VCC[056] VID[1] 2 2 2 2 2 2 2 2
AA17 AE5 CPU_VID2 <40>
VCC[057] VID[2]
C51
C52
AA18 AF4 CPU_VID3 <40>

VCC[058] VID[3]
AA20 AE3 CPU_VID4 <40>
VCC[059] VID[4] 2 2
AB9 AF3 CPU_VID5 <40>
VCC[060] VID[5]
AC10 AE2
AB10
VCC[061] VID[6] CPU_VID6 <40> Mid Frequence Decoupling
VCC[062]
AB12
VCC[063] VCCSENSE
AB14 AF7 VCCSENSE <40>
VCC[064] VCCSENSE
AB15
VCC[065]
AB17
VCC[066] VSSSENSE
AB18 AE7 VSSSENSE <40>
VCC[067] VSSSENSE
Penryn 09/29 Add for power noise
.
B B
Close to Power IC CPU_VID0
The trace width/space/other is 18/7/25.
CPU_VID1
CPU_VID2
Layout Note:
CPU_VID3
Route VCCSENSE and VSSSENSE traces at
27.4 Ohms with 50 mil spacing. CPU_VID4
Place PU and PD within 1 inch of CPU.
CPU_VID5
Length matched to within 25 mils.
CPU_VID6
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
1 1 1 1 1 1 1
C643 C644 C646 C647 C648 C649 C650
2 2 2 2 2 2 2
+CPU_CORE
R21
100_0402_1%
1 2 VCCSENSE
R22
100_0402_1%
1 2 VSSSENSE
A A
Close to CPU pin

within 500mils. Security Classification Compal Secret Data Compal Electronics, Inc.
Penryn(3/3)-PWR+Bypass
Custom 1.0
LA7012P
5 4 3 2 1
5 4 3 2 1
H_A#[3..35] <4>
U3A
<5> H_D#[0..63] A14 H_A#3
H_D#0 H_A#_3 H_A#4
F2 H_D#_0 H_A#_4 C15
H_D#1 G8 F16 H_A#5
H_D#2 H_D#_1 H_A#_5 H_A#6
F8 H_D#_2 H_A#_6 H13
H_D#3 E6 C18 H_A#7
H_D#4 H_D#_3 H_A#_7 H_A#8
G2 H_D#_4 H_A#_8 M16
H_D#5 H6 J13 H_A#9
H_D#6 H_D#_5 H_A#_9 H_A#10
H2 H_D#_6 H_A#_10 P16
H_D#7 F6 R16 H_A#11
D H_D#8 H_D#_7 H_A#_11 H_A#12 D
D4 H_D#_8 H_A#_12 N17
H_D#9 H3 M13 H_A#13
H_D#10 H_D#_9 H_A#_13 H_A#14
M9 H_D#_10 H_A#_14 E17
H_D#11 M11 P17 H_A#15
H_D#12 H_D#_11 H_A#_15 H_A#16
J1 H_D#_12 H_A#_16 F17
H_D#13 J2 G20 H_A#17
H_D#14 H_D#_13 H_A#_17 H_A#18
N12 H_D#_14 H_A#_18 B19
H_D#15 J6 J16 H_A#19
H_D#16 H_D#_15 H_A#_19 H_A#20
P2 H_D#_16 H_A#_20 E20
H_D#17 L2 H16 H_A#21
H_D#18 H_D#_17 H_A#_21 H_A#22
R2 H_D#_18 H_A#_22 J20
H_D#19 N9 L17 H_A#23
H_D#20 H_D#_19 H_A#_23 H_A#24
L6 H_D#_20 H_A#_24 A17
H_D#21 M5 B17 H_A#25
H_D#22 H_D#_21 H_A#_25 H_A#26
J3 H_D#_22 H_A#_26 L16
H_D#23 N2 C21 H_A#27
H_D#24 H_D#_23 H_A#_27 H_A#28
R1 H_D#_24 H_A#_28 J17
H_D#25 N5 H20 H_A#29
H_D#26 H_D#_25 H_A#_29 H_A#30
N6 H_D#_26 H_A#_30 B18
H_D#27 P13 K17 H_A#31
H_D#28 H_D#_27 H_A#_31 H_A#32
N8 H_D#_28 H_A#_32 B20
H_D#29 L7 F21 H_A#33
H_D#30 H_D#_29 H_A#_33 H_A#34
N10 H_D#_30 H_A#_34 K21
H_D#31 M3 L20 H_A#35
H_D#32 H_D#_31 H_A#_35
Y3 H_D#_32
H_D#33 AD14 H12 H_ADS#
H_D#_33 H_ADS# H_ADS# <4>
H_D#34 Y6 B16 H_ADSTB#0
H_D#_34 H_ADSTB#_0 H_ADSTB#0 <4>
H_D#35 Y10 G17 H_ADSTB#1
H_D#_35 H_ADSTB#_1 H_ADSTB#1 <4>
H_D#36 Y12 A9 H_BNR#
H_D#_36 H_BNR# H_BNR# <4>
HOST
H_D#37 Y14 F11 H_BPRI#

H_D#_37 H_BPRI# H_BPRI# <4>
H_D#38 Y7 G12 H_BR0#
H_D#_38 H_BREQ# H_BR0# <4>
H_D#39 W2 E9 H_DEFER#
C H_D#_39 H_DEFER# H_DEFER# <4> C
H_D#40 AA8 B10 H_DBSY#
H_D#_40 H_DBSY# H_DBSY# <4>
H_D#41 Y9 AH7 CLK_MCH_BCLK
H_D#_41 HPLL_CLK CLK_MCH_BCLK <16>
H_D#42 AA13 AH6 CLK_MCH_BCLK#
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# <16>
H_D#43 AA9 J11 H_DPWR#
H_D#_43 H_DPWR# H_DPWR# <5>
H_D#44 AA11 F9 H_DRDY#
H_D#_44 H_DRDY# H_DRDY# <4>
H_D#45 AD11 H9 H_HIT#
H_D#_45 H_HIT# H_HIT# <4>
H_D#46 AD10 E12 H_HITM#
H_D#_46 H_HITM# H_HITM# <4>
H_D#47 AD13 H11 H_LOCK#
H_D#_47 H_LOCK# H_LOCK# <4>
H_D#48 AE12 C9 H_TRDY# H_TRDY# <4>
H_D#49 H_D#_48 H_TRDY#
AE9 H_D#_49
H_D#50 AA2
H_D#51 H_D#_50
AD8 H_D#_51
H_D#52 AA3
H_D#53 H_D#_52 H_DINV#0
H_D#54
AD3
AD7
H_D#_53 H_DINV#_0 J8
L3 H_DINV#1
H_DINV#0 <5> Layout Note:
H_D#_54 H_DINV#_1 H_DINV#1 <5>
H_D#55 H_DINV#2
H_D#56
AE14
AF3
H_D#_55 H_DINV#_2 Y13
Y1 H_DINV#3
H_DINV#2 <5> H_RCOMP / H_VREF / H_SWNG
H_D#_56 H_DINV#_3 H_DINV#3 <5>
H_D#57
H_D#58
AC1 H_D#_57 H_DSTBN#0
trace width and spacing is 10/20
AE3 H_D#_58 H_DSTBN#_0 L10 H_DSTBN#0 <5>
H_D#59 AC3 M7 H_DSTBN#1
H_D#_59 H_DSTBN#_1 H_DSTBN#1 <5>
H_D#60 AE11 AA5 H_DSTBN#2
H_D#_60 H_DSTBN#_2 H_DSTBN#2 <5> +1.05VS +1.05VS
H_D#61 AE8 AE6 H_DSTBN#3
H_D#_61 H_DSTBN#_3 H_DSTBN#3 <5>
H_D#62 AG2
H_D#63 H_D#_62 H_DSTBP#0
AD6 H_D#_63 H_DSTBP#_0 L9 H_DSTBP#0 <5>
1
M8 H_DSTBP#1
H_DSTBP#_1 H_DSTBP#1 <5>
AA6 H_DSTBP#2
H_DSTBP#_2 H_DSTBP#2 <5>
H_SWNG C5 AE5 H_DSTBP#3 R23 R24
H_SWING H_DSTBP#_3 H_DSTBP#3 <5>
H_RCOMP E3 1K_0402_1% 221_0603_1%
H_RCOMP H_REQ#0
B15 H_REQ#0 <4>
2
H_REQ#_0 H_REQ#1 H_VREF H_RCOMP H_SWNG
H_REQ#_1 K13 H_REQ#1 <4>
F13 H_REQ#2
H_REQ#_2 H_REQ#2 <4>
1
B13 H_REQ#3 1 1
B H_REQ#_3 H_REQ#3 <4> B
<4> H_RESET# H_RESET# C12 B14 H_REQ#4
H_CPURST# H_REQ#_4 H_REQ#4 <4>
<5> H_CPUSLP# H_CPUSLP# E11 R25 C53 R26 R27 C54
H_CPUSLP# H_RS#0 2K_0402_1% 0.1U_0402_16V4Z 24.9_0402_1% 100_0402_1% 0.1U_0402_16V4Z
H_RS#_0 B6 H_RS#0 <4>
H_RS#1 2 2
F12 H_RS#1 <4>
2
H_VREF H_RS#_1 H_RS#2
A11 H_AVREF H_RS#_2 C8 H_RS#2 <4>
B11 H_DVREF
CANTIGA ES_FCBGA1329
GM45@ within 100 mils from NB Near B3 pin
U3
PVT ESD solution.

Please close to R23
GL40
GL40@ +1.05VS
1
C70
0.1U_0402_16V4Z
2
A A

Cantiga(1/7)-AGTL+
Custom 1.0
LA7012P
5 4 3 2 1
5 4 3 2 1
U3B
Strap Pin Table M36 RSVD1 SA_CK_0 AP24 M_CLK_DDR0

M_CLK_DDR1
M_CLK_DDR0 <14> Layout Note: +1.5V
N36 RSVD2 SA_CK_1 AT21 M_CLK_DDR1 <14>
011 = FSB667 R33 RSVD3 SB_CK_0 AV24 M_CLK_DDR2
M_CLK_DDR3
M_CLK_DDR2 <15> +DDR_MCH_REF trace
CFG[2:0] 010 = FSB800 T33 AU20 M_CLK_DDR3 <15>
COMPENSATION
RSVD4 SB_CK_1
1
000 = FSB1067 AH9 RSVD5 M_CLK_DDR#0
width and spacing is 20/20. R58
AH10 RSVD6 SA_CK#_0 AR24 M_CLK_DDR#0 <14>
0 = DMI x 2 AH12 RSVD7 SA_CK#_1 AR21 M_CLK_DDR#1
M_CLK_DDR#1 <14> CLOSE TO PIN.AV42 10K_0402_1%
CFG5 Internal pull-up 1 = DMI x 4 *(Default) AH13 AU24 M_CLK_DDR#2
RSVD8 SB_CK#_0 M_CLK_DDR#2 <15>
K12 AV20 M_CLK_DDR#3
M_CLK_DDR#3 <15>
2
RSVD9 SB_CK#_1 +DDR_MCH_REF
0 = iTPM Host Interface is enabled can support disble by SW. AL34 RSVD10
CFG6 Internal pull-up 1 = iTPM Host Interface is Disabled DDR_CKE0_DIMMA
*(Default) AK34 RSVD11 SA_CKE_0 BC28 DDR_CKE0_DIMMA <14>
1
AN35 AY28 DDR_CKE1_DIMMA 1
RSVD12 SA_CKE_1 DDR_CKE1_DIMMA <14>
0 = Intel Management Engine Crypto Transport Layer Security AM35 AY36 DDR_CKE2_DIMMB R64
D RSVD13 SB_CKE_0 DDR_CKE2_DIMMB <15> D
T24 BB36 DDR_CKE3_DIMMB C61 10K_0402_1%
RSVD14 SB_CKE_1 DDR_CKE3_DIMMB <15>
(TLS) cipher suite with no confidentiality For DDR3 : 1.5V power rail 0.1U_0402_16V4Z
Internal pull-up DDR_CS0_DIMMA# 2
CFG7 BA17 DDR_CS0_DIMMA# <14> For DDR2 : 1.8V power rail
2
SA_CS#_0 DDR_CS1_DIMMA#
1 = Intel Management Engine Crypto TLS cipher suite with SA_CS#_1 AY16
DDR_CS2_DIMMB#
DDR_CS1_DIMMA# <14> +1.5V
B31 RSVD15 SB_CS#_0 AV16 DDR_CS2_DIMMB# <15>
confidentiality *(Default) B2 AR13 DDR_CS3_DIMMB#
DDR_CS3_DIMMB# <15>
RSVD16 SB_CS#_1
DDR CLK/ CONTROL/

M1 RSVD17
1
RSVD
0 = Lane Reversal Enable BD17 M_ODT0 M_ODT0 <14>
SA_ODT_0 M_ODT1
CFG9 Internal pull-up 1 = Normal Operation *(Default) SA_ODT_1 AY17 M_ODT1 <14>
AY21 BF15 M_ODT2 M_ODT2 <15> R28
RSVD20 SB_ODT_O M_ODT3 80.6_0402_1%
0 = PCIe Loopback Enable SB_ODT_1 AY13 M_ODT3 <15> For Crestline: 20ohm
CFG10 Internal pull-up 1 = Disable*(Default) 20mil For Calero: 80.6ohm
2
BG22 SMRCOMP For Cantiga: 80.6ohm
SM_RCOMP SMRCOMP#
01 = All Z Mode Enabled BG23 RSVD22 SM_RCOMP# BH21 1 2
CFG[13:12] 00 = Reserved BF23 R29 80.6_0402_1%
RSVD23 SMRCOMP_VOH
10 = XOR Mode Enabled BH18 RSVD24 SM_RCOMP_VOH BF28
Internal pull-up 11 = Normal Operation *(Default) BF18 BH28 SMRCOMP_VOL R30 1 2 0_0402_5%
RSVD25 SM_RCOMP_VOL 1.5V_PGOOD <39>
R53 1 2 @ 12K_0402_5%
DDR3_SM_PWROK <27>
0 = Dynamic ODT Disabled AV42 +DDR_MCH_REF
SM_VREF SM_PWROK R721 1
CFG16 Internal pull-up 1 = Dynamic ODT Enabled *(Default) SM_PWROK AR36 2 @ 10K_0402_5%
BF17 SM_REXT R32 1 2 499_0402_1%
SM_REXT SM_DRAMRST#
0 = Normal Operation *(Default) SM_DRAMRST# BC36 SM_DRAMRST# <14,15>
CFG19 Internal pull-down 1 = DMI Lane Reversal Enable SM_DRAMRST# is only for DDR3.
CFG20 0 = Only PCIE or [SDVO/DP/HDMI] is operational. CLK_MCH_DREFCLK DDR2 left it No Connect
Internal pull-down
* (Default) DPLL_REF_CLK B38
A38 CLK_MCH_DREFCLK#
CLK_MCH_DREFCLK <16>
DPLL_REF_CLK# CLK_MCH_DREFCLK# <16>
(PCIE/SDVO select) 1 = PCIE/[SDVO/DP/HDMI] are operating simu. E41 MCH_SSCDREFCLK
DPLL_REF_SSCLK MCH_SSCDREFCLK <16> +1.5V
F41 MCH_SSCDREFCLK#
DPLL_REF_SSCLK# MCH_SSCDREFCLK# <16>
CLK
F43 CLK_MCH_3GPLL
PEG_CLK CLK_MCH_3GPLL <16>
1
+1.05VS E43 CLK_MCH_3GPLL#
PEG_CLK# CLK_MCH_3GPLL# <16>
C R34 C
1K_0402_1%
1
+3VS AE41 DMI_TXN0

DMI_TXN0 <19>
2
R33 DMI_RXN_0 DMI_TXN1 SMRCOMP_VOH
DMI_RXN_1 AE37 DMI_TXN1 <19>
1K_0402_5% AE47 DMI_TXN2 1 1
DMI_RXN_2 DMI_TXN2 <19>
1
@ AH39 DMI_TXN3
DMI_RXN_3 DMI_TXN3 <19>
1
C55 C56
2
R722 R723 AE40 DMI_TXP0 0.01U_0402_25V7K 2.2U_0603_6.3V4Z R724

DMI_RXP_0 DMI_TXP0 <19> 2 2
54.9_0402_1% 1K_0402_5% MCH_CLKSEL0 T25 AE38 DMI_TXP1 3.01K_0402_1%
<16> MCH_CLKSEL0 CFG_0 DMI_RXP_1 DMI_TXP1 <19>
2
B
@ @ MCH_CLKSEL1 R25 AE48 DMI_TXP2

<16> MCH_CLKSEL1 DMI_TXP2 <19>
2
MCH_CLKSEL2 CFG_1 DMI_RXP_2 DMI_TXP3
<16> MCH_CLKSEL2 P25 AH40 DMI_TXP3 <19>
2
CFG_2 DMI_RXP_3
E
MCH_TSATN# 3 1 TSATN# P20 SMRCOMP_VOL

TSATN# <27> CFG_3
C
Q42 P24 AE35 DMI_RXN0

CFG_4 DMI_TXN_0 DMI_RXN0 <19>
1
DMI
MMBT3904_SOT23-3 R725 1 2@ 2.21K_0402_1% MCH_CFG_5 C25 AE43 DMI_RXN1 1 1
@ R39 1 2@ 2.21K_0402_1% MCH_CFG_6 N24 AE46 DMI_RXN2
R40 1 2@ 2.21K_0402_1% MCH_CFG_7 M24 AH42 DMI_RXN3 C57 C58 R43
CFG
E21 0.01U_0402_25V7K 2.2U_0603_6.3V4Z 1K_0402_1%
R41 CFG_8 2 2
1 2@ 2.21K_0402_1% MCH_CFG_9 C23 AD35 DMI_RXP0
DMI_RXP0 <19>
2
+3VS R42 CFG_9 DMI_TXP_0
1 2@ 2.21K_0402_1% MCH_CFG_10 C24 CFG_10 DMI_TXP_1 AE44 DMI_RXP1
DMI_RXP1 <19>
N21 AF46 DMI_RXP2
CFG_11 DMI_TXP_2 DMI_RXP2 <19>
R44 1 2@ 2.21K_0402_1% MCH_CFG_12 P21 AH43 DMI_RXP3
CFG_12 DMI_TXP_3 DMI_RXP3 <19>
R45 1 2@ 2.21K_0402_1% MCH_CFG_13 T21 CFG_13
1
R20 CFG_14
M20 CFG_15
R47 R48 +3VS R46 1 2@ 2.21K_0402_1% MCH_CFG_16 L21
10K_0402_5% 10K_0402_5% CFG_16
H21 CFG_17 For independent Power Rail : connect to PWM CORE VID
P29 For Common Power Rail : left it No Connect
2
GRAPHICS VID
PM_EXTTS#0 R49 CFG_18
1 2@ 4.02K_0402_1% MCH_CFG_19 R28 CFG_19
PM_EXTTS#1 R50 1 2@ 4.02K_0402_1% MCH_CFG_20 T28 B33
CFG_20 GFX_VID_0 +1.05VS
GFX_VID_1 B32
GFX_VID_2 G33
R51 1 2 0_0402_5% PM_POK_R F33
<19,27> ICH_POK GFX_VID_3
1
B PM_BMBUSY# R29 E33 B
<19> PM_BMBUSY# PM_SYNC# GFX_VID_4
R727 1 2 @ 0_0402_5% H_DPRSTP# B7
<19,40> VGATE <5,18,40> H_DPRSTP# PM_DPRSTP#
PM_EXTTS#0 N33 R726
<14,15> PM_EXTTS#0 PM_EXT_TS#_0
PM
R728 1 2 100_0402_5% PLT_RST#_R PM_EXTTS#1 P32 1K_0402_1%

<17,23,24> PLT_RST# PM_EXT_TS#_1
PM_POK_R AT40 C34
2
PLT_RST#_R PWROK GFX_VR_EN
AT11 RSTIN#
<4,18> H_THERMTRIP# H_THERMTRIP# T20
DPRSLPVR THERMTRIP#
<19,40> DPRSLPVR R32 DPRSLPVR 1
Place closely pin U3.R32 Place closely pin PR132.2 For AMT function
C59 R729
BG48 AH37 CL_CLK0 CL_CLK0 <19> 0.1U_0402_16V4Z 499_0402_1%
DPRSLPVR DPRSLPVR NC_1 CL_CLK CL_DATA0 2
BF48 NC_2 CL_DATA AH36 CL_DATA0 <19>
ME
BD48 AN36 M_PWROK

NC_3 CL_PWROK M_PWROK <19>
BC48 AJ35 CL_RST#
1 1 BH47
NC_4
NC_5
CL_RST#
CL_VREF AH34 CL_VREF
CL_RST# <19>
Strap Pin Table
BG47 NC_6
C861 C862 BE47 SDVO_CTRLDATA 0 = SDVO interface disabled *(Default)
NC_7 T110
2
1000P_0402_50V7K
2
1000P_0402_50V7K BH46 NC_8 DDPC_CTRLCLK N28 (Internal pull-down) 1 = SDVO interface enabled
NC
BF46 M28 T109

NC_9 DDPC_CTRLDATA SDVO_SCLK
BG45 NC_10 SDVO_CTRLCLK G36 DDPC_CTRLDATA 0 = Digital display (iHDMI/DP) interface disabled *(Default)
BH44 NC_11 SDVO_CTRLDATA E36 (Internal pull-down) 1 = Digital display (iHDMI/DP) interface enabled
BH43 K36 MCH_CLKREQ#
NC_12 CLKREQ# MCH_CLKREQ# <16>
MISC
BH6 H36 MCH_ICH_SYNC#

NC_13 ICH_SYNC# MCH_ICH_SYNC# <19> +3VS
BH5 NC_14
BG4 NC_15
09/16 Add C838 For noise BH3 B12 MCH_TSATN# R57 1 2 56_0402_5% +1.05VS SDVO_SCLK 2 1 2.2K_0402_5%
NC_16 TSATN# R56 @
BF3 NC_17
BH2 NC_18
Place closely pin AT11 Place closely pin B7 Place closely pin AR36 BG2 NC_19
BE2 NC_20 HDA_BCLK B28
BG1 NC_21 HDA_RST# B30
H_DPRSTP# SM_PWROK BF1 B29
A PLT_RST#_R NC_22 HDA_SDI A
BD1 NC_23 HDA_SDO C29
BC1 A28
HDA
NC_24 HDA_SYNC
1 1 1 F1 NC_25
A47 NC_26
C838 C631 C638
0.1U_0402_16V4Z 470P_0402_50V7K 100P_0402_50V8J CANTIGA ES_FCBGA1329 Notice: Please check HDA power rail to select HDA controller.
2 2 2 GM45@
Cantiga(2/7)-DMI/DDR/STRP
Custom 1.0
LA7012P
5 4 3 2 1
5 4 3 2 1
D U3D U3E D
DDR_A_D0 AJ38 BD21 DDR_A_BS0 DDR_B_D0 AK47 BC16 DDR_B_BS0
<14> DDR_A_D[0..63] SA_DQ_0 SA_BS_0 DDR_A_BS[0..2] <14><15> DDR_B_D[0..63] SB_DQ_0 SB_BS_0 DDR_B_BS[0..2] <15>
DDR_A_D1 AJ41 BG18 DDR_A_BS1 DDR_B_D1 AH46 BB17 DDR_B_BS1
DDR_A_D2 SA_DQ_1 SA_BS_1 DDR_A_BS2 DDR_B_D2 SB_DQ_1 SB_BS_1 DDR_B_BS2
AN38 SA_DQ_2 SA_BS_2 AT25 AP47 SB_DQ_2 SB_BS_2 BB33
DDR_A_D3 AM38 DDR_B_D3 AP46
DDR_A_D4 SA_DQ_3 DDR_A_RAS# DDR_B_D4 SB_DQ_3
AJ36 SA_DQ_4 SA_RAS# BB20 DDR_A_RAS# <14> AJ46 SB_DQ_4
DDR_A_D5 AJ40 BD20 DDR_A_CAS# DDR_B_D5 AJ48 AU17 DDR_B_RAS#
SA_DQ_5 SA_CAS# DDR_A_CAS# <14> SB_DQ_5 SB_RAS# DDR_B_RAS# <15>
DDR_A_D6 AM44 AY20 DDR_A_WE# DDR_B_D6 AM48 BG16 DDR_B_CAS#
SA_DQ_6 SA_WE# DDR_A_WE# <14> SB_DQ_6 SB_CAS# DDR_B_CAS# <15>
DDR_A_D7 AM42 DDR_B_D7 AP48 BF14 DDR_B_WE#
SA_DQ_7 SB_DQ_7 SB_WE# DDR_B_WE# <15>
DDR_A_D8 AN43 DDR_B_D8 AU47
DDR_A_D9 SA_DQ_8 DDR_B_D9 SB_DQ_8
AN44 SA_DQ_9 AU46 SB_DQ_9
DDR_A_D10 AU40 DDR_B_D10 BA48
AT38 SA_DQ_11 AY48 SB_DQ_11
DDR_A_D12 AN41 DDR_B_D12 AT47
DDR_A_D13 SA_DQ_12 DDR_A_DM0 DDR_B_D13 SB_DQ_12
AN39 SA_DQ_13 SA_DM_0 AM37 DDR_A_DM[0..7] <14> AR47 SB_DQ_13
DDR_A_D14 AU44 AT41 DDR_A_DM1 DDR_B_D14 BA47
DDR_A_D15 SA_DQ_14 SA_DM_1 DDR_A_DM2 DDR_B_D15 SB_DQ_14 DDR_B_DM0
AU42 SA_DQ_15 SA_DM_2 AY41 BC47 SB_DQ_15 SB_DM_0 AM47 DDR_B_DM[0..7] <15>
DDR_A_D16 AV39 AU39 DDR_A_DM3 DDR_B_D16 BC46 AY47 DDR_B_DM1
DDR_A_D17 SA_DQ_16 SA_DM_3 DDR_A_DM4 DDR_B_D17 SB_DQ_16 SB_DM_1 DDR_B_DM2
AY44 SA_DQ_17 SA_DM_4 BB12 BC44 SB_DQ_17 SB_DM_2 BD40
DDR_A_D18 BA40 AY6 DDR_A_DM5 DDR_B_D18 BG43 BF35 DDR_B_DM3
DDR_A_D19 SA_DQ_18 SA_DM_5 DDR_A_DM6 DDR_B_D19 SB_DQ_18 SB_DM_3 DDR_B_DM4
BD43 SA_DQ_19 SA_DM_6 AT7 BF43 SB_DQ_19 SB_DM_4 BG11
DDR_A_D20 AV41 AJ5 DDR_A_DM7 DDR_B_D20 BE45 BA3 DDR_B_DM5
DDR_A_D21 SA_DQ_20 SA_DM_7 DDR_B_D21 SB_DQ_20 SB_DM_5 DDR_B_DM6
AY43 BC41 AP1
B
SA_DQ_21 SB_DQ_21 SB_DM_6
A
DDR_A_D22 BB41 DDR_B_D22 BF40 AK2 DDR_B_DM7
DDR_A_D23 SA_DQ_22 DDR_A_DQS0 DDR_B_D23 SB_DQ_22 SB_DM_7
BC40 SA_DQ_23 SA_DQS_0 AJ44 DDR_A_DQS[0..7] <14> BF41 SB_DQ_23
DDR_A_D24 AY37 AT44 DDR_A_DQS1 DDR_B_D24 BG38
DDR_A_D25 SA_DQ_24 SA_DQS_1 DDR_A_DQS2 DDR_B_D25 SB_DQ_24 DDR_B_DQS0
BD38 SA_DQ_25 SA_DQS_2 BA43 BF38 SB_DQ_25 SB_DQS_0 AL47 DDR_B_DQS[0..7] <15>
MEMORY
DDR_A_D26 DDR_A_DQS3 DDR_B_D26 DDR_B_DQS1
MEMORY
AV37 SA_DQ_26 SA_DQS_3 BC37 BH35 SB_DQ_26 SB_DQS_1 AV48
DDR_A_D27 AT36 AW12 DDR_A_DQS4 DDR_B_D27 BG35 BG41 DDR_B_DQS2
DDR_A_D28 SA_DQ_27 SA_DQS_4 DDR_A_DQS5 DDR_B_D28 SB_DQ_27 SB_DQS_2 DDR_B_DQS3
AY38 SA_DQ_28 SA_DQS_5 BC8 BH40 SB_DQ_28 SB_DQS_3 BG37
DDR_A_D29 BB38 AU8 DDR_A_DQS6 DDR_B_D29 BG39 BH9 DDR_B_DQS4
DDR_A_D30 SA_DQ_29 SA_DQS_6 DDR_A_DQS7 DDR_B_D30 SB_DQ_29 SB_DQS_4 DDR_B_DQS5
AV36 SA_DQ_30 SA_DQS_7 AM7 BG34 SB_DQ_30 SB_DQS_5 BB2
C DDR_A_D31 AW36 DDR_B_D31 BH34 AU1 DDR_B_DQS6 C
DDR_A_D32 SA_DQ_31 DDR_B_D32 SB_DQ_31 SB_DQS_6 DDR_B_DQS7
BD13 SA_DQ_32 BH14 SB_DQ_32 SB_DQS_7 AN6
DDR_A_D33 AU11 AJ43 DDR_A_DQS#0 DDR_B_D33 BG12
SA_DQ_33 SA_DQS#_0 DDR_A_DQS#[0..7] <14> SB_DQ_33
DDR_A_D34 BC11 AT43 DDR_A_DQS#1 DDR_B_D34 BH11
DDR_A_D35 SA_DQ_34 SA_DQS#_1 DDR_A_DQS#2 DDR_B_D35 SB_DQ_34 DDR_B_DQS#0
BA12 BA44 BG8 AL46 DDR_B_DQS#[0..7] <15>
SYSTEM
SA_DQ_35 SA_DQS#_2 SB_DQ_35 SB_DQS#_0
SYSTEM
DDR_A_D36 AU13 BD37 DDR_A_DQS#3 DDR_B_D36 BH12 AV47 DDR_B_DQS#1

DDR_A_D37 SA_DQ_36 SA_DQS#_3 DDR_A_DQS#4 DDR_B_D37 SB_DQ_36 SB_DQS#_1 DDR_B_DQS#2
AV13 SA_DQ_37 SA_DQS#_4 AY12 BF11 SB_DQ_37 SB_DQS#_2 BH41
DDR_A_D38 BD12 BD8 DDR_A_DQS#5 DDR_B_D38 BF8 BH37 DDR_B_DQS#3
DDR_A_D39 SA_DQ_38 SA_DQS#_5 DDR_A_DQS#6 DDR_B_D39 SB_DQ_38 SB_DQS#_3 DDR_B_DQS#4
BC12 SA_DQ_39 SA_DQS#_6 AU9 BG7 SB_DQ_39 SB_DQS#_4 BG9
DDR_A_D40 BB9 AM8 DDR_A_DQS#7 DDR_B_D40 BC5 BC2 DDR_B_DQS#5
DDR_A_D41 SA_DQ_40 SA_DQS#_7 DDR_B_D41 SB_DQ_40 SB_DQS#_5 DDR_B_DQS#6
BA9 SA_DQ_41 BC6 SB_DQ_41 SB_DQS#_6 AT2
DDR_A_D42 AU10 DDR_B_D42 AY3 AN5 DDR_B_DQS#7
DDR_A_D43 SA_DQ_42 DDR_B_D43 SB_DQ_42 SB_DQS#_7
AV9 SA_DQ_43 AY1 SB_DQ_43
DDR_A_D44 BA11 BA21 DDR_A_MA0 DDR_B_D44 BF6
SA_DQ_44 SA_MA_0 DDR_A_MA[0..14] <14> SB_DQ_44
DDR_A_D45 BD9 BC24 DDR_A_MA1 DDR_B_D45 BF5 AV17 DDR_B_MA0 DDR_B_MA[0..14] <15>
DDR
SA_DQ_45 SA_MA_1 SB_DQ_45 SB_MA_0
DDR
DDR_A_D46 AY8 BG24 DDR_A_MA2 DDR_B_D46 BA1 BA25 DDR_B_MA1

DDR_A_D47 SA_DQ_46 SA_MA_2 DDR_A_MA3 DDR_B_D47 SB_DQ_46 SB_MA_1 DDR_B_MA2
BA6 SA_DQ_47 SA_MA_3 BH24 BD3 SB_DQ_47 SB_MA_2 BC25
DDR_A_D48 AV5 BG25 DDR_A_MA4 DDR_B_D48 AV2 AU25 DDR_B_MA3
AV7 SA_DQ_49 SA_MA_5 BA24 AU3 SB_DQ_49 SB_MA_4 AW25
DDR_A_D50 AT9 BD24 DDR_A_MA6 DDR_B_D50 AR3 BB28 DDR_B_MA5
AN8 SA_DQ_51 SA_MA_7 BG27 AN2 SB_DQ_51 SB_MA_6 AU28
DDR_A_D52 AU5 BF25 DDR_A_MA8 DDR_B_D52 AY2 AW28 DDR_B_MA7
AU6 SA_DQ_53 SA_MA_9 AW24 AV1 SB_DQ_53 SB_MA_8 AT33
DDR_A_D54 AT5 BC21 DDR_A_MA10 DDR_B_D54 AP3 BD33 DDR_B_MA9
AN10 SA_DQ_55 SA_MA_11 BG26 AR1 SB_DQ_55 SB_MA_10 BB16
DDR_A_D56 AM11 BH26 DDR_A_MA12 DDR_B_D56 AL1 AW33 DDR_B_MA11
AM5 SA_DQ_57 SA_MA_13 BH17 AL2 SB_DQ_57 SB_MA_12 AY33
DDR_A_D58 AJ9 AY25 DDR_A_MA14 DDR_B_D58 AJ1 BH15 DDR_B_MA13
DDR_A_D59 SA_DQ_58 SA_MA_14 DDR_B_D59 SB_DQ_58 SB_MA_13 DDR_B_MA14
AJ8 SA_DQ_59 AH1 SB_DQ_59 SB_MA_14 AU33
DDR_A_D60 AN12 DDR_B_D60 AM2
AM13 SA_DQ_61 AM3 SB_DQ_61
DDR_A_D62 AJ11 DDR_B_D62 AH3
B DDR_A_D63 SA_DQ_62 DDR_B_D63 SB_DQ_62 B
AJ12 SA_DQ_63 AJ3 SB_DQ_63
CANTIGA ES_FCBGA1329 CANTIGA ES_FCBGA1329
GM45@ GM45@
A A

Cantiga(3/7)-DDR3 A/B CH
Custom 1.0
LA7012P
5 4 3 2 1
5 4 3 2 1
Place the resistor within 500mils

(1.27mm)of the (G)MCH
PEGCOMP trace width
U3C and spacing is 20/25 mils.
+3VS
GMCH_PWM L32 +VCC_PEG
D <22> GMCH_PWM L_BKLT_CTRL D
ENBKL G32 T37
<27> ENBKL L_BKLT_EN PEG_COMPI
R730 1 2 10K_0402_5% L_CTRL_CLK L_CTRL_CLK M32 T36 PEGCOMP 1 2
L_CTRL_DATA L_CTRL_CLK PEG_COMPO
M33 L_CTRL_DATA
R731 1 2 10K_0402_5% L_CTRL_DATA <22> EDID_CLK EDID_CLK K33 R733 49.9_0402_1%
EDID_DATA L_DDC_CLK
<22> EDID_DATA J33 L_DDC_DATA PEG_RX#_0 H44
1 2 EDID_CLK <22> GMCH_ENVDD GMCH_ENVDD M29 J46 Please check Power
R732 2.2K_0402_5% L_VDD_EN PEG_RX#_1
PEG_RX#_2 L44 source if want
1 2 EDID_DATA 1 2 LVDS_IBG C44 L40
R734 2.2K_0402_5% R735 2.37K_0402_1% LVDS_IBG PEG_RX#_3 support IAMT
B43 LVDS_VBG PEG_RX#_4 N41
E37 LVDS_VREFH PEG_RX#_5 P48
E38 LVDS_VREFL PEG_RX#_6 N44
For Cantiga:2.37kohm PEG_RX#_7 T43
ENBKL For Crestline:2.4kohm LVDS_ACLK# C41 U43
<22> LVDS_ACLK# LVDSA_CLK# PEG_RX#_8
For Calero: 1.5Kohm LVDS_ACLK C40 Y43
<22> LVDS_ACLK LVDSA_CLK PEG_RX#_9
2
B37 LVDSB_CLK# PEG_RX#_10 Y48

R259 A37 Y36
LVDSB_CLK PEG_RX#_11
LVDS
100K_0402_1% AA43
LVDS_A0# PEG_RX#_12
<22> LVDS_A0# H47 LVDSA_DATA#_0 PEG_RX#_13 AD37
LVDS_A1# E46 AC47
<22> LVDS_A1#
1
LVDS_A2# LVDSA_DATA#_1 PEG_RX#_14

<22> LVDS_A2# G40 LVDSA_DATA#_2 PEG_RX#_15 AD39
A40 LVDSA_DATA#_3
PEG_RX_0 H43
Note: All LVDS data LVDS_A0 H48 J44
<22> LVDS_A0 LVDSA_DATA_0 PEG_RX_1
LVDS_A1 D45 L43
signals/and it's compliments <22> LVDS_A1
LVDS_A2 LVDSA_DATA_1 PEG_RX_2
GRAPHICS
<22> LVDS_A2 F40 LVDSA_DATA_2 PEG_RX_3 L41
should be routed B40 N40
Differentially LVDSA_DATA_3 PEG_RX_4
C PEG_RX_5 P47 C
A41 LVDSB_DATA#_0 PEG_RX_6 N43
H38 LVDSB_DATA#_1 PEG_RX_7 T42
G37 LVDSB_DATA#_2 PEG_RX_8 U42
J37 LVDSB_DATA#_3 PEG_RX_9 Y42
PEG_RX_10 W47
B42 LVDSB_DATA_0 PEG_RX_11 Y37
G38 LVDSB_DATA_1 PEG_RX_12 AA42
F37 LVDSB_DATA_2 PEG_RX_13 AD36
K37 LVDSB_DATA_3 PEG_RX_14 AC48
PCI-EXPRESS
PEG_RX_15 AD40
PEG_TX#_0 J41
PEG_TX#_1 M46
R481 1 2 75_0402_5% TVA_DAC F25 M47
R482 1 TVA_DAC PEG_TX#_2
2 75_0402_5% TVB_DAC H25 TVB_DAC PEG_TX#_3 M40
R483 1 2 75_0402_5% TVC_DAC K25 M42
TVC_DAC PEG_TX#_4
PEG_TX#_5 R48
TV
H24 TV_RTN PEG_TX#_6 N38
PEG_TX#_7 T40
PEG_TX#_8 U37
PEG_TX#_9 U40
C31 TV_DCONSEL_0 PEG_TX#_10 Y40
E32 TV_DCONSEL_1 PEG_TX#_11 AA46
PEG_TX#_12 AA37
PEG_TX#_13 AA40
B
Layout Note: Place 150 ȍ termination PEG_TX#_14 AD43
AC46 B
PEG_TX#_15
resistors close to GMCH DAC_BLU E28 J42
<21> DAC_BLU CRT_BLUE PEG_TX_0
R736 1 2 150_0402_1% DAC_RED L46
R72 1 150_0402_1% DAC_GRN DAC_GRN PEG_TX_1
2 <21> DAC_GRN G28 CRT_GREEN PEG_TX_2 M48
R73 1 2 150_0402_1% DAC_BLU M39
PEG_TX_3
VGA
DAC_RED J28 M43
<21> DAC_RED CRT_RED PEG_TX_4
PEG_TX_5 R47
G29 CRT_IRTN PEG_TX_6 N37
PEG_TX_7 T39
<21> CRT_DDC_CLK CRT_DDC_CLK H32 U36
CRT_DDC_DATA CRT_DDC_CLK PEG_TX_8
<21> CRT_DDC_DATA J32 CRT_DDC_DATA PEG_TX_9 U39
1 2 CRT_HSYNC_R J29 Y39
<21> CRT_HSYNC CRT_HSYNC PEG_TX_10
R74 33_0402_5% E29 Y46
CRT_TVO_IREF PEG_TX_11
AA36
20mil PEG_TX_12
AA39
CRT_VSYNC_R PEG_TX_13
<21> CRT_VSYNC 1 2 L29 CRT_VSYNC PEG_TX_14 AD42
R75 33_0402_5% AD46
PEG_TX_15
1
10/01
change R74,R75 from 30ohm to 33ohm GM45@ CANTIGA ES_FCBGA1329
R78
1.02K_0402_1%
2
A For Cantiga:1.02kohm A
For Crestline:1.3kohm
For Calero: 255ohm

Cantiga(4/7)-VGA/LVDS
Custom 1.0
LA7012P
5 4 3 2 1
5 4 3 2 1
+3VS +3VS_DAC_CRT
1 2
+1.05VS
VCC_AXF: 321.35mA
0.022U_0402_16V7K
R79 20 mils (10UF*1, 1UF*1)
0.1U_0402_16V4Z
10U_0805_10V4Z
0_0603_5% U3H OSCON +1.05VS_DPLLA
1 1 1 R80 +1.05VS
VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1) 220U_6.3V_M 852mA +V1.05VS_AXF
C62
C63
C64
73mA U13 C65 1 2 +1.05VS
VTT_1
4.7U_0805_10V4Z
+3VS_DAC_CRT B27 VCCA_CRT_DAC_1 VTT_2 T13 1
2 2 2
0.1U_0402_16V4Z
10U_0805_10V4Z
A26 U12 1 MCK3225151YZF 1210 1 2
VCCA_CRT_DAC_2 VTT_3
10U_0805_10V4Z
1U_0603_10V4Z
T12 +
VTT_4 1 1
C66
VCCA_DAC_BG: 2.68mA (0.1UF*1, 0.01UF*1) U11 R81
VTT_5
C67
C68
5mA T11 1 1 0_0603_5%
VTT_6 2 2
C69
C839
CRT
+3VS_DAC_BG A25 VCCA_DAC_BG VTT_7 U10
T10 2 2
D +3VS_DAC_BG VTT_8 D
+3VS B25 U9
VSSA_DAC_BG VTT_9 2 2
VTT_10 T9
1 2 VTT_11 U8 +1.05VS_DPLLA
0.022U_0402_16V7K
R82 32.4mA T8 VCC_SM_CK: 119.85mA
VTT_12 +1.05VS_DPLLB: 64.8mA
0.1U_0402_16V4Z
10U_0805_10V4Z
4.7U_0805_10V4Z
VTT
10_0603_5% F47 U7
+1.05VS_DPLLA VCCA_DPLLA VTT_13 (470UF*1, 0.1UF*1) (10UF*1, 0.1UF*1)
C74
1 1 1 32.4mA VTT_14 T7 1 1
C73
+1.05VS_DPLLB L48 VCCA_DPLLB VTT_15 U6 +1.5V_SM_CK
+1.05VS_DPLLB
C71
C72
C75
24mA T6 +1.5V
VTT_16 R83
PLL
AD1 U5 R737
0.47U_0402_6.3V6K
2 2 2 +1.05VS_HPLL VCCA_HPLL VTT_17 2 2
+1.8V_TXLVDS
139.2mA VTT_18 T5 1 2 +1.05VS 1 2
10U_0805_10V4Z
0.1U_0402_16V4Z
+1.05VS_MPLL AE1 V3 0_0805_5%
VCCA_MPLL VTT_19
0.1U_0402_16V4Z
10U_0805_10V4Z
10mA U3 MCK3225151YZF 1210 1
VTT_20
C79
V2 1 1 1
VTT_21
C80
A PEG A LVDS
1 J48 U2
VCCA_LVDS VTT_22
C77
C78
1000P_0402_50V7K T2
C76 VTT_23 2
J47 V1
VSSA_LVDS VTT_24 2 2 2
U1
2 VTT_25
0.41mA
+1.5VS_PEG_BG: 0.414mA AD48
VCCA_PEG_BG
(0.1UF*1) +1.5VS_PEG_BG
R738 20 mils 50mA +1.05VS_HPLL
+1.5VS 2 1 AA48
VCCA_PEG_PLL +1.05VS_HPLL: 24mA
0_0603_5% +1.05VS_PEGPLL
1 L33 (4.7UF*1, 0.1UF*1) +1.5VS_TVDAC +1.5VS
C83 R739
2 1 +1.05VS
MBK2012121YZF_2P 2 1
0.1U_0402_16V4Z 0_0603_5%
2 POWER
0.022U_0402_16V7K
0.1U_0402_16V4Z
10U_0805_10V4Z
AR20 1 1
VCCA_SM_1 C84 C85
AP20 1 1 1
+1.05VS +1.05VS_A_SM VCCA_SM_2
AN20
VCCA_SM_3
C87
C88
C89
R740 747.5mA AR17 0.1U_0402_16V4Z 2.2U_0603_6.3V4Z
VCCA_SM_4 2 2
A SM
1 2 AP17
VCCA_SM_5 440mA 2 2 2
VCCD_TVDAC: 58.696mA
VCCA_SM:720mA OSCON 1 0_0805_5% AN17 B22
VCCA_SM_6 VCC_AXF_1 +V1.05VS_AXF (0.1UF*1, 0.01UF*1)
AXF
(22UF*2, 4.7UF*1, 1UF*1) 1 1 1 AT16 B21
C90 + C91 4.7U_0805_10V4Z C93 VCCA_SM_7 VCC_AXF_2
AR16 A21
220U_6.3V_M C92 VCCA_SM_8 VCC_AXF_3
C AP16 C
10U_0805_10V4Z 1U_0603_10V4Z VCCA_SM_9
2 2 2 2
149.5mA
BF21 +1.5V_SM_CK
VCC_SM_CK_1 +1.05VS_MPLL +1.8V_TXLVDS
SM CK
+1.05VS_A_SM_CK VCC_SM_CK_2
BH20 1.05VS_MPLL: 139.2mA 20 mils
VCCA_SM_CK: 220mA BG20 L34
R741
37.95mA VCC_SM_CK_3
BF20
(22UF*1, 0.1UF*1) R742
(22UF*1, 2.2UF*1, 0.1UF*1) 2 1 AP28
VCC_SM_CK_4
2 1 2 1
VCCA_SM_CK_1 +1.05VS +1.8VS
1U_0402_6.3V4Z
1U_0603_10V4Z
1000P_0402_50V7K
0_0603_5% AN28 MBK2012121YZF_2P 0_0603_5%
VCCA_SM_CK_2
10U_0805_10V4Z
0.1U_0402_16V4Z
10U_0805_10V4Z
AP25
VCCA_SM_CK_3 +1.8V_TXLVDS: 118.8mA
1 1 1 1 AN25
VCCA_SM_CK_4 80mA +1.8V_TXLVDS 1 1 1 1 (22UF*1, 1000PF*1)
C95
C97
C101
C102
AN24 K47 C99 C100
VCCA_SM_CK_5 VCC_TX_LVDS
C96
A CK
C98
AM28
VCCA_SM_CK_NCTF_1 +3VS_HV 0.1U_0402_16V4Z 2.2U_0603_6.3V4Z
AM26
2 2 2 2 VCCA_SM_CK_NCTF_2 2 2 2 2
AM25
VCCA_SM_CK_NCTF_3 105.3mA
0.1U_0402_16V4Z
AL25 C35
VCCA_SM_CK_NCTF_4 VCC_HV_1
AM24 B35 1
HV
AL24 A35
C103
AM23
VCCA_SM_CK_NCTF_7
AL23
VCCA_SM_CK_NCTF_8 2
1782mA
+3VS_TVDAC: 40mA VCC_PEG_1
V48 +VCC_PEG +1.5VS_PEG_PLL: 50mA +1.05VS
(0.1UF*1, 0.01UF*1 for U48 (0.1UF*1)
VCC_PEG_2 +1.05VS_PEGPLL +VCC_PEG
PEG
V47
+3VS each DAC) VCC_PEG_3 L1 R744
+3VS_TVDAC
79mA VCC_PEG_4
U47
R743 +3VS_TVDAC B24 U46 BLM18PG121SN1D_0603 2 1
VCCA_TV_DAC_1 VCC_PEG_5 0_0805_5%
1 2 A24
VCCA_TV_DAC_2 2 1 +1.05VS
10U_0805_10V4Z
TV
OSCON 1
0.1U_0402_16V4Z
0_0603_5% 1
C109
456mA C104 +
1 1 1 1
C107
C105 C106 A32 AH48 +VCC_DMI C108 220U_6.3V_M
VCC_HDA VCC_DMI_1
HDA
0.022U_0402_16V7K 0.1U_0402_16V4Z AF48
VCC_DMI_2 2 2
DMI
AH47 VCC_DMI: 456mA 2.2U_0603_6.3V4Z
2 2 VCC_DMI_3 2 2
AG47 (0.1UF*1)
VCC_DMI_4
35mA
+1.5VS_TVDAC M25
VCCD_TVDAC
1mA
D TV/CRT
B B
+1.5VS_QDAC L28
VCCD_QDAC
20mils
157.2mA +1.05VS
+1.05VS_HPLL AF1
VCCD_HPLL +VCC_DMI
50mA VTTLF1
A8
+1.05VS_PEGPLL AA47 L1 R745
VCCD_PEG_PLL VTTLF2 +VCCP_D
VTTLF
AB2 2 1
VTTLF3 0_0805_5%
30mA
0.47U_0402_6.3V6K
0.47U_0402_6.3V6K
0.47U_0402_6.3V6K
1U_0603_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
+1.8V_LVDS M38 1 1 1
VCCD_LVDS_1
LVDS
L37 D38 R746 @ R747 1 1 1

VCCD_LVDS_2
C111
C112
C113
C114
C115
C116
+1.05VS 2 @ 1 2 1 2 1 +3VS_HV
RB751V_SOD323 10_0402_5% 0_0402_5%
2 2 2
CANTIGA ES_FCBGA1329 2 2 2
+3VS
GM45@
10/01 Danson
Change D38 from SC1H751H010 to SCS00000Z00 .
VCCD_QDAC: 48.363mA 1.8V_LVDS: 60.311111mA

+1.5VS_QDAC (0.1UF*1, 0.01UF*1) +1.8V_LVDS (1UF*1)
R748
R98
2 1 +1.5VS
1U_0402_6.3V4Z
10U_0805_10V4Z
0_0603_5% 2 1 +1.8VS
0.1U_0402_16V4Z
10U_0805_10V4Z
0_0603_5%
1U_0603_10V4Z
1 1 1 1 1
C840
A A
C117
C118
C119
C120
2 2 2 2 2

Cantiga(6/7)-VCC-1
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA7012P
5 4 3 2 1
5 4 3 2 1
U3F
+1.05VS
Check : power
4140mA VCC_AXG_NTCF_1 W28 8000mA
AP33 V28 C845 C129
VCC_SM_1 VCC_AXG_NCTF_2 0.1U_0402_16V4Z 0.22U_0402_10V4Z
AN33 VCC_SM_2 VCC_AXG_NCTF_3 W26
+1.5V BH32 VCC_SM_3 VCC_AXG_NCTF_4 V26
BG32 VCC_SM_4 VCC_AXG_NCTF_5 W25 1 1 1 C841
10U_0805_10V4Z
0.01U_0402_16V7K
BF32 V25 4.7U_0603_6.3V6K
+1.05VS VCC_SM_5 VCC_AXG_NCTF_6
OSCON 1 BD32 VCC_SM_6 VCC_AXG_NCTF_7 W24
U3G 1 2 BC32 V24
VCC_SM_7 VCC_AXG_NCTF_8 2 2 2
C842
C846
C844 + BB32 W23
VCC_SM_8 VCC_AXG_NCTF_9
VCC
AG34 220U_6.3V_M BA32 V23
D VCC_1 VCC_SM_9 VCC_AXG_NCTF_10 D
AC34 VCC_2 AY32 VCC_SM_10 VCC_AXG_NCTF_11 AM21
2 2 1
AB34 VCC_3 AW32 VCC_SM_11 VCC_AXG_NCTF_12 AL21
AA34 VCC_4 AV32 VCC_SM_12 VCC_AXG_NCTF_13 AK21
Y34 VCC_5 AU32 VCC_SM_13 VCC_AXG_NCTF_14 W21
V34 AT32 V21
VCC CORE
SM
VCC_6 VCC_SM_14 VCC_AXG_NCTF_15
U34 VCC_7 AR32 VCC_SM_15 VCC_AXG_NCTF_16 U21
3060mA AM33 VCC_8 AP32 VCC_SM_16 VCC_AXG_NCTF_17 AM20
AK33 VCC_9 AN32 VCC_SM_17 VCC_AXG_NCTF_18 AK20
AJ33 VCC_10 BH31 VCC_SM_18 VCC_AXG_NCTF_19 W20
0.22U_0402_10V4Z
0.22U_0402_10V4Z
0.1U_0402_16V4Z
AG33 VCC_11 BG31 VCC_SM_19 VCC_AXG_NCTF_20 U20

10U_0805_10V4Z
AF33 VCC_12 BF31 VCC_SM_20 VCC_AXG_NCTF_21 AM19

1 1 1 1 BG30 VCC_SM_21 VCC_AXG_NCTF_22 AL19
C847
C848
C849
BH29 VCC_SM_22 VCC_AXG_NCTF_23 AK19

C843
BG29 VCC_SM_23 VCC_AXG_NCTF_24 AJ19

AE33 VCC_13 BF29 VCC_SM_24 VCC_AXG_NCTF_25 AH19
2 2 2 2
AC33 VCC_14 1 1 BD29 VCC_SM_25 VCC_AXG_NCTF_26 AG19
AA33 VCC_15 BC29 VCC_SM_26 VCC_AXG_NCTF_27 AF19
Y33 C850 C139 BB29 AE19
VCC_16 0.1U_0402_16V4Z 0.1U_0402_16V4Z VCC_SM_27 VCC_AXG_NCTF_28
W33 VCC_17 BA29 VCC_SM_28 VCC_AXG_NCTF_29 AB19
POWER @ 2 2 @
V33 VCC_18 AY29 VCC_SM_29 VCC_AXG_NCTF_30 AA19
GFX NCTF
U33 VCC_19 AW29 VCC_SM_30 VCC_AXG_NCTF_31 Y19
AH28 VCC_20 AV29 VCC_SM_31 VCC_AXG_NCTF_32 W19
AF28 VCC_21 AU29 VCC_SM_32 VCC_AXG_NCTF_33 V19
AC28 VCC_22 AT29 VCC_SM_33 VCC_AXG_NCTF_34 U19
AA28 VCC_23 AR29 VCC_SM_34 VCC_AXG_NCTF_35 AM17
AJ26 VCC_24 EMI +1.5V decoupling AP29 VCC_SM_35 VCC_AXG_NCTF_36 AK17
AG26 VCC_25 VCC_AXG_NCTF_37 AH17
AE26 VCC_26 VCC_AXG_NCTF_38 AG17
AC26 VCC_27 VCC_AXG_NCTF_39 AF17
AH25 +1.05VS BA36 AE17
VCC_28 VCC_SM_36/NC VCC_AXG_NCTF_40
AG25 VCC_29 BB24 VCC_SM_37/NC VCC_AXG_NCTF_41 AC17
VCC
AF25 VCC_30 BD16 VCC_SM_38/NC VCC_AXG_NCTF_42 AB17
C AG24 AM32 BB21 Y17 C
VCC_31 VCC_NCTF_1 VCC_SM_39/NC VCC_AXG_NCTF_43
AJ23 VCC_32 VCC_NCTF_2 AL32 AW16 VCC_SM_40/NC VCC_AXG_NCTF_44 W17
AH23 VCC_33 VCC_NCTF_3 AK32 AW13 VCC_SM_41/NC VCC_AXG_NCTF_45 V17
AF23 VCC_34 VCC_NCTF_4 AJ32 AT13 VCC_SM_42/NC VCC_AXG_NCTF_46 AM16
T32 VCC_35 VCC_NCTF_5 AH32 VCC_AXG_NCTF_47 AL16
AG32 AK16
POWER
VCC_NCTF_6 VCC_AXG_NCTF_48
VCC_NCTF_7 AE32 VCC_AXG_NCTF_49 AJ16
VCC_NCTF_8 AC32 VCC_AXG_NCTF_50 AH16
VCC_NCTF_9 AA32 VCC_AXG_NCTF_51 AG16
VCC_NCTF_10 Y32 VCC_AXG_NCTF_52 AF16
VCC_NCTF_11 W32 Y26 VCC_AXG_1 VCC_AXG_NCTF_53 AE16
VCC_NCTF_12 U32 AE25 VCC_AXG_2 VCC_AXG_NCTF_54 AC16
VCC_NCTF_13 AM30 AB25 VCC_AXG_3 VCC_AXG_NCTF_55 AB16
AL30 +1.05VS AA25 AA16
VCC_NCTF_14 VCC_AXG_4 VCC_AXG_NCTF_56
VCC_NCTF_15 AK30 AE24 VCC_AXG_5 VCC_AXG_NCTF_57 Y16
AH30 10U_0805_10V4Z 0.1U_0402_16V4Z AC24 W16
VCC_NCTF_16 VCC_AXG_6 VCC_AXG_NCTF_58
VCC_NCTF_17 AG30 AA24 VCC_AXG_7 VCC_AXG_NCTF_59 V16
VCC_NCTF_18 AF30 1 Y24 VCC_AXG_8 VCC_AXG_NCTF_60 U16
VCC_NCTF_19 AE30 1 1 1 1 AE23 VCC_AXG_9
AC30 C851 + C853 C854 C138 AC23
NCTF
VCC_NCTF_20 VCC_AXG_10
VCC_NCTF_21 AB30 AB23 VCC_AXG_11
AA30 1U_0603_10V4Z AA23
VCC_NCTF_22 2 2 2 2 2 VCC_AXG_12
VCC_NCTF_23 Y30 AJ21 VCC_AXG_13
VCC_NCTF_24 W30 AG21 VCC_AXG_14
V30 C852 10U_0805_10V4Z AE21
VCC_NCTF_25 220U_6.3V_M VCC_AXG_15
VCC_NCTF_26 U30 AC21 VCC_AXG_16
VCC
VCC_NCTF_27 AL29 OSCON AA21 VCC_AXG_17

VCC_NCTF_28 AK29 Y21 VCC_AXG_18
VCC
VCC_NCTF_29 AJ29 AH20 VCC_AXG_19
VCC_NCTF_30 AH29 AF20 VCC_AXG_20
VCC_NCTF_31 AG29 AE20 VCC_AXG_21
VCC_NCTF_32 AE29 AC20 VCC_AXG_22
B AC29 AB20 B
AA29 AA20
GFX
VCC_NCTF_35 Y29 T17 VCC_AXG_25
VCC_NCTF_36 W29 T16 VCC_AXG_26
VCC_NCTF_37 V29 AM15 VCC_AXG_27
VCC_NCTF_38 AL28 AL15 VCC_AXG_28
VCC_NCTF_39 AK28 AE15 VCC_AXG_29
VCC_NCTF_40 AL26 AJ15 VCC_AXG_30
VCC_NCTF_41 AK26 AH15 VCC_AXG_31
VCC_NCTF_42 AK25 AG15 VCC_AXG_32
VCC_NCTF_43 AK24 AF15 VCC_AXG_33
VCC_NCTF_44 AK23 AB15 VCC_AXG_34
AA15 VCC_AXG_35
Y15 VCC_AXG_36
V15 VCC_AXG_37
U15 VCC_AXG_38
AN14 VCC_AXG_39
AM14 PLACE AS CLOSE PIN AS COULD.
VCC_AXG_40
U14 AV44 VCCSM_LF1
VCC SM LF
VCC_AXG_41 VCC_SM_LF1
T14 VCC_AXG_42 VCC_SM_LF2 BA37 VCCSM_LF2
VCC_SM_LF3 AM40 VCCSM_LF3
CANTIGA ES_FCBGA1329 AV21 VCCSM_LF4
VCC_SM_LF4
GM45@
VCC_SM_LF5 AY5 VCCSM_LF5
T11 VCC_AXG_SENSE AJ14 AM10 VCCSM_LF6
VSS_AXG_SENSE VCC_AXG_SENSE VCC_SM_LF6
T12 AH14 VSS_AXG_SENSE VCC_SM_LF7 BB13 VCCSM_LF7
C140
C141
C142
C143
C855
C856
C857
1 1 1 1 1 1 1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.22U_0402_10V4Z
0.22U_0402_10V4Z
0.47U_0402_6.3V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 2 2 2 2 2 2
A GM45@ A

Cantiga(6/7)-VCC-1
1.0
LA7012P
5 4 3 2 1
5 4 3 2 1
U3I U3J
AU48 VSS_1 VSS_100 AM36 BG21 VSS_199 VSS_297 AH8

AR48 VSS_2 VSS_101 AE36 L12 VSS_200 VSS_298 Y8
AL48 VSS_3 VSS_102 P36 AW21 VSS_201 VSS_299 L8
BB47 VSS_4 VSS_103 L36 AU21 VSS_202 VSS_300 E8
AW47 VSS_5 VSS_104 J36 AP21 VSS_203 VSS_301 B8
AN47 VSS_6 VSS_105 F36 AN21 VSS_204 VSS_302 AY7
AJ47 VSS_7 VSS_106 B36 AH21 VSS_205 VSS_303 AU7
AF47 VSS_8 VSS_107 AH35 AF21 VSS_206 VSS_304 AN7
AD47 VSS_9 VSS_108 AA35 AB21 VSS_207 VSS_305 AJ7
D AB47 Y35 R21 AE7 D
VSS_10 VSS_109 VSS_208 VSS_306
Y47 VSS_11 VSS_110 U35 M21 VSS_209 VSS_307 AA7
T47 VSS_12 VSS_111 T35 J21 VSS_210 VSS_308 N7
N47 VSS_13 VSS_112 BF34 G21 VSS_211 VSS_309 J7
L47 VSS_14 VSS_113 AM34 BC20 VSS_212 VSS_310 BG6
G47 VSS_15 VSS_114 AJ34 BA20 VSS_213 VSS_311 BD6
BD46 VSS_16 VSS_115 AF34 AW20 VSS_214 VSS_312 AV6
BA46 VSS_17 VSS_116 AE34 AT20 VSS_215 VSS_313 AT6
AY46 VSS_18 VSS_117 W34 AJ20 VSS_216 VSS_314 AM6
AV46 VSS_19 VSS_118 B34 AG20 VSS_217 VSS_315 M6
AR46 VSS_20 VSS_119 A34 Y20 VSS_218 VSS_316 C6
AM46 VSS_21 VSS_120 BG33 N20 VSS_219 VSS_317 BA5
V46 VSS_22 VSS_121 BC33 K20 VSS_220 VSS_318 AH5
R46 VSS_23 VSS_122 BA33 F20 VSS_221 VSS_319 AD5
P46 VSS_24 VSS_123 AV33 C20 VSS_222 VSS_320 Y5
H46 VSS_25 VSS_124 AR33 A20 VSS_223 VSS_321 L5
F46 VSS_26 VSS_125 AL33 BG19 VSS_224 VSS_322 J5
BF44 VSS_27 VSS_126 AH33 A18 VSS_225 VSS_323 H5
AH44 VSS_28 VSS_127 AB33 BG17 VSS_226 VSS_324 F5
AD44 VSS_29 VSS_128 P33 BC17 VSS_227 VSS_325 BE4
AA44 VSS_30 VSS_129 L33 AW17 VSS_228
Y44 VSS_31 VSS_130 H33 AT17 VSS_229 VSS_327 BC3
U44 VSS_32 VSS_131 N32 R17 VSS_230 VSS_328 AV3
T44 VSS_33 VSS_132 K32 M17 VSS_231 VSS_329 AL3
M44 VSS_34 VSS_133 F32 H17 VSS_232 VSS_330 R3
F44
BC43
VSS_35
VSS_36
VSS_134
VSS_135
C32
A31
C17 VSS_233 VSS VSS_331
VSS_332
P3
F3
AV43 VSS_37 VSS_136 AN29 BA16 VSS_235 VSS_333 BA2
AU43 VSS_38 VSS_137 T29 VSS_334 AW2
AM43 VSS_39 VSS_138 N29 AU16 VSS_237 VSS_335 AU2
J43 VSS_40 VSS_139 K29 AN16 VSS_238 VSS_336 AR2
C43 VSS_41 VSS_140 H29 N16 VSS_239 VSS_337 AP2
C C
BG42
AY42
VSS_42
VSS_43
VSS VSS_141
VSS_142
F29
A29
K16
G16
VSS_240
VSS_241
VSS_338
VSS_339
AJ2
AH2
AT42 VSS_44 VSS_143 BG28 E16 VSS_242 VSS_340 AF2
AN42 VSS_45 VSS_144 BD28 BG15 VSS_243 VSS_341 AE2
AJ42 VSS_46 VSS_145 BA28 AC15 VSS_244 VSS_342 AD2
AE42 VSS_47 VSS_146 AV28 W15 VSS_245 VSS_343 AC2
N42 VSS_48 VSS_147 AT28 A15 VSS_246 VSS_344 Y2
L42 VSS_49 VSS_148 AR28 BG14 VSS_247 VSS_345 M2
BD41 VSS_50 VSS_149 AJ28 AA14 VSS_248 VSS_346 K2
AU41 VSS_51 VSS_150 AG28 C14 VSS_249 VSS_347 AM1
AM41 VSS_52 VSS_151 AE28 BG13 VSS_250 VSS_348 AA1
AH41 VSS_53 VSS_152 AB28 BC13 VSS_251 VSS_349 P1
AD41 VSS_54 VSS_153 Y28 BA13 VSS_252 VSS_350 H1
AA41 VSS_55 VSS_154 P28
Y41 VSS_56 VSS_155 K28 VSS_351 U24
U41 VSS_57 VSS_156 H28 AN13 VSS_255 VSS_352 U28
T41 VSS_58 VSS_157 F28 AJ13 VSS_256 VSS_353 U25
M41 VSS_59 VSS_158 C28 AE13 VSS_257 VSS_354 U29
G41 VSS_60 VSS_159 BF26 N13 VSS_258
B41 VSS_61 VSS_160 AH26 L13 VSS_259 VSS_NCTF_1 AF32
BG40 VSS_62 VSS_161 AF26 G13 VSS_260 VSS_NCTF_2 AB32
BB40 VSS_63 VSS_162 AB26 E13 VSS_261 VSS_NCTF_3 V32
AV40 VSS_64 VSS_163 AA26 BF12 VSS_262 VSS_NCTF_4 AJ30
AN40 VSS_65 VSS_164 C26 AV12 VSS_263 VSS_NCTF_5 AM29
H40 VSS_66 VSS_165 B26 AT12 VSS_264 VSS_NCTF_6 AF29
E40 VSS_67 VSS_166 BH25 AM12 VSS_265 VSS_NCTF_7 AB29
AT39 BD25 AA12 U26
VSS NCTF
VSS_68 VSS_167 VSS_266 VSS_NCTF_8

AM39 VSS_69 VSS_168 BB25 J12 VSS_267 VSS_NCTF_9 U23
AJ39 VSS_70 VSS_169 AV25 A12 VSS_268 VSS_NCTF_10 AL20
AE39 VSS_71 VSS_170 AR25 BD11 VSS_269 VSS_NCTF_11 V20
N39 VSS_72 VSS_171 AJ25 BB11 VSS_270 VSS_NCTF_12 AC19
L39 VSS_73 VSS_172 AC25 AY11 VSS_271 VSS_NCTF_13 AL17
B B39 Y25 AN11 AJ17 B
VSS_74 VSS_173 VSS_272 VSS_NCTF_14
BH38 VSS_75 VSS_174 N25 AH11 VSS_273 VSS_NCTF_15 AA17
BC38 VSS_76 VSS_175 L25 VSS_NCTF_16 U17
BA38 VSS_77 VSS_176 J25 Y11 VSS_275
AU38 VSS_78 VSS_177 G25 N11 VSS_276
AH38 VSS_79 VSS_178 E25 G11 VSS_277 VSS_SCB_1 BH48
AD38 VSS_80 VSS_179 BF24 C11 VSS_278 VSS_SCB_2 BH1
AA38 VSS_81 VSS_180 AD12 BG10 VSS_279 VSS_SCB_3 A48
Y38 AY24 AV10 C1
VSS SCB
VSS_82 VSS_181 VSS_280 VSS_SCB_4

U38 VSS_83 VSS_182 AT24 AT10 VSS_281 VSS_SCB_5 A3
T38 VSS_84 VSS_183 AJ24 AJ10 VSS_282
J38 VSS_85 VSS_184 AH24 AE10 VSS_283
F38 VSS_86 VSS_185 AF24 AA10 VSS_284
C38 VSS_87 VSS_186 AB24 M10 VSS_285
BF37 VSS_88 VSS_187 R24 BF9 VSS_286 NC_26 E1
BB37 VSS_89 VSS_188 L24 BC9 VSS_287 NC_27 D2
AW37 VSS_90 VSS_189 K24 AN9 VSS_288 NC_28 C3
AT37 VSS_91 VSS_190 J24 AM9 VSS_289 NC_29 B4
AN37 VSS_92 VSS_191 G24 AD9 VSS_290 NC_30 A5
AJ37 VSS_93 VSS_192 F24 G9 VSS_291 NC_31 A6
H37 VSS_94 VSS_193 E24 B9 VSS_292 NC_32 A43
C37 VSS_95 VSS_194 BH23 BH8 VSS_293 NC_33 A44
BG36 VSS_96 VSS_195 AG23 BB8 VSS_294 NC_34 B45
BD36 Y23 AV8 C46
NC
VSS_97 VSS_196 VSS_295 NC_35

AK15 VSS_98 VSS_197 B23 AT8 VSS_296 NC_36 D47
AU36 VSS_99 VSS_198 A23 NC_37 B47
VSS_199 AJ6 NC_38 A46
NC_39 F48
CANTIGA ES_FCBGA1329 E48
GM45@ NC_40
NC_41 C48
NC_42 B48
A A
GM45@

Cantiga(7/7)-GND
Custom 1.0
LA7012P
5 4 3 2 1
5 4 3 2 1
+VREF_DQ_DIMMA +1.5V +1.5V

4BA2/6W
<9> DDR_A_D[0..63] +1.5V
<9> DDR_A_DM[0..7]
1
JDIMM1
+VREF_DQ_DIMMA 1 2
<9> DDR_A_DQS[0..7] Pre MP ADD for ESD solution R297
VREF_DQ VSS1 DDR_A_D4 1K_0402_1%
3 VSS2 DQ4 4 <9> DDR_A_DQS#[0..7] +1.5V +VREF_DQ_DIMMA
0.1U_0402_10V6K
2.2U_0603_6.3V4Z
DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5
C303
C347
1 1 DDR_A_D1 7 8 Near R297
2
DQ1 VSS3 DDR_A_DQS#0 <9> DDR_A_MA[0..14]
9 VSS4 DQS#0 10
DDR_A_DM0 11 12 DDR_A_DQS0 1
DM0 DQS0
13 VSS5 VSS6 14
1
2 2 DDR_A_D2 DDR_A_D6 C659
15 DQ2 DQ6 16
D DDR_A_D3 17 18 DDR_A_D7 D
DQ3 DQ7 0.1U_0402_16V4Z
2 R305
19 VSS7 VSS8 20
DDR_A_D8 21 22 DDR_A_D12 1K_0402_1%
DDR_A_D9 DQ8 DQ12 DDR_A_D13
23 24
2
DQ9 DQ13
25 VSS9 VSS10 26
DDR_A_DQS#1 27 28 DDR_A_DM1
DDR_A_DQS1 DQS#1 DM1 SM_DRAMRST#
29 DQS1 RESET# 30 SM_DRAMRST# <8,15>
31 VSS11 VSS12 32
35 DQ11 DQ15 36 For Arranale only +VREF_DQ_DIMMA
37 VSS13 VSS14 38
DDR_A_D16 39 DQ16 DQ20 40 DDR_A_D20 supply from a external 1.5V voltage divide
DQ17 DQ21 circuit.
43 VSS15 VSS16 44
DDR_A_DQS#2 45 DQS#2 DM2 46 DDR_A_DM2 07/17/2009
DDR_A_DQS2 47 48
DQS2 VSS17 DDR_A_D22
49 VSS18 DQ22 50
DDR_A_D19 DQ18 DQ23
53 DQ19 VSS19 54
55 56 DDR_A_D28
DDR_A_D24 VSS20 DQ28 DDR_A_D29
57 DQ24 DQ29 58
DDR_A_D25 59 60 Place closely pin JDIMM1.30
DQ25 VSS21 DDR_A_DQS#3
61 VSS22 DQS#3 62
DDR_A_DM3 63 64 DDR_A_DQS3
DM3 DQS3 SM_DRAMRST#
65 VSS23 VSS24 66
69 DQ27 DQ31 70
71 VSS25 VSS26 72 1
C639
@
100P_0402_50V8J
DDR_CKE0_DIMMA DDR_CKE1_DIMMA 2
<8> DDR_CKE0_DIMMA 73 CKE0 CKE1 74 DDR_CKE1_DIMMA <8>
C 75 76 C
VDD1 VDD2
77 NC1 A15 78
<9> DDR_A_BS2 DDR_A_BS2 79 80 DDR_A_MA14
BA2 A14
81 VDD3 VDD4 82
DDR_A_MA12 83 84 DDR_A_MA11 1224 Change C639 to @ for download image fail issue
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 VDD9 VDD10 100
<8> M_CLK_DDR0 M_CLK_DDR0 101 102 M_CLK_DDR1
CK0 CK1 M_CLK_DDR1 <8>
<8> M_CLK_DDR#0 M_CLK_DDR#0 103 104 M_CLK_DDR#1
CK0# CK1# M_CLK_DDR#1 <8>
105 VDD11 VDD12 106
DDR_A_MA10 107 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 <9>
<9> DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS#
BA0 RAS# DDR_A_RAS# <9>
111 VDD13 VDD14 112
<9> DDR_A_WE# DDR_A_WE# 113 114 DDR_CS0_DIMMA#
WE# S0# DDR_CS0_DIMMA# <8>
<9> DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
CAS# ODT0 M_ODT0 <8>
117 VDD15 VDD16 118
DDR_A_MA13 119 120 M_ODT1
A13 ODT1 M_ODT1 <8> +VREF_DQ_DIMMA
<8> DDR_CS1_DIMMA# DDR_CS1_DIMMA# 121 122
S1# NC2
123 VDD17 VDD18 124 Layout Note:
125 NCTEST VREF_CA 126
127 VSS27 VSS28 128 Place near DIMM
0.1U_0402_10V6K
2.2U_0603_6.3V4Z
DDR_A_D32 129 130 DDR_A_D36

DQ32 DQ36
C346
C355
DDR_A_D33 131 132 DDR_A_D37 1 1

DQ33 DQ37
133 VSS29 VSS30 134
DDR_A_DQS#4 135 136 DDR_A_DM4
DDR_A_DQS4 DQS#4 DM4
137 DQS4 VSS31 138
B DDR_A_D38 2 2 B
139 VSS32 DQ38 140
DDR_A_D34 141 142 DDR_A_D39 +1.5V
DDR_A_D35 DQ34 DQ39
143 DQ35 VSS33 144
145 146 DDR_A_D44
VSS34 DQ44
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_A_D40 147 148 DDR_A_D45
DQ40 DQ45
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
DDR_A_D41 149 150 1
DQ41 VSS35
C589
C588
C586
C581
C310
C309
C570
C308
C314
C315
C317
C316
151 152 DDR_A_DQS#5 1 1 1 1 1 1 1 1 1 1 1 1
DDR_A_DM5 VSS36 DQS#5 DDR_A_DQS5 + C569
153 DM5 DQS5 154
155 156 VDDQ(1.5V) = 220U_6.3V_M
DDR_A_D42 VSS37 VSS38 DDR_A_D46 @ @
157 DQ42 DQ46 158
2 2 2 2 2 2 2 2 2 2 2 2 2
OSCON
DDR_A_D43 159 160 DDR_A_D47 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
DQ43 DQ47
161 VSS39 VSS40 162
DDR_A_D48 163 164 DDR_A_D52 6*0603 10uf (PER CONNECTOR)
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDR_A_DQS#6 169 170 DDR_A_DM6 VTT(0.75V) =
DDR_A_DQS6 DQS#6 DM6
171 DQS6 VSS43 172
173 174 DDR_A_D54 3*0805 10uf 4*0402 1uf
DDR_A_D50 VSS44 DQ54 DDR_A_D55
175 DQ50 DQ55 176
DDR_A_D51 177 178 VREF =
DQ51 VSS45 DDR_A_D60 +0.75VS
179 VSS46 DQ60 180
DDR_A_D56 181 182 DDR_A_D61 1*0402 0.1uf 1*0402 2.2uf
DDR_A_D57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDR_A_DQS#7 VDDSPD (3.3V)=
DDR_A_DM7 VSS48 DQS#7 DDR_A_DQS7
187 DM7 DQS7 188
C605
1U_0603_10V4Z
C607
1U_0603_10V4Z
C606
C300
1U_0603_10V4Z
10U_0603_6.3V6M
1U_0603_10V4Z
189 VSS49 VSS50 190 1*0402 0.1uf 1*0402 2.2uf
C301
DDR_A_D58 191 192 DDR_A_D62 1 1 1 1 1
193 DQ59 DQ63 194
1 R570 2 195 VSS51 VSS52 196
10K_0402_5% 197 198 PM_EXTTS#0
SA0 EVENT# PM_EXTTS#0 <8,15> 2 2 2 2 2
+3VS 199 VDDSPD SDA 200 CLK_SMBDATA <15,16>
2.2U_0603_6.3V4Z
0.1U_0402_10V6K
201 SA1 SCL 202 CLK_SMBCLK <15,16>

C608
C617
A 203 204 A
1 1 VTT1 VTT2 +0.75VS
1 10K_0402_5%
R571
205 206 1/76BA1/86W

G1 G2
2 2 FOX_AS0A626-U4RN-7F
ME@
2

DDRIII SO-DIMM A
DDR3 SO-DIMM A H=4mm Reverse type THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
Custom
Rev
1.0
LA7012P
5 4 3 2 1
5 4 3 2 1
+VREF_DQ_DIMMB +1.5V 4BA2/6W +1.5V

<9> DDR_B_DQS#[0..7]
<9> DDR_B_D[0..63]
JDIMM2 +1.5V
+VREF_DQ_DIMMB <9> DDR_B_DM[0..7]
1 VREF_DQ VSS1 2
3 4 DDR_B_D4
VSS2 DQ4 <9> DDR_B_DQS[0..7]
1
DDR_B_D0 5 6 DDR_B_D5
DQ0 DQ5
2.2U_0603_6.3V4Z
0.1U_0402_10V6K
DDR_B_D1 7 8 R341
DQ1 VSS3 DDR_B_DQS#0 <9> DDR_B_MA[0..14] 1K_0402_1%
1 1 9 VSS4 DQS#0 10
DDR_B_DM0 DDR_B_DQS0 +VREF_DQ_DIMMB
11 DM0 DQS0 12
C382
C384
13 14
2
DDR_B_D2 VSS5 VSS6 DDR_B_D6
15 DQ2 DQ6 16
2 2 DDR_B_D3 DDR_B_D7
D 17 DQ3 DQ7 18 D
19 VSS7 VSS8 20
1
DDR_B_D9 DQ8 DQ12 DDR_B_D13
23 DQ9 DQ13 24
25 26 R340
DDR_B_DQS#1 VSS9 VSS10 DDR_B_DM1 1K_0402_1%
27 DQS#1 DM1 28
DDR_B_DQS1 29 30 SM_DRAMRST#
SM_DRAMRST# <8,14>
2
DQS1 RESET#
31 VSS11 VSS12 32
35 DQ11 DQ15 36
37 VSS13 VSS14 38
41 DQ17 DQ21 42 For Arranale only +VREF_DQ_DIMMB
43 VSS15 VSS16 44
DDR_B_DQS#2 45 46 DDR_B_DM2 supply from a external 1.5V voltage divide
DDR_B_DQS2 DQS#2 DM2
47 DQS2 VSS17 48 circuit.
49 50 DDR_B_D22
VSS18 DQ22
DDR_B_D18 51 DQ18 DQ23 52 DDR_B_D23 07/17/2009
DDR_B_D19 53 54
DQ19 VSS19 DDR_B_D28
55 VSS20 DQ28 56
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_B_DQS#3 Place closely pin JDIMM2.30
DDR_B_DM3 VSS22 DQS#3 DDR_B_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66
DDR_B_D26 67 68 DDR_B_D30 SM_DRAMRST#
69 DQ27 DQ31 70
71 VSS25 VSS26 72
1
C640
@
<8> DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB 100P_0402_50V8J
CKE0 CKE1 DDR_CKE3_DIMMB <8> 2
75 VDD1 VDD2 76
77 NC1 A15 78
<9> DDR_B_BS2 DDR_B_BS2 79 80 DDR_B_MA14
C BA2 A14 C
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86 1224 Change C640 to @ for download image fail issue
87 VDD5 VDD6 88
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD9 VDD10 100
<8> M_CLK_DDR2 M_CLK_DDR2 101 102 M_CLK_DDR3
CK0 CK1 M_CLK_DDR3 <8>
<8> M_CLK_DDR#2 M_CLK_DDR#2 103 104 M_CLK_DDR#3
CK0# CK1# M_CLK_DDR#3 <8>
105 VDD11 VDD12 106
DDR_B_MA10 107 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <9>
<9> DDR_B_BS0 DDR_B_BS0 109 110 DDR_B_RAS# Layout Note:
BA0 RAS# DDR_B_RAS# <9>
111 VDD13 VDD14 112
<9> DDR_B_WE# DDR_B_WE# 113 WE# S0# 114 DDR_CS2_DIMMB#
DDR_CS2_DIMMB# <8>
Place near DIMM
<9> DDR_B_CAS# DDR_B_CAS# 115 116 M_ODT2
CAS# ODT0 M_ODT2 <8>
117 VDD15 VDD16 118
DDR_B_MA13 119 120 M_ODT3
A13 ODT1 M_ODT3 <8> +VREF_DQ_DIMMB
<8> DDR_CS3_DIMMB# DDR_CS3_DIMMB# 121 122
S1# NC2
123 VDD17 VDD18 124
125 NCTEST VREF_CA 126
+1.5V
0.1U_0402_10V6K
2.2U_0603_6.3V4Z
127 VSS27 VSS28 128

DDR_B_D32 129 130 DDR_B_D36
DQ32 DQ36
C385
C383
DDR_B_D33 131 132 DDR_B_D37 1 1

DQ33 DQ37
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
133 VSS29 VSS30 134
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
DDR_B_DQS#4 135 136 DDR_B_DM4
DQS#4 DM4
C582
C587
C576
C311
C313
C590
C575
C312
C307
C304
C305
C306
DDR_B_DQS4 137 138 1 1 1 1 1 1 1 1 1 1 1 1
DQS4 VSS31 DDR_B_D38 2 2
139 VSS32 DQ38 140
DDR_B_D34 141 142 DDR_B_D39
DDR_B_D35 DQ34 DQ39 @ @
143 DQ35 VSS33 144
DDR_B_D44 2 2 2 2 2 2 2 2 2 2 2 2
145 VSS34 DQ44 146
DDR_B_D40 147 148 DDR_B_D45
DDR_B_D41 DQ40 DQ45
B 149 DQ41 VSS35 150 B
151 152 DDR_B_DQS#5
153 DM5 DQS5 154 VDDQ(1.5V) =
155 VSS37 VSS38 156
DDR_B_D42 157 158 DDR_B_D46 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
159 DQ43 DQ47 160
161 VSS39 VSS40 162 6*0603 10uf (PER CONNECTOR)
DDR_B_D48 163 164 DDR_B_D52
165 DQ49 DQ53 166 Layout Note:
167 VSS41 VSS42 168 VTT(0.75V) =
DDR_B_DQS#6 169 170 DDR_B_DM6 Place near DIMM
DDR_B_DQS6 DQS#6 DM6
171 DQS6 VSS43 172 3*0805 10uf 4*0402 1uf
173 174 DDR_B_D54
DDR_B_D50 VSS44 DQ54 DDR_B_D55
175 DQ50 DQ55 176
DDR_B_D51 177 178
DQ51 VSS45 DDR_B_D60 +0.75VS
179 VSS46 DQ60 180 1*0402 0.1uf 1*0402 2.2uf
DDR_B_D56 181 182 DDR_B_D61
DDR_B_D57 DQ56 DQ61
183 DQ57 VSS47 184 VDDSPD (3.3V)=
185 186 DDR_B_DQS#7
187 DM7 DQS7 188 1*0402 0.1uf 1*0402 2.2uf
10U_0603_6.3V6M
1U_0603_10V4Z
1U_0603_10V4Z
1U_0603_10V4Z
189 VSS49 VSS50 190
C596
C595
C299
C598
DDR_B_D58 191 192 DDR_B_D62 1 1 1 1
193 DQ59 DQ63 194
195 VSS51 VSS52 196
1 R572 2 197 SA0 EVENT# 198 PM_EXTTS#0
PM_EXTTS#0 <8,14>
10K_0402_5% 2 2 2 2
199 VDDSPD SDA 200 CLK_SMBDATA <14,16>
+3VS 1 2 201 SA1 SCL 202 CLK_SMBCLK <14,16>
2.2U_0603_6.3V4Z
0.1U_0402_10V6K
R573 10K_0402_5% 203 204 +0.75VS

VTT1 VTT2 1/76BA1/86W
C618
C616
1 1
205 G1 G2 206
FOX_AS0A626-U8RN-7F
2 2 ME@
A A
DDR3 SO-DIMM A H=8mm Reverse type

DDRIII SO-DIMM B
Custom 1.0
LA7012P
5 4 3 2 1
5 4 3 2 1
+3VSM_CK505 +3VS
FSC FSB FSA CPU SRC PCI REF DOT_96 USB
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz +3VS R668 1 2 0_0805_5%
@
1 1 1 1 1 1 1
R669 1 2 0_0402_5%
0 0 0 266 100 33.3 14.318 96.0 48.0 C811 C812 C813 C814 C815 C816 C817
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R670 R671
2 2 2 2 2 2 2 2.2K_0402_5% 2.2K_0402_5%
0 0 1 133 100 33.3 14.318 96.0 48.0 2N7002DW-T/R7_SOT363-6
<19,23> ICH_SMBDATA 6 1 CLK_SMBDATA
+VDD_CK505
0 1 0 200 100 33.3 14.318 96.0 48.0 Q1A
+1.05VS R673 1 2 0_0805_5%
2
D D
1 1 1 1 1 1 1 +3VS
0 1 1 166 100 33.3 14.318 96.0 48.0
5
C818 C819 C820 C821 C822 C823 C824
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z Q1B
2 2 2 2 2 2 2 CLK_SMBCLK
1 0 0 333 100 33.3 14.318 96.0 48.0 <19,23> ICH_SMBCLK 3 4
2N7002DW-T/R7_SOT363-6
1 0 1 100 100 33.3 14.318 96.0 48.0 SA000020K00 (Silego : SLG8SP556VTR )
1 1 0 400 100 33.3 14.318 96.0 48.0 SA000020H00 (ICS : ICS9LPRS387AKLFT) R674 1
@
2 0_0402_5%
+3VSM_CK505 U30
1 1 1 Reserved 9 CLK_SMBDATA
SDA CLK_SMBDATA <14,15>
55 VDD_SRC
10 CLK_SMBCLK
SCL CLK_SMBCLK <14,15>
6 VDD_REF
+1.05VS 12 71 CLK_CPU_BCLK
VDD_PCI CPU_0 CLK_CPU_BCLK <4>
72 70 CLK_CPU_BCLK# CPU
VDD_CPU CPU_0# CLK_CPU_BCLK# <4>
2
@ 19 68 CLK_MCH_BCLK
VDD_48 CPU_1 CLK_MCH_BCLK <7>
R675
56_0402_5% 27 67 CLK_MCH_BCLK# NB
+VDD_CK505 VDD_PLL3 CPU_1# CLK_MCH_BCLK# <7>
1
FSA R680 2 1 2.2K_0402_5% R676 1 2 1K_0402_5% MCH_CLKSEL0 <8>

66 24 CLK_MCH_DREFCLK
VDD_CPU_IO SRC_0/DOT_96 CLK_MCH_DREFCLK <8>
R678 1 2 0_0402_5%
<5> CPU_BSEL0
31 25 CLK_MCH_DREFCLK# NB(96MHz)
VDD_PLL3_IO SRC_0#/DOT_96# CLK_MCH_DREFCLK# <8>
1
C @ 62 C
R679 VDD_SRC_IO MCH_SSCDREFCLK
LCDCLK/27M 28 MCH_SSCDREFCLK <8>
1K_0402_5% 52 VDD_SRC_IO MCH_SSCDREFCLK# NB_SSC(100MHz)
29 MCH_SSCDREFCLK# <8> SRC PORT LIST
2
LCDCLK#/27M_SS
23 VDD_IO
38 VDD_SRC_IO SRC_2 32 CLK_MCH_3GPLL
CLK_MCH_3GPLL <8> PORT DEVICE
+1.05VS 33 CLK_MCH_3GPLL# MCH_PEGPLL
SRC_2# CLK_MCH_3GPLL# <8>
R685 1 2 33_0402_5% FSA 20
SRC0 MCH_DREFCLK
USB_0/FS_A
1
<19> CLK_48M_ICH
@ FSB 2
SRC_3 35
SRC2 MCH_3GPLL
R686 FS_B/TEST_MODE
1K_0402_5% R687 1 2 33_0402_5% FSC 7
SRC_3# 36
SRC3
<19> CLK_14M_ICH REF_0/FS_C/TEST_
SRC4
2
FSB R688 1 2 1K_0402_5% 8 39

MCH_CLKSEL1 <8> REF_1 SRC_4
<5> CPU_BSEL1
R690 1 2 0_0402_5% 40
SRC6
CK_PWRGD SRC_4#
1 CKPWRGD/PD# SRC7 PCIE_WLAN1
1
<19> CK_PWRGD
@
R691
11 NC SRC_6 57
SRC8
0_0402_5%
SRC_6# 56
SRC9 PCIE_LAN
2
H_STP_CPU#
<19> H_STP_CPU#
53 CPU_STOP#
61 CLK_PCIE_WLAN1
CLK_PCIE_WLAN1 <23>
SRC10 PCIE_ICH
H_STP_PCI# SRC_7
<19> H_STP_PCI#
54 PCI_STOP#
60 CLK_PCIE_WLAN1#
CLK_PCIE_WLAN1# <23>
WLAN SRC11 PCIE_SATA
+1.05VS SRC_7#
CLK_XTAL_IN 5 XTAL_IN
SRC_8/CPU_ITP 64
1
B CLK_XTAL_OUT 4 +3VS B
@ XTAL_OUT
SRC_8#/CPU_ITP# 63
R692 SATA_CLKREQ# R693 2 1 10K_0402_5%
1K_0402_5%
13 44 CLK_PCIE_LAN WLAN_CLKREQ1# R695 2 1 10K_0402_5%
CLK_PCIE_LAN <24>
2
FSC R696 1 PCI_1 SRC_9

2 10K_0402_5% R697 1 2 1K_0402_5% MCH_CLKREQ# R698 2 1 10K_0402_5%
MCH_CLKSEL2 <8>
T5 R700 1 2 @ 33_0402_5% PCI2_TME 14 45 CLK_PCIE_LAN# LAN CLKREQ_LAN# R701 2 1 10K_0402_5%
PCI_2 SRC_9# CLK_PCIE_LAN# <24>
R699 1 2 0_0402_5%
<5> CPU_BSEL2
15 PCI_3
1
50 CLK_PCIE_ICH
SRC_10 CLK_PCIE_ICH <19>
@ R705 1 33_0402_5% PCI4_SEL
R704
<27> CLK_PCI_LPC 2 16 PCI_4/SEL_LCDCL
51 CLK_PCIE_ICH# ICH-DMIPCIE REQ PORT LIST
SRC_10# CLK_PCIE_ICH# <19>
0_0402_5% R706 1 2 33_0402_5% ITP_EN 17
<17> CLK_PCI_ICH PCIF_5/ITP_EN
PORT DEVICE
2
48 CLK_PCIE_SATA
SRC_11 CLK_PCIE_SATA <18>
ICH-SATA
18 VSS_PCI SRC_11# 47 CLK_PCIE_SATA#
CLK_PCIE_SATA# <18> REQ_3#
3 VSS_REF REQ_4#
+3VS +3VS +3VS 22 VSS_48 CLKREQ_3# 37
REQ_6#
26 41
VSS_IO CLKREQ_4# REQ_7# PCIE_WLAN1
1
@ @
PVT EMI Change Y4 from SJ114P3M720 to SJ100002600.
R707 R708 R709
Close to CLK_PCI_LPC
69 VSS_CPU CLKREQ_6# 58
REQ_9# PCIE_LAN
10K_0402_5% 10K_0402_5% 10K_0402_5% CLK_XTAL_IN WLAN_CLKREQ1#
+3VS C825 27P_0402_50V8J
30 VSS_PLL3 CLKREQ_7# 65 WLAN_CLKREQ1# <23> REQ_10#
2
ITP_EN PCI4_SEL PCI2_TME CLKREQ_LAN#

Y4
34 VSS_SRC CLKREQ_9# 43 CLKREQ_LAN# <24> REQ_11# PCIE_SATA
1
14.31818MHZ X5H01431AFG1H-X
@ 1
59 VSS_SRC SLKREQ_10# 49
REQ_A# MCH_3GPLL
2
A R710 R711 R712 CLK_XTAL_OUT 42 46 SATA_CLKREQ# A

VSS_SRC CLKREQ_11# SATA_CLKREQ# <19>
10K_0402_5% 10K_0402_5% 10K_0402_5% C657 C828 27P_0402_50V8J
470P_0402_50V7K 73 21 MCH_CLKREQ#
MCH_CLKREQ# <8>
2
2 VSS USB_1/CLKREQ_A#
Routing the trace at least 10mil
SLG8SP556VTR_QFN72_10X10
For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#

For PCI4_SEL, 0 = Pin24/25 : DOT96 / DOT96# Clock Generator CK505
Pin28/29 : LCDCLK / LCDCLK# THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1 = Pin24/25 : SRC_0 / SRC_0# Custom 1.0
LA7012P
Pin28/29 : 27M/27M_SS Date: Friday, December 24, 2010 Sheet 16 of 41
5 4 3 2 1
5 4 3 2 1
09/16 Add C858 For ESD

Place closely pin C14
+3VS
PLT_RST#
1 2 PCI_DEVSEL#
R788 8.2K_0402_5% 1
1 2 PCI_STOP#
R789 8.2K_0402_5% C858
1 2 PCI_TRDY# U9B 0.1U_0402_16V4Z
D R790 8.2K_0402_5% PCI_REQ0# 2 D
D11 AD0 REQ0# F1
1 2 PCI_FRAME# C8 G4 PCI_GNT0#
R791 8.2K_0402_5% AD1 GNT0# PCI_REQ1#
1 2 PCI_PLOCK#
D9
E12
AD2 PCI REQ1#/GPIO50 B6
A7 T107
R792 8.2K_0402_5% AD3 GNT1#/GPIO51 PCI_REQ2#
E9 AD4 REQ2#/GPIO52 F13
1 2 PCI_IRDY# C9 F12 T108
R793 8.2K_0402_5% AD5 GNT2#/GPIO53 PCI_REQ3#
E10 AD6 REQ3#/GPIO54 E6
PCI_SERR# PCI_GNT3#
R794
1 2
8.2K_0402_5%
B7
C7
AD7 GNT3#/GPIO55 F6
Place closely pin D4
PCI_PERR# AD8
1 2 C5 AD9 C/BE0# D8
R795 8.2K_0402_5% G11 B4 CLK_PCI_ICH
AD10 C/BE1#
F8 AD11 C/BE2# D6
2
F11 AD12 C/BE3# A5
E7 AD13
+3VS A3 D3 PCI_IRDY# R811
AD14 IRDY# 0_0402_5%
D2 AD15 PAR E3
1 2 PCI_PIRQA# F10 R1 PCI_RST#
1
R796 8.2K_0402_5% AD16 PCIRST# PCI_DEVSEL#
D5 AD17 DEVSEL# C6
1 2 PCI_PIRQB# D10 E4 PCI_PERR# 1
R797 8.2K_0402_5% AD18 PERR# PCI_PLOCK#
B3 AD19 PLOCK# C2
1 2 PCI_PIRQC# F7 J4 PCI_SERR# C869
R798 8.2K_0402_5% AD20 SERR# PCI_STOP# 18P_0402_50V8J
C3 AD21 STOP# A4
PCI_PIRQD# PCI_TRDY# 2
1 2 F3 AD22 TRDY# F5
R799 8.2K_0402_5% F4 D7 PCI_FRAME#
PCI_PIRQE# AD23 FRAME#
1 2 C1 AD24
R800 8.2K_0402_5% G7 C14 PLT_RST#
PCI_PIRQF# AD25 PLTRST# CLK_PCI_ICH
1 2 H7 AD26 PCICLK D4 CLK_PCI_ICH <16>
R801 8.2K_0402_5% D1 R2 PCI_PME#
AD27 PME# PCI_PME# <27>
1 2 PCI_PIRQG# G5
R802 8.2K_0402_5% AD28
H6 AD29
1 2 PCI_PIRQH# G1 1 2
R803 8.2K_0402_5% AD30 R804 @ 10K_0402_5%
+3VALW PCI_RST#
H3 AD31 PCI_RST# <27>
C 1 2 PCI_REQ0# C
1
R805 8.2K_0402_5%
PCI_REQ1#
R806
1 2
8.2K_0402_5% PCI_PIRQA# J5
Interrupt I/F H4 PCI_PIRQE# R813
PCI_REQ2# PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF# 100K_0402_5%
1 2 E1 PIRQB# PIRQF#/GPIO3 K6
R807 8.2K_0402_5% PCI_PIRQC# J6 F2 PCI_PIRQG#
2
PCI_REQ3# PCI_PIRQD# PIRQC# PIRQG#/GPIO4 PCI_PIRQH#
1 2 C4 PIRQD# PIRQH#/GPIO5 G2
R808 8.2K_0402_5%
ICH9-M ES_FCBGA676
PLT_RST#
PLT_RST# <8,23,24>
1
R814
100K_0402_5%
2
PCI_GNT0# SB_SPI_CS#1
<19> SB_SPI_CS#1
1
SPI@ @
R809 R810
1K_0402_5% 1K_0402_5%
2
1 2 PCI_GNT3#
B R812 @ 1K_0402_5% B
Boot BIOS Strap

PCI_GNT#0 SPI_CS#1 Boot BIOS Loaction
0 1 SPI
A16 Swap Override Strap
Low= A16 swap override Enable 1 0 PCI
PCI_GNT#3 High= Default*
1 1 LPC*
A A

ICH9M(1/4)-PCI
Custom 1.0
LA7012P
5 4 3 2 1
5 4 3 2 1
+3VS
R933
GATEA20 2 1
+RTCVCC 10K_0402_5%
D
Change Y2 from SJ100001U00 to SJ100003300. D
R934 330K_0402_1% 1 2 ICH_RTCX1 R935
1 2 LAN100_SLP C870 15P_0402_50V8J KB_RST# 2 1
Y5
1
R936 1M_0402_5% 10K_0402_5%
1 2 SM_INTRUDER# 2 NC OSC 1
R819 +1.05VS
R820 330K_0402_1% 32.768KHZ_12.5PF_Q13MC14610002 3 4 10M_0402_5%
NC OSC
1 2 ICH_INTVRMEN LPC_AD[0..3] <27>
R821 @
2
U9A H_DPRSTP# 2 1
C23 K5 LPC_AD0
ICH_RTCX2 RTCX1 FWH0/LAD0 LPC_AD1 56_0402_5%
1 2 C24 RTCX2 FWH1/LAD1 K4
C871 15P_0402_50V8J L6 LPC_AD2 R824 @
ICH_RTCRST# FWH2/LAD2 LPC_AD3 H_DPSLP#
+RTCVCC 1 2 A25 RTCRST# FWH3/LAD3 K2 2 1
+RTCVCC R822 20K_0402_5% +RTCVCC 1 2 ICH_SRTCRST# F20
R180 20K_0402_5% SM_INTRUDER# SRTCRST# LPC_FRAME# 56_0402_5%
close to RAM door C22 INTRUDER# FWH4/LFRAME# K3 LPC_FRAME# <27>
RTC
LPC
CLRP1
@ 1 2 ICH_INTVRMEN B22 J3
R823 +RTCBATT R365 @ LAN100_SLP INTVRMEN LDRQ0# +1.05VS
2 1 A22 LAN100_SLP LDRQ1#/GPIO23 J1
1 2 10K_0603_5%
E25 N7 GATEA20
2MM GLAN_CLK A20GATE GATEA20 <27>
1
2 100_0603_1% 1 2 AJ27 H_A20M#
A20M# H_A20M# <4>
C872 1 2 C248 1U_0603_10V6K C13
C873 1U_0603_10V4Z LAN_RSTSYNC
DPRSTP# AJ25 H_DPRSTP_R# R825 2 1 0_0402_5% H_DPRSTP#
H_DPRSTP# <5,8,40>
R826
0.1U_0402_16V4Z +3VALW F14 AE23 H_DPSLP# 56_0402_5%
1 LAN_RXD0 DPSLP# H_DPSLP# <5>
G13
2
LAN_RXD1 H_FERR#_S R827 1
D14 LAN_RXD2 FERR# AJ26 2 56_0402_5% H_FERR# <4>
LAN / GLAN
9/14 Add R937 by Danson.
R937 D13 AD22 H_PWRGOOD
LAN_TXD_0 CPUPWRGD H_PWRGOOD <5>
10K_0402_5% D12 LAN_TXD_1
E13 AF25 H_IGNNE#
+1.5VS LAN_TXD_2 IGNNE# H_IGNNE# <4>
2
C B10 AE22 H_INIT# C
GPIO56 INIT# H_INIT# <4> +1.05VS
AG25 H_INTR
CPU
INTR H_INTR <4>
R828 1 2GLAN_COMP B28 L3 KB_RST# R833 need to place within 2" of ICH9M
GLAN_COMPI RCIN# KB_RST# <27>
24.9_0402_1% B27 GLAN_COMPO
1
AF23 H_NMI R830 must be place within 2" of R833 w/o stub.
NMI H_NMI <4>
<26> HDA_BITCLK_CODEC 1 R829 2 33_0402_5% HDA_BITCLK_ICH AF6
HDA_BIT_CLK SMI# AF24 H_SMI#
H_SMI# <4>
<26> HDA_SYNC_CODEC 1 R831 2 33_0402_5% HDA_SYNC_R AH4 HDA_SYNC
R830
AH27 H_STPCLK# 56_0402_5%
STPCLK# H_STPCLK# <4>
<26> HDA_RST_CODEC# 1 R832 2 33_0402_5% HDA_RST_R# AE7
2
HDA_RST# THRMTRIP_ICH# R833 1 H_THERMTRIP#
THRMTRIP# AG26 2 54.9_0402_1% H_THERMTRIP# <4,8>
<26> HDA_SDIN0 AF4 HDA_SDIN0
AG4 HDA_SDIN1 TP12 AG27
AH3 HDA_SDIN2
AE5
IHDA
HDA_SDIN3
HDA_SDOUT_R SATA4RXN AH11 Place closely pin AG26
<26> HDA_SDOUT_CODEC 1 2 AG5 HDA_SDOUT SATA4RXP AJ11
R834 33_0402_5% AG12
T111 SATA4TXN THRMTRIP_ICH#
AG7 HDA_DOCK_EN#/GPIO33 SATA4TXP AF12
+3VS 1 2 AE8 HDA_DOCK_RST#/GPIO34
D30 R835 10K_0402_5%
HDD_LED# 2 @ 1 SATA_LED# AG8 1
<32> HDD_LED# RB751V_SOD323 SATALED# R836 1
SATA5RXN AH9 2 @ 1K_0402_5%
1 2 <28> SATA_DTX_C_IRX_N0 AJ16 AJ9 R837 1 2 @ 1K_0402_5% C641
R92 0_0402_5% SATA0RXN SATA5RXP 100P_0402_50V8J
<28> SATA_DTX_C_IRX_P0 AH16 SATA0RXP SATA5TXN AE10
2
10/01 Danson
HDD <28> SATA_ITX_C_DRX_N0 AF17
AG17
SATA0TXN SATA5TXP AF10
<28> SATA_ITX_C_DRX_P0 SATA0TXP
AH18 CLK_PCIE_SATA#
SATA_CLKN CLK_PCIE_SATA# <16>
SATA
Change D30 from SC1H751H010 to SCS00000Z00 . <32> SATA_DTX_C_IRX_N1 AH13 AJ18 CLK_PCIE_SATA
SATA1RXN SATA_CLKP CLK_PCIE_SATA <16>
<32> SATA_DTX_C_IRX_P1 AJ13 SATA1RXP SATARBIAS# AJ7
Add R92 from SATA_LED# to HDD_LED#. AG14 AH7 SATARBIAS R838 1 2 24.9_0402_1%
<32> SATA_ITX_C_DRX_N1 SATA1TXN SATARBIAS
ODD <32> SATA_ITX_C_DRX_P1 AF14 SATA1TXP 10mils width less than 500mils
B B
ICH9-M ES_FCBGA676
Need check
+3VS
SATA PORT LIST
XOR Chain Entrance Strap
PORT DEVICE
2
R839
ICH_TP3 HDA_SDOUT Description
1K_0402_5% 0 0 RSVD 0 HDD
@
0 1 Enter XOR Chain 1 ODD
1
HDA_SDOUT_R
1 0 Normal Operation 4
1 1 Set PCIE port config bit 1 5
Flash Descriptor Security Override Strap

Low= Descriptor Security override
A GPIO33 High= Default* (Internal pull-up) A

ICH9M(2/4)-LAN,ATA,LPC,RTC
Custom 1.0
LA7012P
5 4 3 2 1
5 4 3 2 1
+3VS
R840 1 SERIRQ
09/10 Add for Project ID Place closely pin B2 Place closely pin AC1
2 10K_0402_5%
R841 1 2 8.2K_0402_5% PCI_CLKRUN# CLK_48M_ICH CLK_14M_ICH

10K_0402_5% 20@
R842 1 2 @ 10K_0402_5% GPIO38 2 1 R943 +3VS
1
+3VALW
R843 1 2 8.2K_0402_5% EC_THERM# 10K_0402_5% 10@ R857
+3VS PROJECT_ID1 2 1 R1150 R850 10_0402_5%
+3VALW 22_0402_5% @
1
@
2
2
R848 1 2 10K_0402_5% OCP# 10K_0402_5% 20@
R844 R845 2 1 R1159 1 1
+3VS
1
2.2K_0402_5% 2.2K_0402_5% R846 C878
U9C 8.2K_0402_5% 10K_0402_5% 10@ C879 10P_0402_50V8J
2
D R847 D
R851 1 2 @ 8.2K_0402_5% PM_BMBUSY# R849 <16,23> ICH_SMBCLK G16 AH23 PROJECT_ID2 2 1 R1052 10P_0402_50V8J @
1
10K_0402_5% 10K_0402_5% SMBCLK SATA0GP/GPIO21 2 @ 2
R858 1 2 @ 10K_0402_5% GPIO39
<16,23> ICH_SMBDATA
LINKALERT#
A13
SMBDATA SMB SATA1GP/GPIO19
AF19
PROJECT_ID1
SATA
GPIO
E17 AE21
2
ME__EC_CLK1 LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36 PROJECT_ID2
C17 AD20
R852 1 SMLINK0 SATA5GP/GPIO37
2 10K_0402_5% GPIO48 ME__EC_DATA1 B18
SMLINK1 CLK_14M_ICH
H1 CLK_14M_ICH <16>
+3VS ICH_RI# CLK14 CLK_48M_ICH +3VALW
+3VALW
F19
RI# clocks CLK48
AF3 CLK_48M_ICH <16>
R4 P1 ICH_SUSCLK T95
SUS_STAT#/LPCPD# SUSCLK
1
R856 1 2 10K_0402_5% LINKALERT# XDP_DBRESET# G19 10/15 Change C880 from 100P to 1000P for noise.
<4> XDP_DBRESET#
1
SYS_RESET# SLP_S3# @
C16 SLP_S3# <27>
R861 1 CL_RST# PM_BMBUSY# SLP_S3# SLP_S4#
2 @ 10K_0402_5% @ @
<8> PM_BMBUSY# M6 E16 SLP_S4# <27>
R854
R853 R859 PMSYNC#/GPIO0 SLP_S4# SLP_S5# 10K_0402_5% M_PWROK
G17
SYS / GPIO
SLP_S5# SLP_S5# <27>
R864 1 2 10K_0402_5% XDP_DBRESET# 10K_0402_5% 10K_0402_5% 1 2 LID_OUT# A17
<27> EC_LID_OUT#
2
R855 0_0402_5% SMBALERT#/GPIO11 S4_STATE#
C10 1
2
R866 1 ICH_RI# H_STP_PCI# S4_STATE#/GPIO26 M_PWROK
2 10K_0402_5% <16> H_STP_PCI# A14 R860 1 2 @ 100_0402_5%
R862 R_STP_CPU# STP_PCI# ICH_POK
<16> H_STP_CPU# 1 2 0_0402_5% E19 G20 ICH_POK <8,27>
C880
R867 1 STP_CPU# PWROK
2 1K_0402_5% ICH_PCIE_WAKE# 1 2 R863 1000P_0402_50V7K
PCI_CLKRUN# L4 M2 R865 1 2 499_0402_1% DPRSLPVR 10K_0402_5% 2
Power MGT
CLKRUN# DPRSLPVR/GPIO16 DPRSLPVR <8,40>
R868 1 2 8.2K_0402_5% ICH_LOW_BAT#
ICH_PCIE_WAKE# E20 B13 ICH_LOW_BAT#
<23,24> ICH_PCIE_WAKE# WAKE# BATLOW#
R870 1 2 10K_0402_5% LID_OUT# SERIRQ M5
<27> SERIRQ SERIRQ
EC_THERM# AJ23 R3 PBTN_OUT#
<27> EC_THERM# THRM# PWRBTN# PBTN_OUT# <27>
R872 1 2 10K_0402_5% WOL_EN
VGATE R869 1 2 0_0402_5% VRMPWRGD D21 D20
R915 1 GPIO14 VRMPWRGD LAN_RST#
2 10K_0402_5%
Place closely pin G19 T96 SST_CTL A20 D22 EC_RSMRST#R EC_RSMRST#R R871 1 2 10K_0402_5%
TP11 RSMRST#
@ R927 OCP# AG19 R5 CK_PWRGD_R R873 1 2 0_0402_5% CK_PWRGD
+3VS GPIO1 CK_PWRGD CK_PWRGD <16>
2 1 GPIO6 AH21
<27,32> ODD_DA# GPIO6
XDP_DBRESET# 0_0402_5% GPIO7 AG21 R6 M_PWROK
GPIO7 CLPWROK M_PWROK <8>
R916 1 2 10K_0402_5% GPIO6 EC_SMI# A21 R874 1 2 0_0402_5% R875 1 2 3.24K_0402_1% +3VS
<27> EC_SMI# GPIO8 VGATE <8,40>
1 EC_SCI# C12 B16 T97 1
<27> EC_SCI#
1
R876 1 GPIO7 GPIO13 GPIO12 SLP_M#
2 10K_0402_5% C21
C833 GPIO17 GPIO13 C881 R877
AE18 F24 CL_CLK0 <8>
R878 1 GPIO13 GPIO18 GPIO17 CL_CLK0
2 10K_0402_5% 0.1U_0402_16V4Z K1 B19 0.1U_0402_16V4Z 453_0402_1%
GPIO
Controller Link
2 GPIO20 GPIO18 CL_CLK1 2
AF8
R879 1 GPIO20
C 2 @ 10K_0402_5% GPIO17 GPIO22 AJ22 F22 C
2
SCLOCK/GPIO22 CL_DATA0 CL_DATA0 <8>
A9 C19
R880 1 GPIO27 CL_DATA1
2 @ 10K_0402_5% GPIO18 09/16 Add C833 For ESD T98 D19
SATA_CLKREQ# GPIO28 CL_VREF0_ICH
<16> SATA_CLKREQ# L1 C25
R882 1 GPIO20 GPIO38 SATACLKREQ#/GPIO35 CL_VREF0 CL_VREF1_ICH
2 10K_0402_5% AE19 A19 R881 1 @ 2 3.24K_0402_1% +3VALW
GPIO39 SLOAD/GPIO38 CL_VREF1
AG22 1
1
R883 1 GPIO22 GPIO48 SDATAOUT0/GPIO39 CL_RST#
2 10K_0402_5% AF21 F21 CL_RST# <8>
GPIO49 SDATAOUT1/GPIO48 CL_RST0# C882 @ R885
Place closely pin D21 <32> ODD_EN
GPIO57
AH24
GPIO49 CL_RST1#
D18
@ 0.1U_0402_16V4Z 453_0402_1%
A8
GPIO57/CLGPIO5 D31 RB751V_SOD323 2
A16
+3VS SB_SPKR MEM_LED/GPIO24
M7 C18 2 @ 1 ACIN
2
<26> SB_SPKR SPKR GPIO10/SUS_PWR_ACK ACIN <27,36>
VRMPWRGD MCH_ICH_SYNC# AJ24 C11 GPIO14
MISC
<8> MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT
R888 1 2 @ 10K_0402_5% SB_SPKR ICH_RSVD B21 C20 +3VALW 2 1 2 1
T99 TP3 WOL_EN/GPIO9 R886 R887 @ 0_0402_5%
1 AH20
T100 TP8 WOL_EN @ 10K_0402_5%
AJ20
R889 1 TP9
2 @ 100K_0402_5% GPIO57 C860 T101 AJ21
TP10
1000P_0402_50V7K
2
R890 1 2 @ 100K_0402_5% DPRSLPVR ICH9-M ES_FCBGA676
RSMRST circuit
R891 1 2 @ 1K_0402_5% ICH_RSVD 10/01 Change Q8 from SB000009S80 to SB000006780
10/12 Add C833 For Noise
Change D31 from SC1H751H010 to SCS00000Z00 .
<35,37> SPOK 2 R893 @1 2 R892 @1
0_0402_5% 0_0402_5%
+3VALW
Change Lan from Port6 to Port 1 for power consumption.
RP1 U9D EC_RSMRST#R 1 Q8 3
C
EC_RSMRST# <27>
5 4 USB_OC#6 PCIE_IRX_PTX_N1 N29 V27 DMI_RXN0
E
<24> PCIE_IRX_PTX_N1 PERN1 DMI0RXN DMI_RXN0 <8>
6 3 USB_OC#1 PCIE_IRX_PTX_P1 N28 V26 DMI_RXP0 DMI_RXP0 <8> BAV99DW-7_SOT363 MMBT3906_SOT23-3
<24> PCIE_IRX_PTX_P1 PERP1 DMI0RXP
7 2 USB_OC#2 LAN C891 0.1U_0402_10V7K PCIE_ITX_PRX_N1 P27 U29 DMI_TXN0 1 2
B
<24> PCIE_ITX_C_PRX_N1 DMI_TXN0 <8> +3VALW
1 2
USB_OC#4 C892 0.1U_0402_10V7K PCIE_ITX_PRX_P1 PETN1 DMI0TXN DMI_TXP0 R894 4.7K_0402_5%
8 1 P26 U28
Direct Media Interface

<24> PCIE_ITX_C_PRX_P1 PETP1 DMI0TXP DMI_TXP0 <8>
2
10K_1206_8P4R_5% L29 Y27 DMI_RXN1 DMI_RXN1 <8> @ D32B
PERN2 DMI1RXN DMI_RXP1 R895
L28 Y26 DMI_RXP1 <8>
RP2 PERP2 DMI1RXP DMI_TXN1 2.2K_0402_5% D32A
M27 W29 DMI_TXN1 <8>
USB_OC#5 PETN2 DMI1TXN DMI_TXP1 BAV99DW-7_SOT363
5 4 M26 W28 DMI_TXP1 <8>
1
USB_OC#7 PETP2 DMI1TXP R896
6 3
6
PCI - Express
7 2 USB_OC#9 PCIE_RXN3 J29 AB27 DMI_RXN2 DMI_RXN2 <8> 1 2
<23> PCIE_RXN3 PERN3 DMI2RXN
8 1 USB_OC#0 PCIE_RXP3 J28 AB26 DMI_RXP2 DMI_RXP2 <8>
B <23> PCIE_RXP3 PERP3 DMI2RXP B
WLAN <23> PCIE_TXN3 C884 0.1U_0402_10V7K PCIE_C_TXN3 K27 AA29 DMI_TXN2 DMI_TXN2 <8> 4.7K_0402_5%
10K_1206_8P4R_5% C885 0.1U_0402_10V7K PCIE_C_TXP3 PETN3 DMI2TXN DMI_TXP2
<23> PCIE_TXP3 K26 AA28 DMI_TXP2 <8>
PETP3 DMI2TXP
RP3 G29 AD27 DMI_RXN3
5
6
4
3
USB_OC#8
USB_OC#3
+3VS G28
H27
PERN4
PERP4
DMI3RXN
DMI3RXP
AD26
AC29
DMI_RXP3
DMI_TXN3
DMI_RXN3
DMI_RXP3
<8>
<8> PCIE PORT LIST USB PORT LIST
PETN4 DMI3TXN DMI_TXN3 <8>
7 2 USB_OC#10 H26 AC28 DMI_TXP3 DMI_TXP3 <8>
PETP4 DMI3TXP
2
USB_OC#11
8 1
@ E29 T26 CLK_PCIE_ICH# PORT DEVICE PORT DEVICE
PERN5 DMI_CLKN CLK_PCIE_ICH# <16>
10K_1206_8P4R_5% R898 E28 T25 CLK_PCIE_ICH
PERP5 DMI_CLKP CLK_PCIE_ICH <16>
330_0402_5% Within 500 mils
F27
F26
PETN5
AF29
1 LAN 0 RIGHT SIDE
1
R899 1 PETP5 DMI_ZCOMP

2 @ 0_0402_5% VRMPWRGD AF28 DMI_IRCOMP R897 1 2 24.9_0402_1% +1.5VS 2 1 LEFT SIDE
DMI_IRCOMP
C29
PERN6/GLAN_RXN
1
D USB20_N0
2 @
C28
D27
PERP6/GLAN_RXP USBP0N
AC5
AC4 USB20_P0
USB20_N0 <29>
RIGHT USB
3 WLAN 2 CMOS
<40> CLK_ENABLE# PETN6/GLAN_TXN USBP0P USB20_P0 <29>
G Q9 USB20_N1
S RHU002N06_SOT323
D26
PETP6/GLAN_TXP USBP1N
AD3
AD2 USB20_P1
USB20_N1 <29>
LEFT USB
4 3
3
USBP1P USB20_P1 <29>

ICH_SPI_CLK_1 R919 1 SPI@ 2 33_0402_5% ICH_SPI_CLK USB20_N2
ICH_SPI_CS0# R920 2 SPI@ 1 0_0402_5% ICH_SPI_CS0#_R
D23
D24
SPI_CLK USBP2N
AC1
AC2 USB20_P2
USB20_N2 <22>
CMOS
5 4 CARD READER
SPI_CS0# USBP2P USB20_P2 <22>
SB_SPI_CS#1
<17> SB_SPI_CS#1 F23
SPI_CS1#GPIO58/CLGPIO6 USBP3N
AA5
AA4
6 5 WIRELESS
ICH_SPI_MOSI_1 R422 1 SPI@ USBP3P
2 0_0402_5% ICH_SPI_MOSI D25 SPI AB2 USB20_N4
USB20_N4 <30> 6 BT
ICH_SPI_MISO SPI_MOSI USBP4N USB20_P4
E23
SPI_MISO USBP4P
AB3 USB20_P4 <30>Card Reader
USB20_N5
USB_OC#0 USBP5N
AA1
USB20_P5
USB20_N5 <23> 7 LEFT SIDE
<29> USB_OC#0 N4
OC0#/GPIO59 USBP5P
AA2 USB20_P5 <23> WLAN
USB_OC#1 USB20_N6
<29> USB_OC#1_7
USB_OC#2
N5
OC1#/GPIO40 USBP6N
W5
USB20_P6
USB20_N6 <30> 8
N6
OC2#/GPIO41 USB USBP6P
W4 USB20_P6 <30> BT
USB_OC#3 USB20_N7
USB_OC#4
P6
OC3#/GPIO42 USBP7N
Y3
USB20_P7
USB20_N7 <29> 9
M1
OC4#/GPIO43 USBP7P
Y2 USB20_P7 <29> LEFT USB
USB_OC#5
USB_OC#6
N2
M4
OC5#/GPIO29 USBP8N
W1
W2
10
USB_OC#7 OC6#/GPIO30 USBP8P
+3VS SPI Flash (16Mb*1) USB_OC#8
M3
N3
OC7#/GPIO31 USBP9N
V2
V3
11
USB_OC#9 OC8#/GPIO44 USBP9P
20mils USB_OC#10
N1
P5
OC9#/GPIO45
OC10#/GPIO46
USBP10N
USBP10P
U5
U4
20mils USB_OC#11 P3 U1
A SPI@
C1171
1
8
U33 SPI@
4
FOR SB 16M SPI ROM R900 1 2 22.6_0402_1% USBRBIAS AG2
OC11#/GPIO47 USBP11N
USBP11P
U2 A
0.1U_0402_16V4Z VCC VSS USBRBIAS

AG1
2 USBRBIAS#
3
W ICH9-M ES_FCBGA676
Within 500 mils
7
HOLD
Change U26 P/N from SA00000XT00 to SA000041N00 0915
ICH_SPI_CS0# 1
S
ICH_SPI_CLK_1 6
C SPI@
ICH_SPI_MOSI_1 5
D Q
2 ICH_SPI_MISO_1 2
R917
1 ICH_SPI_MISO
0_0402_5%
MX25L1606EM2I-12G_SO8
ICH9M(3/4)-USB,GPIO,PCIE
Change U33 footprint from WIESO_G6179-100000_8P to MX25L1606EM2I-12G_SO8 0920 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA7012P 1.0
Change Value from MX25L8005M2C-15G SOP 8P to MX25L1606EM2I-12G_SO8 0920 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2 1
5 4 3 2 1
+1.05VS
20 mils U9F U9E
+RTCVCC A23 VCCRTC VCC1_05[01] A15 1634mA AA26 VSS[001] VSS[107] H5
B15 0.1U_0402_16V4Z AA27 J23
ICH_V5REF_RUN VCC1_05[02] VSS[002] VSS[108]
1 1 2mA A6 V5REF VCC1_05[03] C15 AA3 VSS[003] VSS[109] J26
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C894 C898 D15 AA6 J27
0.1U_0402_16V4Z 0.1U_0402_16V4Z VCC1_05[04] VSS[004] VSS[110]
2mA VCC1_05[05] E15 1 1 1 1 AB1 VSS[005] VSS[111] AC22
C1168
C1169
ICH_V5REF_SUS AE1 F15 C895 C899 0.1U_0402_16V4Z AA23 K28
2 2 V5REF_SUS VCC1_05[06] VSS[006] VSS[112]
VCC1_05[07] L11 AB28 VSS[007] VSS[113] K29
AA24 VCC1_5_B[01] VCC1_05[08] L12 AB29 VSS[008] VSS[114] L13
2 2 2 2
AA25 VCC1_5_B[02] VCC1_05[09] L14 AB4 VSS[009] VSS[115] L15
AB24 VCC1_5_B[03] VCC1_05[10] L16 AB5 VSS[010] VSS[116] L2
+5VS +3VS AB25 L17 AC17 L26
VCC1_5_B[04] VCC1_05[11] VSS[011] VSS[117]
AC24 L18 AC26 L27
VCC1_5_B[05] VCC1_05[12] VSS[012] VSS[118]
AC25 M11 AC27 L5
VCC1_5_B[06] VCC1_05[13] VSS[013] VSS[119]
2
D R902 D
AD24 M18 AC3 L7
R901 D33 VCC1_5_B[07] VCC1_05[14] 0.01U_0402_16V7K VSS[014] VSS[120]
AD25
CORE
P11 1 2 +1.5VS AD1 M12
100_0402_5% VCC1_5_B[08] VCC1_05[15] CHB1608U301_0603 VSS[015] VSS[121]
RB751V_SOD323 AE25 P18 AD10 M13
VCC1_5_B[09] VCC1_05[16] VSS[016] VSS[122]
AE26 T11 1 1 AD12 M14
VCC1_5_B[10] VCC1_05[17] C896 C897 10U_0805_6.3V6M VSS[017] VSS[123]
AE27 T18 AD13 M15
1
VCC1_5_B[11] VCC1_05[18] VSS[018] VSS[124]

AE28 U11 AD14 M16
ICH_V5REF_RUN VCC1_5_B[12] VCC1_05[19] VSS[019] VSS[125]
AE29 U18 AD17 M17
VCC1_5_B[13] VCC1_05[20] 2 2 VSS[020] VSS[126]
1 20 mils F25
VCC1_5_B[14] VCC1_05[21]
V11 AD18
VSS[021] VSS[127]
M23
C893 G25 V12 AD21 M28
VCC1_5_B[15] VCC1_05[22] VSS[022] VSS[128]
H24 V14 AD28 M29
1U_0603_10V4Z VCC1_5_B[16] VCC1_05[23] +1.05VS VSS[023] VSS[129]
H25 V16 AD29 N11
2 VCC1_5_B[17] VCC1_05[24] VSS[024] VSS[130]
J24 VCC1_5_B[18] VCC1_05[25] V17 AD4 VSS[025] VSS[131] N12
VCCA3GP
10/01 Danson J25 VCC1_5_B[19] VCC1_05[26] V18 AD5 VSS[026] VSS[132] N13
K24 VCC1_5_B[20] 1 AD6 VSS[027] VSS[133] N14
Change D33 and D34 from K25 23mA C900 10U_0805_10V4Z AD7 N15
VCC1_5_B[21] VSS[028] VSS[134]
SC1H751H010 to SCS00000Z00 . L23 VCC1_5_B[22] AD9 VSS[029] VSS[135] N16
+5VALW +3VALW L24 R29 +1.5VS_DMIPLL_ICH AE12 N17
VCC1_5_B[23] VCCDMIPLL 2 VSS[030] VSS[136]
L25 VCC1_5_B[24] 48mA AE13 VSS[031] VSS[137] N18
M24 VCC1_5_B[25] VCC_DMI[1] W23 AE14 VSS[032] VSS[138] N26
2
M25 Y23 +1.05VS AE16 N27

R903 D34 VCC1_5_B[26] VCC_DMI[2] VSS[033] VSS[139]
N23 VCC1_5_B[27] 2mA AE17 VSS[034] VSS[140] P12
100_0402_5% RB751V_SOD323 N24 AB23 AE2 P13
VCC1_5_B[28] V_CPU_IO[1] VSS[035] VSS[141]
N25 VCC1_5_B[29] V_CPU_IO[2] AC23 AE20 VSS[036] VSS[142] P14
4.7U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
P24 AE24 P15
1
ICH_V5REF_SUS VCC1_5_B[30] VSS[037] VSS[143]

P25 VCC1_5_B[31] VCC3_3[01] AG29 +3VS 1 1 1 AE3 VSS[038] VSS[144] P16
C902
C903
C904
20 mils R24 AJ6 +3VS 1 (DMI) AE4 P17
VCC1_5_B[32] VCC3_3[02] +3VS (SATA) VSS[039] VSS[145]
1 R25 VCC1_5_B[33] VCC3_3[07] AC10 1 AE6 VSS[040] VSS[146] P2
C905 R26 C901 AE9 P23
VCC1_5_B[34] 0.1U_0402_16V4Z C906 0.1U_0402_16V4Z 2 2 2 VSS[041] VSS[147]
R27 VCC1_5_B[35] VCC3_3[03] AD19 AF13 VSS[042] VSS[148] P28
2
VCCP_CORE
1U_0603_10V4Z T24 AF20 1 0.1U_0402_16V4Z AF16 P29
2 VCC1_5_B[36] VCC3_3[04] 2 VSS[043] VSS[149]
T27 VCC1_5_B[37] VCC3_3[05] AG24 AF18 VSS[044] VSS[150] P4
T28 AC20 C907 AF22 P7
C VCC1_5_B[38] VCC3_3[06] VSS[045] VSS[151] C
T29 VCC1_5_B[39] AH26 VSS[046] VSS[152] R11
R904 2 +3VS
646mA U24 VCC1_5_B[40] 308mA AF26 VSS[047] VSS[153] R12
0_0805_5% 40 mils U25 B9 AF27 R13
10U_0805_10V4Z +1.5VS_PCIE_ICH VCC1_5_B[41] VCC3_3[08] VSS[048] VSS[154]
+1.5VS 1 2 V24 VCC1_5_B[42] VCC3_3[09] F9 AF5 VSS[049] VSS[155] R14
V25 G3 +3VS +1.5VS AF7 R15
1 VCC1_5_B[43] VCC3_3[10] 1 1 1 VSS[050] VSS[156]
1 1 1 U23 VCC1_5_B[44] VCC3_3[11] G6 AF9 VSS[051] VSS[157] R16
PCI
C908 + C910 C911 C912 W24 J2 C909 C913 C914 AG13 R17
VCC1_5_B[45] VCC3_3[12] VSS[052] VSS[158]
2
220U_6.3V_M W25 J7 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z AG16 R18
VCC1_5_B[46] VCC3_3[13] 2 2 2 VSS[053] VSS[159]
OSCON 2 2 2 2
K23
VCC1_5_B[47] VCC3_3[14]
K7 R906 @ AG18
VSS[054] VSS[160]
R28
Y24 R905 0_0402_5% AG20 T12
VCC1_5_B[48] VSS[055] VSS[161]
Y25
VCC1_5_B[49] 11mA AG23
VSS[056] VSS[162]
T13
10U_0805_10V4Z 2.2U_0603_6.3V4Z AJ4 +VCC_HDA_ICH AG3 T14
1
VCCHDA VSS[057] VSS[163]
R907 47mA 11mA AG6
VSS[058] VSS[164]
T15
AJ3 +VCCSUS_HDA_ICH 1 0_0402_5% AG9 T16
+1.5VS_SATAPLL_ICH AJ19 VCCSUSHDA 0.1U_0402_16V4Z VSS[059] VSS[165]
+1.5VS 1 2 AH12 T17
VCCSATAPLL VSS[060] VSS[166]
1U_0603_10V4Z
0.1U_0402_16V4Z 1 C915 AH14 T23

VSS[061] VSS[167]
10U_0805_10V4Z
CHB1608U301_0603 AC8 TP_VCCSUS1_05_ICH_1 C916 AH17 B26

VCCSUS1_05[1] 2 VSS[062] VSS[168]
1 1 +1.5VS AC16 F17 TP_VCCSUS1_05_ICH_2 T102 AH19 U12
VCC1_5_A[01] VCCSUS1_05[2] VSS[063] VSS[169]
C918
C919
1 AD15 T103 AH2 U13

C917 VCC1_5_A[02] 2 VSS[064] VSS[170]
AD16 AH22 U14
VCC1_5_A[03] VSS[065] VSS[171]
AE15 AD8 VCCSUS1_5_ICH_1 AH25 U15
2 2 VCC1_5_A[04] VCCSUS1_5[1] VSS[066] VSS[172]
ARX
1U_0603_10V4Z AF15 AH28 U16

2 VCC1_5_A[05] VCCSUS1_5_ICH_2 VSS[067] VSS[173]
AG15 F18 1 2 1 1 2 +3VALW AH5 U17
VCC1_5_A[06] VCCSUS1_5[2] C971 R908 @ R909 VSS[068] VSS[174]
AH15 AH8 AD23
VCC1_5_A[07] 0_0402_5% 0_0402_5% VSS[069] VSS[175]
AJ15 AJ12 U26
VCC1_5_A[08] 0.1U_0402_16V4Z VSS[070] VSS[176]
A18 AJ14 U27
VCCSUS3_3[01] 2 VSS[071] VSS[177]
AC11 D16 AJ17 U3
VCCPSUS
+1.5VS VCC1_5_A[09] VCCSUS3_3[02] VSS[072] VSS[178]

1 AD11 D17 AJ8 V1
C921 VCC1_5_A[10] VCCSUS3_3[03] VSS[073] VSS[179]
AE11 E22 1 B11 V13
VCC1_5_A[11] VCCSUS3_3[04] C920 VSS[074] VSS[180]
AF11
VCC1_5_A[12]
Follow KHLBX and CRB. B14
VSS[075] VSS[181]
V15
ATX
1U_0603_10V4Z AG10 B17 V23

2 VCC1_5_A[13] +3VALW 4.7U_0603_6.3V6M VSS[076] VSS[182]
B
AG11
VCC1_5_A[14] 212mA 2
B2
VSS[077] VSS[183]
V28
B
AH10 B20 V29
VCC1_5_A[15] 0.1U_0402_16V4Z VSS[078] VSS[184]
AJ10 AF1 B23 V4
1342mA 1 1 B5
VSS[080] VSS[186]
V5
AC9 B8 W26
+1.5VS VCC1_5_A[17] C922 C923 VSS[081] VSS[187]
1 C26 W27
C924 0.1U_0402_16V4Z VSS[082] VSS[188]
AC18 C27 W3
VCC1_5_A[18] 2 2 VSS[083] VSS[189]
AC19 E11 Y1
1U_0603_10V4Z VCC1_5_A[19] VSS[084] VSS[190]
T1 E14 Y28
2 VCCSUS3_3[06] VSS[085] VSS[191]
AC21 T2 E18 Y29
T3 E2 Y4
VCCSUS3_3[08] VSS[087] VSS[193]
G10 T4 E21 Y5
G9 T5 E24 AG28
T6 E5 AH6
VCCSUS3_3[11] +3VALW VSS[090] VSS[196]
AC12 U6 E8 AF2
VCCPUSB

AC13 U7 F16 B25
AC14 V6 F28
VCC1_5_A[25] VCCSUS3_3[14] VSS[093]
11mA VCCSUS3_3[15]
V7 1 F29
VSS[094]
+1.5VS AJ5 W6 C799 G12
VCCUSBPLL VCCSUS3_3[16] 4.7U_0603_6.3V6K VSS[095]
+1.5VS W7 G14 A1
VCCSUS3_3[17] VSS[096] VSS_NCTF[01]
USB CORE
1 1 11mA AA7
VCC1_5_A[26] VCCSUS3_3[18]
Y6
2
G18
VSS[097] VSS_NCTF[02]
A2
C800 C801 AB6 Y7 G21 A28
0.1U_0402_16V4Z 0.1U_0402_16V4Z VCC1_5_A[27] VCCSUS3_3[19] VSS[098] VSS_NCTF[03]
AB7 T7 G24 A29
VCC1_5_A[28] VCCSUS3_3[20] VSS[099] VSS_NCTF[04]
AC6 G26 AH1
2 2 VCC1_5_A[29] VSS[100] VSS_NCTF[05]
AC7 G27 AH29
C972 VCC1_5_A[30] VSS[101] VSS_NCTF[06]
G8 AJ1
2 1 A10
VCCLAN1_05[1]
H2
AJ2
+3VS VCC_LAN1_05_INT_ICH A11 G22 VCCCL1_05_ICH H23 AJ28
VCCLAN1_05[2] VCCCL1_05 VSS[104] VSS_NCTF[09]
0.1U_0402_16V4Z 19mA G23 +VCCCL1_5_INT_ICH 1 H28 AJ29
VCCCL1_5 C970 VSS[105] VSS_NCTF[10]
Follow KHLBX and CRB. A12
VCCLAN3_3[1] 1 H29
B1
1 B12 19mA C803 B29
C802 VCCLAN3_3[2] @ 1U_0603_10V4Z 0.1U_0402_16V4Z VSS_NCTF[12]
close to AC7 VCCCL3_3[1]
A24 +3VS 2
0.1U_0402_16V4Z CHB1608U301_0603 23mA B24
VCCCL3_3[2] 2
GLAN POWER
A +VCC_GLANPLL_ICH A27 ICH9-M ES_FCBGA676 A

1 2 VCCGLANPLL
2 R910 Follow KHLBX and CRB.
+1.5VS 1 1
2.2U_0603_6.3V4Z D28
C804 C805 VCCGLAN1_5[1]
D29 VCCGLAN1_5[2]
(10UF*1, 2.2UF*1) 2 2
E26 VCCGLAN1_5[3]
E27 VCCGLAN1_5[4]
10U_0805_10V4Z
R911 4.7U_0805_10V4Z 80mA A26
+1.5VS 1 2
CHB1608U301_0603
+3VS
VCCGLAN3_3
ICH9-M ES_FCBGA676
1 1mA Issued Date 2010/09/10 Deciphered Date 2010/08/19 Title
C806
ICH9M(4/4)-POWER&GND
2 B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA7012P
5 4 3 2 1
A B C D E
+5VS +5VS +5VS +5VS +5VS Pre MP ADD for ESD solution
+5VS +5VS +5VS
3 3 3 3 3
Near D26 Near D3 Near D21
1 BLUE 1 GREEN 1 RED 1 JVGA_HS 1 JVGA_VS
1 1 1
2 2 2 BAT54S-7-F_SOT23-3 2 2
@ @ @ @ @ C624 C627 C658
D1 D2 D3 D27 D26 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 2 2 2 1
FCM1608CF-121T03 0603
<10> DAC_RED 1
L11
2 RED +5VS
D21
+CRT_VCC
CRT Connector
FCM1608CF-121T03 0603 F1
1 2 GREEN 2 1 1 2 +CRTVCC_CONN
<10> DAC_GRN
L10 1
FCM1608CF-121T03 0603 RB491D_SC59-3 1.1A_6V_SMD1812P110TF
1 2 BLUE C629
<10> DAC_BLU
L9 R91 @
W=40mils 0.1U_0402_16V4Z
1
1
1 2 2
1 1 1 1 1 1
R153 R131 R90 C158 C146 C137 C157 C145 C136 0_0603_5%
150_0402_1% 150_0402_1% 150_0402_1% 10P_0402_50V8J 10P_0402_50V8J
2 2 2 2 2 2
2
10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J10P_0402_50V8J JCRT1

CLOSE TO CONN T10
6
11
2
RED 1 2
7
CRT_DDC_DAT_CONN 12
GREEN 2
8
JVGA_HS 13
BLUE 3
9
JVGA_VS 14 G 16
4 G 17
10
+CRT_VCC CRT_DDC_CLK_CONN 15
5
1 R575 2 1
1 TYCO_1775763-1
10K_0402_5% C628 ME@
C619 100P_0402_50V8J
2
0.1U_0402_16V4Z
2 Follow KHLBx
5
L32
P
OE#
2 4 CRT_HSYNC_1 1 2 CRT_HSYNC_2 1 2 JVGA_HS

<10> CRT_HSYNC A Y R576 39_0402_1% FCM1608CF-121T03 0603
G
U26 +3VS +3VS +CRT_VCC

3 TC7SET125FUF_SC70 1 3
3
@
C626
1
10P_0402_50V8J
+CRT_VCC 2 R159 R162
2.2K_0402_5% 2.2K_0402_5% R157 R158
5
1 R580 2 2.2K_0402_5% 2.2K_0402_5%
1
2
10K_0402_5% <10> CRT_DDC_DATA 4 3 CRT_DDC_DAT_CONN
C620
0.1U_0402_16V4Z Q13B
2
2 Follow KHLBx 2N7002DW-T/R7_SOT363-6
5
L31 <10> CRT_DDC_CLK 1 6 CRT_DDC_CLK_CONN

P
OE#
2 4 CRT_VSYNC_1 1 2 CRT_VSYNC_2 1 2 JVGA_VS 1 1

<10> CRT_VSYNC A Y R577 39_0402_1% FCM1608CF-121T03 0603 @ @
Q13A
G
U25 1 C178 C177

TC7SET125FUF_SC70 2N7002DW-T/R7_SOT363-6 100P_0402_50V8J 68P_0402_50V8K
3
@ C625 2 2
10P_0402_50V8J Change Q13 from SB00000EO10 to SB00000AR00.
2
4 4

CRT Connector
B 1.0
LA7012P
A B C D E
5 4 3 2 1
INVPWM
DAC_BRIG
+LEDVDD (40MIL) B+
CMOS Camera
470P_0402_50V7K
470P_0402_50V7K
470P_0402_50V7K
DISPOFF# 680P_0402_50V7K 4.7U_0805_25V6-K
1 R549 2 0_0805_5%
C15 1 1
1 @ 1 @ 1 @ @ C567 C566
C13 C296 R539 @
D 0_0603_5% +CMOS_PW D
2 2 1 2
2 2 2 +3VS +CMOS_PW +5VS
Q24 CMOS@
JLVDS1 R596 CMOS@ AP2301GN-HF_SOT23-3 R280 CMOS@
+LCDVDD_CONN 2 1 (20 MIL) 0_0603_5% 0_0603_5%
EMI demand 2 1 USB20_N2 CAM_3 3 CAM_1
(60 MIL) 4 4 3 3 USB20_N2 <19> +3VS 1 2 1 1 2
1 6 5 USB20_P2 USB20_P2 <19> CMOS
680P_0402_50V7K 6 5
8 8 7 7 1 1
+3VS @ C14 10 9 LVDS_A0#
10 9 LVDS_A0# <10> +5VS
12 11 LVDS_A0 C275 C337
LVDS_A0 <10>
2
2 12 11 R270 CMOS@ 0.1U_0402_16V4Z 10U_0805_10V4Z
14 14 13 13
16 15 LVDS_A1# 100K_0402_5% 2 CMOS@ 2 CMOS@
16 15 LVDS_A1# <10>
@ R392 R395@ INVPWM 18 17 LVDS_A1 CMOS1
18 17 LVDS_A1 <10>
2.2K_0402_5% 2.2K_0402_5% DISPOFF# 20 19
20 19 LVDS_A2# R435
<27> DAC_BRIG 22 22 21 21 LVDS_A2# <10>
24 23 LVDS_A2 150K_0402_5% 1
24 23 LVDS_A2 <10>
1
26 26 25 25 CMOS@
<10> EDID_CLK EDID_CLK 28 27 LVDS_ACLK# C326
OUT
28 27 LVDS_ACLK# <10>
<10> EDID_DATA EDID_DATA 30 29 LVDS_ACLK 0.01U_0402_16V7K
30 29 LVDS_ACLK <10> 2
CMOS@
32 GNDGND 31 <27> CMOS_OFF# 2 IN
GND
ACES_87142-3041
C
ME@ Q21 C
+3VS DTC124EKAT146_SC59-3
3
CMOS@
R261
1
0_0402_5%
1 2 R250
@
4.7K_0402_5%
D12
@
2
BKOFF# 1 2 DISPOFF#
<27> BKOFF#
RB751V_SOD323
LCD POWER CIRCUIT
1
R751 10/01
10K_0402_5%
Change D12 from SC1H751H010 to SCS00000Z00 . +LCDVDD +5VALW
2
+3VS
W=60mils
1
R13 R31
R432 150_0603_1% 100K_0402_5% 1
0_0402_5% C539
1 2 4.7U_0603_6.3V6K
<27> INVT_PWM
B Q4 B
2
1
3
D R38 2
2N7002H_SOT23-3
2 1 2 2
Q3 G 220K_0402_5%
R430 @ S 1
1
0_0402_5% DTC124EK AP2301GN-HF_SOT23-3
1 2 C34 W=60mils
OUT
1
R35 0.1U_0402_16V4Z
0_0402_5% 2 +LCDVDD +LCDVDD_CONN
L2
<10> GMCH_ENVDD 2 1 LCD_ENVDD 2
+3VS IN
1 2
GND
Q5 FBMA-L11-201209-221LMA30T_0805
1
DTC124EKAT146_SC59-3 1 1
3
5
U22 C33 C25

1 R37 @
P
NC INVPWM 100K_0402_5% 4.7U_0805_10V4Z 0.1U_0402_16V4Z

<10> GMCH_PWM 2 A Y 4
2 2
G
2
@
TC7SZ14FU_SSOP5
3
2
G
A A
R431 @
3 1 INVPWM 2 1 +3VS
S
2N7002H_SOT23-3
10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Q82 @
For GMCH DPST THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS/CAMERA
B 1.0
LA7012P
5 4 3 2 1
A B C D E
Mini-Express Card for WLAN(Half)

+3VS_WLAN
+3VS +3VS_WLAN +1.5VS

J6 @ 1 1 1
1 2Watt C422 C423 C424 1
1 2 @
1 2
2
@ J4
@J4 0.01U_0402_16V7K 0.1U_0402_16V4Z 4.7U_0603_6.3V6M
JUMP_43X79 2 2 2
2
JUMP_43X79
+3VS_WLAN
1
JWLAN1
1
<19,24> ICH_PCIE_WAKE# ICH_PCIE_WAKE# 1 @ 2 ICH_PCIE_WAKE#_R 1 2
BT_ACTIVE R334 1 WAKE# 3.3V +1.5VS_CONN
<30> BT_ACTIVE 2 0_0402_5% 3 NC GND 4
R333 @ 0_0402_5% 5 6 +1.5VS_CONN
NC 1.5V
<16> WLAN_CLKREQ1# 7 CLKREQ# NC 8
9 GND NC 10
<16> CLK_PCIE_WLAN1# 11 REFCLK- NC 12 1 1 1
13 14 C425 C426 C433
<16> CLK_PCIE_WLAN1 REFCLK+ NC
15 16 @
GND NC 0.01U_0402_16V7K 0.1U_0402_16V4Z 4.7U_0603_6.3V6M
17 NC GND 18
19 20 R377 1 2 0_0402_5% 2 2 2
NC NC WL_OFF# <27>
21 GND PERST# 22 PLT_RST# <8,17,24>
23 24 R376 1 2 @ 0_0402_5% +3VALW
<19> PCIE_RXN3 PERn0 +3.3Vaux
25 26 R375 1 2 0_0402_5% +3VS_WLAN
<19> PCIE_RXP3 PERp0 GND
27 GND +1.5V 28
29 30 R374 1 2 @ 0_0402_5% ICH_SMBCLK <16,19>
GND SMB_CLK R373 1
2 <19> PCIE_TXN3 31 PETn0 SMB_DATA 32 2 @ 0_0402_5% ICH_SMBDATA <16,19> 2
<19> PCIE_TXP3 33 PETp0 GND 34
35 GND USB_D- 36 USB20_N5 <19>
+3VS_WLAN 37 38
NC USB_D+ USB20_P5 <19>
39 NC GND 40
41 42 R372 2 1 @ 300_0402_5%
NC LED_WWAN# R371 2 0_0402_5%
43 NC LED_WLAN# 44 1 WLAN_LED# <32>
45 NC LED_WPAN# 46
47 NC +1.5V 48
2
100_0402_1% 1 2 R274 49 50
<27> EC_TX_P80_DATA NC GND
100_0402_1% 1 2 R273 51 52 R626
<27> EC_RX_P80_CLK NC +3.3V 100K_0402_5%
53 GND GND 54
1
+5VS
TAITW_PFPET0-AFGLBG1ZZ4N0
2
For EC to detect ME@

R625
debug card insert. 100K_0402_5%
1
3 3
4 4

Mini-Card/DEBUG-PORT
1.0
LA7012P
A B C D E
5 4 3 2 1
+3VALW +3V_LAN +1.7_VDDCT +1.7_LX

Close together
Power On strapping
Pin Description Chip Default
Layout Notice : Place as close
J8 chip as possible. L39 H:Over Clock Enable
+1.7_VDDCT 1 2 +1.7_LX LED0 H
1000P_0402_50V7K
4.7UH_SIA4012-4R7M_20% L:Over Clock Disable
0.1U_0402_16V4Z
1 2
1 2 *
C549
C548
C547
10U_0805_10V4Z
1 1
JUMP_43X79
H:SWR Switch mode regulator Select *
Note: Place Close to LAN chip LED1 --
@
GIGA@
D 2 2 L39 DCR< 0.15 ohm AR8151 Pin23=LED2. D
Atheros request can't disable LAN power Rate current > 1A AR8152, Pin23 is CLKREQ
Close to
Atheros request reserve Pin40
+3V_LAN
Place Close to LAN chip
MDI0+ R526 1 2 1@ 2 C594 1000P_0402_50V7K
49.9_0402_1%
R251 1 @ 2 4.7K_0402_5% PLT_RST# MDI0- R527 1 2 1 2 C592 0.1U_0402_16V4Z
49.9_0402_1%
R252 1 @ 2 4.7K_0402_5% PCIE_WAKE#_R R1160 R1161 R1162 R1163 MDI1+ R528 1 2 1@ 2 C577 1000P_0402_50V7K
49.9_0402_1%
R253 1 @ 2 4.7K_0402_5% CLKREQ_LAN# MDI1- R529 1 2 1 2 C593 0.1U_0402_16V4Z
49.9_0402_1%
U29 8152@ MDI2+ R530 1 2 1@ 2 C580 1000P_0402_50V7K
GIGA@ 49.9_0402_1%
0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% MDI2- R531 1 2 1 2 C591 0.1U_0402_16V4Z
NONSURGE@ NONSURGE@ NONSURGE@ NONSURGE@ GIGA@ 49.9_0402_1% GIGA@
MDI3+ R532 1 2 1@ 2 C599 1000P_0402_50V7K
GIGA@ 49.9_0402_1%
S IC AR8152-AL1E QFN 40P E-LAN CTRL MDI3- R533 1 2 1 2 C583 0.1U_0402_16V4Z
no overclocking GIGA@ 49.9_0402_1% GIGA@
PD 5.1K
Place Close to Chip U29 1 2 LED0,1,2 intel Pull UP Note 1 : 8152 no mount MDI3+, MDI3-, MDI2-, MDI2+
C R515 5.1K_0402_5% C
C553 1 PCIE_PRX_LANTX_N1 ACTIVITY
resister and cap
<19> PCIE_IRX_PTX_N1 2 0.1U_0402_16V7K 29 TX_N LED_0 38 ACTIVITY <25>
LAN_LINK#
C552 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_P1 30
Atheros LED_1 39
23 1 8152@ 2
LAN_LINK# <25> CLKREQ_LAN#
Note 2 : C594, C577, C580, C599, reserved for EMI.
<19> PCIE_IRX_PTX_P1 TX_P LED_2
8151-AL1A R516 0_0402_5%
<19> PCIE_ITX_C_PRX_N1 36 RX_N Pre MP Add it for EMI
12 MDI0- SURGE@ 1 R1160 2 3.9_0402_1% MDI0-_R
TRXN0 MDI0-_R <25>
35 11 MDI0+ SURGE@ 1 R1161 2 3.9_0402_1% MDI0+_R
<19> PCIE_ITX_C_PRX_P1 RX_P TRXP0 MDI1- SURGE@ MDI1-_R MDI0+_R <25>
15 1 R1162 2 3.9_0402_1%
TRXN1 MDI1-_R <25>
<16> CLK_PCIE_LAN# 2 R517 1 0_0402_5% CLK_PCIE_LAN#_C 32 REFCLK_N TRXP1 14 MDI1+ SURGE@ 1 R1163 2 3.9_0402_1% MDI1+_R
MDI1+_R <25>
<16> CLK_PCIE_LAN 2 R518 1 0_0402_5% CLK_PCIE_LAN_C 33 REFCLK_P TRXN2 18 MDI2-
MDI2- <25>
17 MDI2+
TRXP2 MDI2+ <25>
PLT_RST# 2 21 MDI3-
<8,17,23> PLT_RST# PERST# TRXN3 MDI3- <25>
20 MDI3+
TRXP3 MDI3+ <25>
<19,23> ICH_PCIE_WAKE#
R519 1 @ 2 0_0402_5% PCIE_WAKE#_R 3 W AKE# 9/27 Add it for avoid to be struck by lightning
<27> LAN_WAKE# R521 1 2 0_0402_5% Close Pin 10
25 10 LAN_RBIAS 1 2 +3V_LAN
SMCLK RBIAS
26 SMDATA
R522 2.37K_0402_1% C554 & C555 Close pin1 < 200mil
+3V_LAN
C557 & C558 Close pin < 400mil Part Number = SC300001J00
28 TEST_RST VDD33 1
C554
C555
C557
@ C558
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
1U_0402_6.3V4Z
27 TESTMODE 1 1 1 1 D24
8152@ 40 +1.7_LX MDI0+ 1 10
LX +1.7_LX 1 10
C559 1 2 0.1U_0402_16V4Z LAN_XTALO 7 2 9 MDI1-
LAN_XTALI XTLO 2 2 2 2 MDI0- 2 9
8 XTLI 3 3 8 8
5 +1.7_VDDCT 4 7 MDI1+
GND
VDDCT +1.7_VDDCT 4 7
1 2 5 5 6 6
CLKREQ_LAN# 1 GIGA@ 2 CLKREQ_LAN#_R 4 C561 0.1U_0402_16V4Z
<16> CLKREQ_LAN# CLKREQ#
R525 0_0402_5% 24 +1.1_DVDDL SURGE@
11
DVDDL +1.1_DVDDL TCLAMP3304N.TCT_SLP2626P10-10
B DVDDL_REG 37 B
+1.1_AVDDL 13
+1.1_AVDDL AVDDL
19 AVDDL
+1.1_AVDDL +2.7_AVDDH_R 0_0402_5% 1 2 R520 +2.7_AVDDH
+1.1_AVDDL
31
34
AVDDL AVDDH 16
22 +2.7_AVDDH Customer Lan Will used
AVDDL AVDDH
+1.1_AVDDL 6 AVDDL_REG AVDDH_REG 9 +2.7_AVDDH GIGA@ surge Semtech
Suggesttion 3304N
C564
C565
C568
C601
C597
C600
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1 1 1 1
C572
C571
C574
C573
C563
C562
C560
1U_0402_6.3V4Z
41 GND 1 1 1 1 1 1 2
AR8151-AL1A_QFN40_5X5 Part Number = SC300001J00
2 2 2 2 2 2
GIGA@
GIGA@
GIGA@
GIGA@
LAN_XTALI 2 2 2 2 2 2 1 D20
MDI2+ 1 10
LAN_XTALO 1 10 MDI3-
2 2 9 9
Y6 MDI2- 3 8
3 8 MDI3+
1 2 4 7
GND
4 7
Near Near Near Near Near Near Near Near Near Near 5 5 6 6
25MHZ_20PF_7A25000012
Pin13 Pin19 Pin31 Pin34 Pin6 Pin9 Pin22 Pin16 Pin37 Pin24
27P_0402_50V8J
27P_0402_50V8J
1 1
11
C578
C579
TCLAMP3304N.TCT_SLP2626P10-10 @
2 2
A A
Configure Configure
Pin4 R525 C559 Pin23 R516 Security Classification Compal Secret Data Compal Electronics, Inc.
AR8152 VDDCT_REG * CLKREQn * LAN-AR8151/8152
AR8151 CLKREQn * LED[2] DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA7012P 1.0
5 4 3 2 1
5 4 3 2 1
9/27 Add it for avoid to be struck by lightning

BS201N-LV C602 SCV00001400
MCT3 1 2
@
BS201N-LV C603 SCV00001400
MCT2 1 2
@
Customer Lan BS201N-LV C604 SCV00001400
D D
+1.7_VDDCT surge MCT1 1
@
2
Suggesttion MCT0
BS201N-LV C609 SCV00001400
1 2
2
@
R306 Will used BS-201N-LV
0_0603_5%
1
C427 2 1 1U_0402_6.3V4Z
T8 GIGA@
C435 2 1 0.1U_0402_16V4Z +1.7_VDDCT_R 1 24 MCT3 2 R534 1 GIGA@
GIGA@ MDI3+ TCT1 MCT1 MDO3+ 75_0402_5%
<24> MDI3+ 2 TD1+ MX1+ 23
MDI3- 3 22 MDO3-
<24> MDI3- TD1- MX1-
C436 2 1 0.1U_0402_16V4Z 4 21 MCT2 2 R535 1 GIGA@ Place closely JRJ45
GIGA@ MDI1+_R TCT2 MCT2 MDO1+ 75_0402_5%
<24> MDI1+_R 5 TD2+ MX2+ 20
MDI1-_R 6 19 MDO1- 40 mil
<24> MDI1-_R TD2- MX2-
C438 2 1 0.1U_0402_16V4Z 7 18 MCT1 2 R536 1 LAN_GND
MDI2+ TCT3 MCT3 MDO2+ 75_0603_5%
RJ45_GND
<24> MDI2+ 8 TD3+ MX3+ 17
MDI2- 9 16 MDO2-
<24> MDI2- TD3- MX3-
C440 2 1 0.1U_0402_16V4Z 10 15 MCT0 2 R537 1
TCT4 MCT4
2
MDI0+_R 11 14 MDO0+ 75_0603_5%
<24> MDI0+_R TD4+ MX4+
MDI0-_R 12 13 MDO0- D11 D13
C <24> MDI0-_R TD4- MX4- C
PESD5V0U2BT 3P PESD5V0U2BT 3P
GSL5009LF 1 @ @
C585
1
1000P_1206_2KV7K
2
T7 8152@
MDI1+_R 1 16 MDO1+
MDI1-_R TD+ TX+ MDO1-
2 TD- TX- 15
+1.7_VDDCT_R 3 14 MCT1
CT CT
4 NC NC 13
5 NC NC 12
+1.7_VDDCT_R 6 11 MCT0
MDI0+_R CT CT MDO0+
7 RD+ RX+ 10
12/13 PreMP Add it for avoid to be struck by lightning MDI0-_R 8 9 MDO0- JRJ45
RD- RX-
12 Amber LED-
Near to near JRJ45. S X'FORM_ NS681680 ACTIVITY R538 2 1 220_0402_5% ACTIVITY_R 11 16
D55 <24> ACTIVITY Amber LED+ SHLD4
MDO0- 1 10 MDO0+ 1 MDO3- 8 15
1 10 PR4- SHLD3
2 2 9 9
3 8 C387 MDO3+ 7
3 8 470P_0402_50V7K PR4+ 40 mil
B 4 7 B
GND
4 7 2 MDO1-
5 5 6 6 PVT Add EMI solution. 6 PR2-
LAN_GND
SURGE@ MDO2- 5
11
TCLAMP3302N.TCT_SLP2626P10-10 R97 PR3-

BLM18PG181SN1D_0603 MDO2+ 4 PR3+
D52 2 1
MDO1+ 3
MDO1- MDO1+ PR2+
1 1 10 10
2 9 MDO0- 2
2 9 C863 0.1U_0603_25V7K PR1-
3 3 8 8 SHLD2 14
4 7 1 2 MDO0+ 1
GND
4 7 PR1+
5 5 6 6
LAN_LINK# 10 Green LED- 13
<24> LAN_LINK# SHLD1
SURGE@ 1 220_0402_5%
11
TCLAMP3302N.TCT_SLP2626P10-10 R884 0_0402_5% +3V_LAN 2 1 +3V_LAN_R 9 Green LED+

1 2 C386 R702
470P_0402_50V7K 1 FOX_JM36113-P2221-7F
2
ME@
C395
470P_0402_50V7K
2
A A

LAN_Transformer
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA7012P 1.0
5 4 3 2 1
5 4 3 2 1
CX20671
High Definition Audio Codec SoC +3VS HDA_RST_CODEC#
With Integrated Class-D Stereo EMI
1
HDA_SYNC_CODEC
Amplifier. R363
@ 4.7K_0402_5% HDA_SDOUT_CODEC
An integrated 5 V to 3.3 V Low-dropout
voltage regulator (LDO). 1 2 HDA_BITCLK_CODEC
2
33_0402_5% @ R331
HDA_RST_CODEC#
An integrated 3.3 V to 1.8V Low-dropout
1 1 1 1
voltage regulator (LDO). C584
1
C375
C376
C378
C370
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
@
100P_0402_50V8J 2 2 2 2
D 2 D
@ @ @ @
R309
+3VS 2 1 +DVDD_3_3
0_0603_5%
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1
C407
C400
C408
FILT_1_65 +LDO_OUT_3_3V_R
+3VS 2 1 +VAUX_3.3
0_0402_5% R339 2 2 2
1U_0603_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+3VALW 2 @ 1 1 1 1 1
10U_0805_10V4Z
0.1U_0402_16V4Z
C414
C412
C410
C409
0_0402_5% R337 1 1 AVDD_3.3 pinis output of
C381
C380
To support Wake-on-Jack or Wake-on-Ring, the CODEC internal LDO. NOT connect
VAUX_3.3 & VDD_IO pins must be powerd by a rail that
is not removed unless AC power is removed. 2 2 2 2 to external supply.
*DSH page42 has more detail. 2 2
Layout Note:Path from +5VS to LPW R_5.0

RPW R_5.0 must be very low
2 1 +VDD_IO resistance (<0.01 ohms)
+3VS
0_0402_5% R328 R311
+3VALW 2 @ 1 10K only needed if supply to VAUX_3.3 +AVDD_5V 2 1 +5VS
1U_0603_10V4Z
0.1U_0402_16V4Z
0_0402_5% R329 1 1 is removed during system re-start. 0_0603_5%
+CLASSD_5V
C369
C377
1 R348 2 +5VS
10U_0805_10V4Z
0.1U_0402_16V4Z
1 1
FILT_1_8
C413
C411
0.1_1206_1%
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2 2
1 1 1 1
<BOM Structure>
C391
C392
C390
C399
10U_0805_10V4Z
0.1U_0402_16V4Z
1
2 2
10K_0402_5%
1 1
C371
C379
R332 2 2 2 2
0.1U_0402_16V4Z
2 2
18
29
27
28
26
C 1 C
3
7
2
C393
U17
FILT_1.8
VAUX_3.3
DVDD_3.3
FILT_1.65
AVDD_3.3
VDD_IO
AVDD_5V
AVDD_HP
Please bypass caps very close to device.
12 2
LPWR_5.0
15
HDA_RST_CODEC# RPWR_5.0 +CLASSD_5V_C
<18> HDA_RST_CODEC# 9 17
RESET# CLASS-D_REF R344 1 2 5.11K_0402_1% +VAUX_3.3
HDA_BITCLK_CODEC 5 Sense resistors must be
<18> HDA_BITCLK_CODEC BIT_CLK
HDA_SYNC_CODEC 8 36 SENSE_A R345 1 2 10K_0402_1% Port C
<18> HDA_SYNC_CODEC SYNC SENSE_A MIC_JD <30> connected same power
33_0402_5% 1 R336 2 HDA_SDIN0_R 6 R346 1 2 39.2K_0402_1% PLUG_IN <30> Port A
<18> HDA_SDIN0 SDATA_IN that is used for VAUX_3.3
HDA_SDOUT_CODEC 4
<18> HDA_SDOUT_CODEC SDATA_OUT
35 MIC_INR Internal MIC
PORTB_R MIC_INL
PORTB_L
34 Vender advise: Change R352 and R351 frorm 2.2K to 3.3K by Danson
33 +MICBIASB
PC_BEEP B_BIAS R352 1
EAPD active low 10 2 3.3K_0402_5% +MICBIASC
PC_BEEP R351 1 2 3.3K_0402_5%
0=power down ex AMP 32 +MICBIASC
C_BIAS EXT_MICR EXT_MICR_C
1=power up ex AMP PORTC_R
31 C403 1 2 2.2U_0603_10V7K R350 100_0402_1%
EXT_MIC_R <30>
30 EXT_MICL C415 1 2 2.2U_0603_10V7K EXT_MICL_C External MIC
PORTC_L EXT_MIC_L <30>
0_0402_5% 1 2 R338 38 R356 100_0402_1%
<27> EAPD GPIO0/EAPD#
EC_MUTE# 2 1 37
<27> EC_MUTE# GPIO1/SPK_MUTE#
0_0402_5% R343 23 HP_OUTR_R R601 1 2 15_0402_5%
PORTA_R HP_OUTR <30>
22 HP_OUTL_R R602 1 2 15_0402_5% Headphone
PORTA_L HP_OUTL <30>
40
DMIC_CLK
Changed from 5.1ohm to 15ohm for "zi zi"noise.
1 24
DMIC_1/2 NC
25
NC
39
C416 SPK_L2+ NC
11
LEFT+ Vender advise: Change R349 frorm 4.7K to 2.2K and C347 from 2.2u to 4.7
1 2 SPK_L1- 13
0.1U_0402_16V4Z LEFT-
Internal SPEAKER AVEE
21
+MICBIASB
19
C396 SPK_R2+ FLY_P
16 20 1 2
10U_0805_10V4Z
0.1U_0402_16V4Z
SPK_R1- RIGHT+ FLY_N C401 1U_0603_10V4Z
1 2 14 1 1
RIGHT-
2
0.1U_0402_16V4Z
C406
C404
GND
Add for ESD solution. R349

@ R355 2.2K_0402_5%
B 2 2 B
1 2 CX20671-11Z_QFN40_6X6
41
0_0402_5%
1
@ R354 MIC1 C394 4.7U_0603_6.3V6K
1 2 1 MIC_IN 1 2 MIC_INR
0_0402_5% 2 GNDA
@ R362 MIC_INL
1 2 WM-64PCY_2P
0_0402_5% 45@
2
D4
PESD5V0U2BT 3P
GND GNDA
1
Add for ESD solution.
wide 20MIL
JSPK1
SPK_R1- L19 1 2 0_0603_5% SPK_R1-_CONN 1
SPK_R2+ L20 0_0603_5% SPK_R2+_CONN 1
1 2 2
PC Beep SPK_L1-
SPK_L2+
L22
L23
1
1
2
2
0_0603_5%
0_0603_5%
SPK_L1-_CONN
SPK_L2+_CONN
3
4
2
3
4
5
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
@ GND1
1 1 1 1 6
GND2
2
C632
C633
C634
C635
2 1 PC_BEEP1
R598 0_0402_5% D5 D6 ACES_88231-04001
PESD5V0U2BT 3P PESD5V0U2BT 3P ME@
2 2 2 2 @ @
EC Beep <27> BEEP# 2 1
D18 RB751V_SOD323
1
R582
ICH Beep 2 1 1 2 1 2 PC_BEEP
<19> SB_SPKR
A 33_0402_5% C645 0.1U_0402_16V4Z A
D35 RB751V_SOD323 Add for ESD solution.
2 1PC_BEEP2
R599 @ 0_0402_5%
1
@
R585
10K_0402_5%
2

CX20671 Codec
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
LA7012P
5 4 3 2 1
+3VALW
+EC_AVCC
+3VS
1 1 1 1 1 1
0.1U_0402_16V4Z
C516
0.1U_0402_16V4Z
C517
0.1U_0402_16V4Z
C518
0.1U_0402_16V4Z
C519
1000P_0402_50V7K
C520
1000P_0402_50V7K
C523
L21 1 2
+3VALW +EC_AVCC
FBM-11-160808-601-T_06032 1
C521 2 2 2 2 2 2
0.1U_0402_16V4Z C522 1 2 NUM_LED#
111
125
1000P_0402_50V7K +3VS R102 @ 10K_0402_5%
22
33
96
67
9
1 2 1 ECAGND 2 1 2 CAPS_LED#
L24 FBM-11-160808-601-T_0603 R103 @ 10K_0402_5%
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
1
1 2
R60 0_0402_5% @ R105
D46 1 21 INVT_PWM 10K_0402_5%
<18> GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM <22>
<18> KB_RST# 2 @ 1 KB_RST#_EC 2 23 BEEP#
BEEP# <26>
2
RB751V_SOD323 KBRST#/GPIO01 BEEP#/PWM2/GPIO10 EC_FAN_PWM
<19> SERIRQ 3 26
SERIRQ# FANPWM1/GPIO12 ACOFF
10/01 Danson <18> LPC_FRAME# 4
LFRAME# ACOFF/FANPWM2/GPIO13
27 ACOFF <34,36> 10/01 Add for reduce noise
LPC_AD3 5
<18> LPC_AD3 LAD3
Change D46 from SC1H751H010 to SCS00000Z00 . LPC_AD2 7 PWM Output
<18> LPC_AD2 LAD2
LPC_AD1 8 63 BATT_TEMP FSTCHG
<18> LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP <35>
LPC_AD0
LAD0 LPC & MISC
<18> LPC_AD0 10 64
BATT_OVP/AD1/GPIO39 ADP_I
2 1 2 1 65 ADP_I <36>
@ C525 22P_0402_50V8J @ 10_0402_5% ADP_I/AD2/GPIO3A
<16> CLK_PCI_LPC 12
PCICLK AD Input AD3/GPIO3B
66
R100 13 75
<17> PCI_RST# PCIRST#/GPIO05 AD4/GPIO42
1 2 EC_RST# 37 76 TSATN#_EC R59 1 2 @ 0_0603_5%
+3VALW ECRST# SELIO2#/AD5/GPIO43 TSATN# <8>
R63 47K_0402_5% EC_SCI#
100P_0402_50V8J
100P_0402_50V8J
<19> EC_SCI#
BATT_LEN#
20
SCI#/GPIO0E C655 closely PU3.3
2 <35> BATT_LEN# 38 1 1
CLKRUN#/GPIO1D DAC_BRIG @
C524 DAC_BRIG/DA0/GPIO3C
68 DAC_BRIG <22>
C655 C656
C656 closely U46.65
PVT EN_DFAN1/DA1/GPIO3D
70
0.1U_0402_16V4Z Add BATT_LEN# on Pin38 DA Output 71 IREF
1 IREF/DA2/GPIO3E IREF <36> 2 2
KSI0 55 72 +3VALW
KSI0/GPIO30 DA3/GPIO3F CHGVADJ <36>
KSI1 56
KSI1/GPIO31 R65
KSI2 57 EC_MUTE# 1 2 @ 10K_0402_5%
KSI3 KSI2/GPIO32
Place closely pin13 KSI4
58
KSI3/GPIO33 PSCLK1/GPIO4A
83
USB_ON#
EC_MUTE# <26>
59 84 USB_ON# <29>
KSI5 KSI4/GPIO34 PSDAT1/GPIO4B
60 85 NOVO# <30>
KSI6 KSI5/GPIO35 PSCLK2/GPIO4C
61
KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D
86
PCI_RST# KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK <32>
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA <32> +5VS
1 KSO1 40
KSO2 KSO1/GPIO21
41
C859 KSO3 KSO2/GPIO22 R67
42 97 1 2 @ 4.7K_0402_5% TP_CLK R61 1 2 4.7K_0402_5%
0.1U_0402_16V4Z KSO4 KSO3/GPIO23 SDICS#/GPXOA00 EN_WOL#
+3VALW 2
43
KSO4/GPIO24 SDICLK/GPXOA01
98 KB926 SPI STRAP PIN
KSO5 TP_DATA R62 2 4.7K_0402_5%
KSO5/GPIO25 Int. K/B
44 99 BATT_SEL_EC <36> 1
KSO6 SDIDO/GPXOA02
45 109
KSO7 KSO6/GPIO26 Matrix SDIDI/GPXID0 CMOS_OFF# <22>
46
KSO7/GPIO27 SPI Device Interface
KSO8 47
KSO8/GPIO28 FRD#SPI_SO <28>
KSO9 48 119 FRD#SPI_SO BATT_TEMP 1 2
KSO9/GPIO29 SPIDI/RD# R818 2
09/16 Add C859 For ESD KSO10 49 120 FWR#SPI_SI 1 0_0402_5% SPI_SI <28>
C527 100P_0402_50V8J
KSO11 KSO10/GPIO2A SPIDO/WR# SPI_CLK R817 1
50 SPI Flash ROM 126 2 33_0402_5% SPI_CLK_R <28>
ACIN 1 2
1
KSO11/GPIO2B SPICLK/GPIO58 R421 1

KSO12 51 128 FSEL#SPICS# 2 0_0402_5% SPI_CS# <28>
C528 100P_0402_50V8J
R931 R932 KSO13 KSO12/GPIO2C SPICS#
52
47K_0402_5% 47K_0402_5% KSO[0..17] KSO14 KSO13/GPIO2D
53
<32> KSO[0..17] KSO15 KSO14/GPIO2E
54 73
KSI[0..7] KSO16 KSO15/GPIO2F CIR_RX/GPIO40
81 74
2
<32> KSI[0..7] KSO17 KSO16/GPIO48 CIR_RLC_TX/GPIO41 +3VALW

82 89 FSTCHG <36>
KSO1 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 CHARGE_LED0#
90 CHARGE_LED0# <32>
+3VALW BATT_CHGI_LED#/GPIO52 CAPS_LED#
91 CAPS_LED# <30>
1
KSO2 EC_SMB_CK1 CAPS_LED#/GPIO53 CHARGE_LED1#
<35> EC_SMB_CK1 77
SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54
92 CHARGE_LED1# <32>
EC_SMB_DA1 78 93
<35> EC_SMB_DA1
2
EC_SMB_CK2 SDA1/GPIO45 SUSP_LED#/GPIO55 SYSON @ R36

<4> EC_SMB_CK2 79
SCL2/GPIO46 SM Bus SYSON/GPIO56
95 SYSON <31,39>
R69 EC_SMB_DA2 80 121 10K_0402_5%
<4> EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <40>
10K_0402_5% 127 ACIN
ACIN <19,36>
2
AC_IN/GPIO59 EC_RSMRST#
1
0_0402_5% 1 R95 2 S3# 6 100 EC_RSMRST#

<19> SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# <19>
0_0402_5% 1 R96 2 S5# 14 101 EC_LID_OUT#
<19> SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# <19>
EC_SMI# 15 102 EC_ON
<19> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON <30,37>
1 2 LID_SW# 16 103 0_0402_5% +3VALW
<24> LAN_WAKE# <32> LID_SW# LID_SW#/GPIO0A EC_SWI#/GPXO06
R70 0_0402_5% 17 104 ICH_POK_EC 1 2ICH_POK
SUSP#/GPIO0B ICH_PWROK/GPXO06 ICH_POK <8,19>
18 GPO 105 BKOFF# R76
PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# <22>
1 2 EC_PME# 19 GPIO 106 1 2 +3VS
EC_PME#/GPIO0D WL_OFF#/GPXO09 WL_OFF# <23>
R71 @ 0_0402_5% 25 107 R77 4.7K_0402_5% USB_ON# R66 1 2 10K_0402_5%
<32> KILL_SW# EC_THERM#/GPIO11 GPXO10 DDR3_SM_PWROK <8> @
FAN_SPEED1 28 108
FAN_SPEED1/FANFB1/GPIO14 GPXO11
S
3 1 29 EN_WOL# 1 2
<17> PCI_PME# <19,32> ODD_DA# FANFB2/GPIO15
EC_TX_P80_DATA 30 R104 @ 10K_0402_5%
<23> EC_TX_P80_DATA EC_TX/GPIO16
@ Q19 EC_RX_P80_CLK 31 110 S4# 1 R93 2 0_0402_5% SLP_S4# <19>
<23> EC_RX_P80_CLK EC_RX/GPIO17 PM_SLP_S4#/GPXID1 ENBKL
G
32 112
2N7002H_SOT23-3 <30> ON/OFF# ENBKL <10> change to 'L' active
2
+3VALW ON_OFF/GPIO18 ENBKL/GPXID2 EAPD

<30,32> PWR_LED# 34 114 EAPD <26>
NUM_LED# PWR_LED#/GPIO19 GPXID3 EC_THERM#
<30> NUM_LED# 36
NUMLED#/GPIO1A GPI GPXID4
115 EC_THERM# <19>
116 SUSP#
GPXID5 SUSP# <31,38>
117 PBTN# 1 R94 2 0_0402_5%
GPXID6 PBTN_OUT# <19>
118 BT_OFF# <30>
XCLKI GPXID7
122
+3VALW XCLKO XCLK1
123 124
XCLK0 V18R
1 1
AGND
1 2 FRD#SPI_SO C529 @
GND
GND
GND
GND
GND
R99 @ 100K_0402_1% 4.7U_0603_6.3V6K C927
+3VALW 1U_0603_10V4Z
1 2 FSEL#SPICS# KB926QFE0_LQFP128 2 2
FAN1 Conn
11
24
35
94
113
69
R86 @ 100K_0402_1% 1 2 LID_SW# U46
R85 @ 100K_0402_1%
+3VS
ECAGND
E0 version SUSP#
+5VS
SA00001J5A0 1
@
2
+5VALW C530
SPI_CLK_R 1000P_0402_50V7K R68 2
1 2 EC_SMB_CK1 2 10K_0402_5%
1
R84 4.7K_0402_5% C490

10U_0805_10V4Z
1
EC_SMB_DA1 R227 1 JFAN1
1 2
R236 4.7K_0402_5% Change D46 from SJ100001U00 to SJ132P7KW10 0_0402_5% Add C388 for noise 1
FAN_SPEED1 1
1 R619 2 0_0402_5% TACH_R 2
2
EC_FAN_PWM FAN_PWM_R 2
C532 1 1 2 3
R620 0_0402_5% 3
4
XCLKO C531 VR_ON 4
5
10P_0402_50V8J G5
1 6
2 G6
+3VS 15P_0402_50V8J C388 ACES_85205-04001
X1 1000P_0402_50V7K ME@
1
4 3 2
R237 OSC NC
For SED Team
2
20M_0603_5% 1 2
R234 R235 OSC NC
@
2.2K_0402_5% 2.2K_0402_5%
2
32.768KHZ_12.5PF_Q13MC14610002
Close PR131.1
C535
1
EC_SMB_CK2
EC_SMB_DA2 XCLKI
1 1
@ @
C533
100P_0402_50V8J
C534
100P_0402_50V8J
15P_0402_50V8J Security Classification Compal Secret Data Compal Electronics, Inc.
2 2
EC / FAN Conn
Custom 1.0
LA7012P
SPI Flash (16Mb*1) FOR EC 16M SPI ROM FOR EC 256K SPI ROM (NONShare ROM)
Change U31 P/N from SA00000XT00 to SA000041N00 0915 2010/09/24 Add U23 for NONShare SPI ROM.
+3VALW Change U31 footprint from WIESO_G6179-100000_8P to
20mils MX25L1606EM2I-12G_SO8 0920
1
U31 LPC@
C1170 8 4 +3VALW
0.1U_0402_16V4Z VCC VSS
2 2 1 SPI_W# 3
R921 0_0402_5% W U23 SPI@
2 1SPI_HOLD# 7 HOLD
SPI_CS# 1
CE# VDD 8
R922 0_0402_5% SPI_W# 3 6 SPI_CLK_R
SPI_CS# SPI_HOLD# 7 WP# SCK SPI_SI
<27> SPI_CS# 1 S HOLD# SI 5
4 2 SPI_SO
SPI_CLK_R VSS SO
6 C
<27> SPI_CLK_R W25X20BVSNIG SOIC 8P
SPI_SI 5 2 SPI_SO 2 1 FRD#SPI_SO FRD#SPI_SO <27>
<27> SPI_SI D Q R816 0_0402_5%
MX25L1606EM2I-12G_SO8
SA00003GM10
256kB(NAU00 2nd)
+5VALW +5VALW +5VS +5VS +5VS +3VALW +3VS +3VS
1 1 1 1 1 1 1 1
C122 C124 C128 C130 C131 C132 C133 C147
SATA HDD Conn. 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
JHDD1 2 2 2 2 2 2 2 2
10/11 Change JHDD1 P/N from SP01000QT00 to SP01000FX00
C441 1 2 0.01U_0402_16V7K SATA_ITX_DRX_P0

1
2
GND Near H1 Near H7 Near H3 Near H2 Near H6 Near H22 Near H4 Near H16
<18> SATA_ITX_C_DRX_P0 A+
<18> SATA_ITX_C_DRX_N0 C442 1 2 0.01U_0402_16V7K SATA_ITX_DRX_N0 3 A-
4 GND
C444 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N0 5
<18> SATA_DTX_C_IRX_N0 C445 1 SATA_DTX_IRX_P0 B- +5VS +3VS +3VS
2 0.01U_0402_16V7K 6 B+
<18> SATA_DTX_C_IRX_P0
7 GND A:H_2P8
+3VS
1 1 1
H1 H2 H3 H4 H5 H6 C150 C149 C148
8 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA H_4P2 D:H_3P8 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VCC3.3
1 9 VCC3.3
C121 @ 10 2 2 2
0.1U_0402_16V4Z VCC3.3 H18 H15
11
1
1
GND HOLEA HOLEA
2
12
13
GND Near H6 Near H6 Near C147
+5VS GND
14 VCC5
R749 15 H7 H8 H9
1
+5VS_HDD VCC5 HOLEA HOLEA HOLEA
1 2 16 VCC5
1 1 1 0_0805_5% 17 J:H_2P8 X1 I:H_3P0N X1
GND BOTTOM SIDE
18 RESERVED
C125 C123 19 VGA FD1 FD2 H16 H10
1
1
1000P_0402_50V7K 10U_0805_10V4Z GND HOLEA HOLEA
20 VCC12 1 1
2 2 2
21 VCC12
C126 22
0.1U_0402_16V4Z VCC12 FD3 FD4
3P2 X1
1
SUYIN_127043FB022G208ZR_RV H17
H_4P2 H23
1 1
ME@ HOLEA H19 H20 HOLEA

H11 H12 HOLEA HOLEA H_3P0X4P0N H_4P5X3P0N H_6P0N
HOLEA HOLEA
H24 H21 H22
1
1
HOLEA HOLEA HOLEA
1
1
BOTTOM SIDE BOTTOM SIDE

FAN WLAN
1
HDD / SPI ROM / Hold
B 1.0
LA7012P
A B C D E
+USB_VCCA
W=80mils JUSB1 ME@
+USB_VCCA 1
USB20_N0_R 1
PVT Change U19 and U27 part number from SA000039E00 to SA00002XX00 1 <19> USB20_N0 2 R914 1 0_0402_5% 2 2
1 2 R912 1 0_0402_5% USB20_P0_R 3
+ <19> USB20_P0 3
C615 4
1
+5VALW
220U_6.3V_M C715
470P_0402_50V7K
5
4
G5
Right USB Conn. 1
6 G6
2
2 2 D25
@ ACES_85205-04001
WCM-2012-900T_4P
PJDLC05_SOT23-3
+USB_VCCA USB20_N0 4 3 USB20_N0_R
U19 4 3
1 GND VOUT 8 RIGHT USB PORT X1
C421 0.1U_0402_16V4Z 2 7 USB20_P0 1 2 USB20_P0_R
VIN VOUT 1 2
2 1 3 VIN VOUT 6
USB_ON# 4 5 L66 @
<27> USB_ON# USB_OC#0 <19>
1
EN FLG
RT9715BGS_SO8
1
C429
@ 1000P_0402_50V7K
2 +USB_VCCB
W=80mils JUSB2
+USB_VCCB 1
USB20_N1_R 1
1 <19> USB20_N1 2 R918 1 0_0402_5% 2 2
1 2 R913 1 0_0402_5% USB20_P1_R 3
2
+ <19> USB20_P1 3 2
C430 4
220U_6.3V_M C432
470P_0402_50V7K
5
4
GND
Left USB Conn.
6 GND
2 2 7 GND
8 GND
D47
@ SUYIN_020173MR004S558ZL
2
PJDLC05_SOT23-3
L63 @ ME@
USB20_N1 4 3 USB20_N1_R
+5VALW 4 3
+USB_VCCB USB20_P1 1 2 USB20_P1_R

1 2
LEFT USB PORT x2 WCM-2012-900T_4P
U27
1 8
1
GND VOUT
2 VIN VOUT 7
3 VIN VOUT 6
USB_ON# 4 5
EN FLG USB_OC#1_7 <19>
1
RT9715BGS_SO8 1
C621
0.1U_0402_16V4Z
C610
@ 1000P_0402_50V7K
Change JUSB3 connector from ESATA to USB Left2 USB Conn.
2 +USB_VCCB
3 3
2 JUSB3
+USB_VCCB
W=80mils
1 1
1 2 R924 1 0_0402_5% USB20_N7_R 2
<19> USB20_N7 2
1 2 R923 1 0_0402_5% USB20_P7_R 3
+ <19> USB20_P7 3
C623 C622 4
220U_6.3V_M 470P_0402_50V7K 4
5 GND
6 GND
2 2 7 GND
8
Pre MP ADD for ESD solution GND
SUYIN_020173MR004S558ZL
2
PJDLC05_SOT23-3
+5VALW +USB_VCCB ME@
D10
Near D10 Near C622 L64 @ @
USB20_N7 4 3 USB20_N7_R
4 3
1 1
C661 C660 USB20_P7 1 2 USB20_P7_R
1 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 WCM-2012-900T_4P
1
4 4

USB ports/BT
B 1.0
LA7012P
A B C D E
ON/OFF switch Power Bottom Board Conn. 8pin NOVO_BTN#
ON/OFFBTN# NUM_LED#
2
+5VALW +5VS CAPS_LED#
D19
SW1 PJSOT24C 3P C/A SOT-23 PWR_LED#
0.1U_0402_16V4Z
JPWRB2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 3
Power Button 2 4
1
2
1 1
C357
1
C358
1
C359
<27> NUM_LED#
1
SMT1-05_4P 2
<27> CAPS_LED# 3 3
4
6
5
@ +3VALW NOVO_BTN# 4 2 2 2
5 5
ON/OFFBTN#
TOP Side J5
PWR_LED#
6
7
6 EMI REQUEST 1ST = SCA00000E00
<27,32> PWR_LED# 7
2
@1 2 8
9
8 2ST = SCA00000R00
SHORT PADS R272 GND
Bottom Side 100K_0402_5%
10 GND
D14
ACES_85201-08051
1
3 ON/OFF# ME@
ON/OFF# <27>
ON/OFFBTN# 1
2 51_ON#
1
DAN202UT106_SC70-3 2 PVT ESD solution.
C356 D15
@ @ +5VALW NUM_LED# +5VS +5VALW
1000P_0402_50V7K RLZ20A_LL34 PWR_LED# CAPS_LED# NOVO_BTN#
1
D 1 ON/OFFBTN#
2
EC_ON 2 +5VS
<27,37> EC_ON
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
G Q28
S 2N7002H_SOT23-3 D49 D50 D51 1 1 1 1
3
2
AZ5125-02S.R7G_SOT23-3 AZ5125-02S.R7G_SOT23-3 AZ5125-02S.R7G_SOT23-3 C360 C364 C365 C366

R302
10K_0402_5% 2 2 2 2
1
1
+3VALW Card Reader/Audio Jack SB CONN JCR1

<26> PLUG_IN PLUG_IN 1 1
2
HP_OUTR 2
<26> HP_OUTR 2
R296 HP_OUTL 3
+5VALW <26> HP_OUTL 3
100K_0402_5% 4
BT MODULE CONN D44
<26> MIC_JD MIC_JD
EXT_MIC_L
5
4
5
<26> EXT_MIC_L 6
1
6
1
NOVO# 2 EXT_MIC_R 7
<27> NOVO# <26> EXT_MIC_R 7
BT@ 1 NOVO_BTN# 8
R304 BT@ 51_ON# +3VS 8
<34> 51_ON# 3 CardReader 9 9
100K_0402_5% 2 R926 1 0_0402_5% USB20_P4_R 10
C353 <19> USB20_P4 10
0.1U_0402_16V4Z 2 R925 1 0_0402_5% USB20_N4_R 11 13
<19> USB20_N4
2
DAN202UT106_SC70-3 11 GND
1 R616 2 1 2 12 12 GND 14
100K_0402_5%
1
BT@ L65 @
USB20_N4 4 3USB20_N4_R ACES_85201-1205N
OUT
4 3
+3VS +3VS_BT
2 BT@ R583 USB20_P4 1 2USB20_P4_R ME@
<27> BT_OFF# IN 1 2
Q31 0_0603_5% 30mils
GND
DTC124EKAT146_SC59-3 3 1+3VS_BT_R 1 2 WCM-2012-900T_4P

1
BT@ C354
3
EXT_MIC_R
EXT_MIC_L
BT@
HP_OUTR
HP_OUTL
PLUG_IN
Q32 0.1U_0402_16V4Z
MIC_JD
2
BT@ BT@ 2
<32> BT_LED#
Q29 AP2301GN-HF_SOT23-3 JBT1 ME@
1
DTC124EKAT146_SC59-3 1 1
2 2
OUT
2
<19> USB20_P6 USB20_P6 3 3
<19> USB20_N6 USB20_N6 4 4 D7 D8 D9
2 BTON_LED 5 5 G1 7 PESD5V0U2BT 3P PESD5V0U2BT 3P PESD5V0U2BT 3P
IN BT_ACTIVE @ @
<23> BT_ACTIVE 6 6 G2 8
GND
ACES_87213-0600G
1
3
Security Classification Compal Secret Data Compal Electronics,Ltd.

Audio Jack & SW & BT Conn.
B 1.0
LA7012P
A B C D E
+VSB
+VSB
+5VALW TO +5VS +3VALW TO +3VS
1
R229
10K_0402_5% Change U10 from SB548000320 to SB000009510 Change U14 from SB548000320 to SB000009510
R89
47K_0402_5%
2
5VS_GATE 2 R228 1 5VS_GATE_R
2
10K_0402_5% 1 3VS_GATE 2 1 3VS_GATE_R
1
D R88 0_0402_5% 1
1
1 D 1
SUSP 2 Q20 C278
G 2N7002H_SOT23-3 0.1U_0603_25V7K SUSP 2 Q46 C144
S 2 G 2N7002H_SOT23-3 0.1U_0603_25V7K
3
S 2
3
+5VALW
4
+5VS
5
1 6 3
7 2 1 1 +3VALW +3VS
4
1
C279 8 1
10U_0805_10V4Z C277 C276 5
2 10U_0805_10V4Z 1U_0603_10V4Z R202 6 3
U10 1
2 2 470_0603_5% 7 2 1 1
1
AO4468L_SO8 @ C127 8 1
1 2
10U_0805_10V4Z C134 C135
D 2 10U_0805_10V4Z 1U_0603_10V4Z R87
U4 2 2 470_0603_5%
2 SUSP
G AO4468L_SO8 @
1 2
S Q16
3
D
2N7002H_SOT23-3
@ 2 SUSP
G
S Q6
3
2N7002H_SOT23-3
@
2 2
+1.8VS +1.5V +1.05VS +0.75VS

1
R142 R342 R143 R568

470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5%
@ @ @ @
1 2
1 2
1 2
1 2
D D D D +VSB
G
2 SUSP
G
2 SYSON#
G
2 SUSP
G
2 SUSP +1.5V to +1.5VS
1
S Q10 S Q35 S Q11 S Q40 Change U16 from SB548000320 to SB000009510
3
2N7002H_SOT23-3 2N7002H_SOT23-3 2N7002H_SOT23-3 2N7002H_SOT23-3

100K_0402_5%
@ @ @ @
R312
2
1.5VS_GATE 2 1 1.5VS_GATE_R
Q33 R313 0_0402_5% 1 1
1
D
SUSP 2 C373 C361
G @ 0.1U_0603_25V7K
Pre MP Change SUSP pull high from +5VALW to +3VLP. 2N7002H_SOT23-3
S 2 2
3
0.1U_0603_25V7K
3 +3VLP +5VALW PVT Change R5 from 100K to 10K. 3
+5VALW
1
@
1
R5 +1.5V +1.5VS
4
R4 10K_0402_5% @
100K_0402_5% R6 5
100K_0402_5% 1 6 3
2
SUSP 7 2 1 1
2
<39> SUSP
1
SYSON# C389 8 1
Q45 Q2 10U_0805_10V4Z C362 C363
1
DTC124EKAT146_SC59-3 DTC124EKAT146_SC59-3 2 10U_0805_10V4Z 1U_0603_10V4Z R314

@ U16 2 2 470_0603_5%
OUT
OUT
AO4468L_SO8 @
2
2 SYSON 2
<27,38> SUSP# IN <27,39> SYSON IN
1
D
GND
GND
2 SUSP
G
S Q34
3
3
2N7002H_SOT23-3
@
4 4

DC Interface
Custom 1.0
LA7012P
A B C D E
5 4 3 2 1
INT_KBD Conn.
Lid Switch Kill Switch
+3VALW KSI[0..7] JKB1
R615
STATUS <27> KSI[0..7]
1
KSO[0..17] 1
R614 100K_0402_5% 2
1 2 +VCC_LID 1 2
1,2(LOW) OFF <27> KSO[0..17]
3
2
100P_0402_50V8J C721 KSO0 3
2 1 4
0_0402_5%
2,3(HI) ON 100P_0402_50V8J 2 1 C722 KSO1 KSO17 5
4
100P_0402_50V8J C723 KSO2 KSO16 5
2 1 6 6
2
D 100P_0402_50V8J C724 KSO3 KSO15 D
+3VALW 2 1 7 7
R617 100P_0402_50V8J 2 1 C725 KSO4 KSO10 8
VDD
100P_0402_50V8J C726 KSO5 KSO11 8
1 100K_0402_5% SW2 2 1 9 9
2 1 3 100P_0402_50V8J 2 1 C727 KSO6 KSO14 10
3 100P_0402_50V8J C728 KSO7 KSO13 10
C694 3 2 2 1 11 11
OUTPUT LID_SW# <27> 100P_0402_50V8J C729 KSO8 KSO12
0.1U_0402_16V4Z 2 2 1 12 12
2 C695 <27> KILL_SW# 2 100P_0402_50V8J 2 1 C730 KSO9 KSO3 13
GND
100P_0402_50V8J C731 KSO10 KSO6 13
10P_0402_50V8J 2 1 14 14
1 1 100P_0402_50V8J 2 1 C732 KSO11 KSO8 15
1 100P_0402_50V8J C733 KSO12 KSO7 15
U32 2 1 16 16
1
S-5711ACDL-M3T1S_SOT23-3 100P_0402_50V8J 2 1 C734 KSO13 KSO4 17
100P_0402_50V8J C735 KSO14 KSO2 17
LSSM12-P-V-T-R_3P 2 1 18 18
100P_0402_50V8J 2 1 C736 KSO15 KSI0 19
100P_0402_50V8J C747 KSO16 KSO1 19
2 1 20 20
100P_0402_50V8J 2 1 C746 KSO17 KSO5 21
KSI3 21
22 22
KSI2 23
PVT Change U32 part number from SA032120010 to SA000031C00 KSO0 24
23
KSI5 24
25
LED KSI4
KSO9
26
27
25
26
100P_0402_50V8J C737 KSI0 KSI6 27
LED1 2 1 28 28
100P_0402_50V8J 2 1 C738 KSI1 KSI7 29 31
White LED1_5V 100P_0402_50V8J 2 1 C739 KSI2 KSI1 30
29 G1
32
<27,30> PWR_LED# 1 2 2 1 +5VALW 30 G2
300_0402_5% R622 100P_0402_50V8J 2 1 C740 KSI3
100P_0402_50V8J 2 1 C741 KSI4 ACES_85201-3005N
19-213A-T1D-CP2Q2HY-3T_WHITE 100P_0402_50V8J 2 1 C742 KSI5 ME@
100P_0402_50V8J 2 1 C743 KSI6
LED2 100P_0402_50V8J 2 1 C744 KSI7
Orange
C
BATT_LOW_LED# 1 2 LED2_3V 2 1 Reserve for ESD.
C
<27> CHARGE_LED1# +3VALW
O 300_0402_5% R623
<27> CHARGE_LED0# 3 4 LED2_5V 2 1 +5VALW

W
White
BATT_CHG_LED# 470_0402_5% R624
check connector & pin define.
18-225A-S2T3D-C01-3T_ORG-WHITE
D22 LED3
White LED3_5V
<23> WLAN_LED# 1 2 1 2 2 1 +5VS
300_0402_5% R627
RB751V_SOD323 CONN PIN define need double check
19-213A-T1D-CP2Q2HY-3T_WHITE
D23
+5VS
To TP/B Conn.
<30> BT_LED# 1 2
RB751V_SOD323 Add for ESD solution.
C701 TP_CLK
LED4 TP_DATA
White 0.1U_0402_16V4Z
<18> HDD_LED# 1 2 LED4_5V 2 1 +5VS JTP1
2
300_0402_5% R628 4
TP_CLK 4 D48
<27> TP_CLK 3 3
19-213A-T1D-CP2Q2HY-3T_WHITE TP_DATA 2 PESD5V2S2UT_SOT23-3
<27> TP_DATA 2
1 1 1 1
@ @
B B
C699 C700 E&T_6905-E04N-00R
1
100P_0402_50V8J 100P_0402_50V8J ME@
2 2
ODD Power Control
11/05 Add this function.
@ J9
1 1 2 2
+5VS JUMP_43X79 +5VS_ODD
JODD1
3 1
@
SATA ODD Conn.
1 1 GND
1
Q99 <18> SATA_ITX_C_DRX_P1 C428 1 2 0.01U_0402_16V7K SATA_ITX_DRX_P1 2

C612 C431 1 A+
<18> SATA_ITX_C_DRX_N1 2 0.01U_0402_16V7K SATA_ITX_DRX_N1 3 A-
@ R552 AP2301GN-HF_SOT23-3 0.1U_0402_16V4Z 4
2
2 GND
10K_0402_5%
C613 <18> SATA_DTX_C_IRX_N1
C437 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N1 5 B-
R677 @ @ 0.01U_0402_16V7K 1 C439 1 2 0.01U_0402_16V7K SATA_DTX_IRX_P1 6
2
<18> SATA_DTX_C_IRX_P1 B+
1 2 1 2 7 GND
C611 +5VS_ODD
1
100K_0402_5% 10U_0805_10V4Z @R717

@ R717
2 1 2 0_0402_5% ODD_DETECT# 8
OUT
DP
9 +5V
R554 @ 10 17
ODD_DA# +5V GND
<19> ODD_EN 2 IN <19,27> ODD_DA# 1 2 0_0402_5% 11 MD GND 16
@ 12
GND
R555 @ GND
13 GND
A Q100 +3VS 1 2 A
DTC124EKAT146_SC59-3 10K_0402_5%
3
OCTEK_SLS-13SB1G_RV
ME@

KB/TP/LID/KLL/ODD/LED FOR 14
Custom 1.0
LA7012P
5 4 3 2 1
5 4 3 2 1
9HUVLRQFKDQJHOLVW3,5/LVW 3DJHRIIRU+:

,WHP )L[HG,VVXH 5HDVRQIRUFKDQJH 5HY 3* 0RGLI\/LVW 'DWH 3KDVH

D D

C
C

B B

A
A

HW PIR
Custom 1.0
LA7012P
5 4 3 2 1
5 4 3 2 1
DC030006J00 VIN
Precharge detector
PF1 PL1 15.97V/14.84V FOR
4 APDIN
7A_24VDC_429007.WRML
1 2 APDIN1
SMB3025500YA_2P
1 2
ADAPTOR
4
3
3
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
2
D 2 D
1
1
1 PreCHG PQ1
TP0610K-T1-E3_SOT23-3
2
@ 4602-Q04C-09R 4P P2.5
PC122
PC1
PC2
PC123
PC3
PC4
PR1
JDCIN1 1K_1206_5% PD1
1 2 2 1 3 1
VIN
PR2 LL4148_LL34-2 @
1K_1206_5% @
1 2
100K_0402_1%
1
1
100K_0402_1%
PR3
PR4
PR5
1K_1206_5%
2
1 2
PR6
2
1K_1206_5%
1 2
VIN
100K_0402_1%
1
PD2
PR7
LL4148_LL34-2
1
PQ2
1
PD3 PD4 PDTC115EU_SOT323-3
1 2
LL4148_LL34-2 2
2 1 <27,36> ACOFF 1 2
BATT+
1
3 PQ3
PR8 PR9 <20,22,27,28,29,30,31,32,37,38,39> +5VALW PDTC115EU_SOT323-3
68_1206_5% 68_1206_5% RB715F_SOT323-3
C PQ4 VS 2 C
3
TP0610K-T1-E3_SOT23-3
2
2
N1 3 1
0.22U_0603_25V7K
3
1
PR10 PC6
PC5
100K_0402_1% 0.1U_0603_25V7K
B+
2
PR11
2
22K_0402_1% PR12
1 2 2.2M_0402_5%
<30> 51_ON#
2 1
VL
VS
499K_0402_1%
1
0.01U_0402_25V7K
PR13
1
1
PC7
PR14
100K_0402_1%
2
@
2
<35,37> MAINPWON
8
PD5 PU1A
2 LM393DG_SO8 3
P
+
1 1 O
205K_0402_1%
499K_0402_1%
0.01U_0402_25V7K
3 2
G
-
1
+RTCBATT
- +
1
1000P_0402_50V7K
PR15
PR16
PC10
JRTC1 PR17 PR18 <36> ACON @ RB715F_SOT323-3
4
1
1
560_0603_5% 560_0603_5%
PC9
B +RTCBATT PC8 B
2 1 1 2 1 2 +CHGRTC
2
0.1U_0603_25V7K
PRG++ 2
2
ML1220T13RE
45@
2N7002W-T/R7_SOT323-3
1 2 PR19 PR20
+3VLP <36> PACIN
1
34K_0402_1% D PQ5 47K_0402_1%
2 1 2 2 1
PD6 6251VREF G
1
RB751V-40_SOD323-2 S
3
PQ6
2
PDTC115EU_SOT323-3
PR21
2
66.5K_0402_1%
+5VALW
3
ACIN BATT ONLY
Precharge detector Precharge detector
Min. typ. Max. Min. typ. Max.
A L-->H 14.991V 15.381V 15.782V L-->H 7.196V 7.349V 7.505V A
H-->L 13.860V 14.247V 14.621V H-->L 6.138V 6.214V 6.056V

DCIN / Vin Detector /Pre-charge
Custom 1.0
5 4 3 2 1
5 4 3 2 1
PH1 under CPU botten side :

VMB2 VMB
CPU thermal protection at 92 degree C
PF2 PL2
JBATT1 12A_65V_451012MRL SMB3025500YA_2P
Recovery at 56 degree C
1 1 1 2 1 2 BATT+
2
2 EC_SMCA
3
3 EC_SMDA
4
D 4 D
5
5
1
6
6 PC11 PC12
7
7 1000P_0402_50V7K 0.01U_0402_25V7K VL
8
2
GND
9
GND
TYCO_1775789-1 VL
@
2
PC13 PR24 PR25
0.1U_0603_25V7K 10K_0402_1% 21.5K_0402_1% PR26
2
PR23 @ 100K_0402_1%
2
100_0402_1% PU2
1
1 2 EC_SMB_CK1 <27> 1 VCC TMSNS1 8
2
2 GND RHYST1 7
1 2 PR27
EC_SMB_DA1 <27>
3 6 9.76K_0402_1%
PR22 OT1 TMSNS2
100_0402_1%
@ 47K_0402_1%
1 2 +3VALW 4 5
1
OT2 RHYST2
2
PR28
1
PR29
6.49K_0402_1% G718TM1U_SOT23-8
PH1
100K_0402_1%_TSM0B104F4251RZ
1 2 A/D
1
BATT_TEMP <27>
PR30
2
10K_0402_1%
MAINPWON <34,37>
3
1
PD15
PD16 PH2
C @ 100K_0402_1%_TSM0B104F4251RZ C
@ PJSOT24C @ PJSOT24C
2
1
VS
+3VALW +3VS
0.01U_0402_25V7K
1
PC14
VMB2
PR31 PR32
2
100K_0402_1% 10K_0402_1%
PR33 PR34
2
649K_0402_1% 5.1M_0402_5%
1
1 2 BATT_OUT <36>
2N7002W-T/R7_SOT323-3
PQ8
PR35 TP0610K-T1-E3_SOT23-3
8
10K_0402_1%
1
D
1 2 5
P
+
7 2 B+ 3 1 +VSBP
O
PQ7
PR36 6 G
-
G
2
100K_0402_1%
0.22U_0603_25V7K
232K_0402_1% PU1B S
3
1
LM393DG_SO8
4
1
PR37
PC15
B B
PC16
PQ44 0.1U_0603_25V7K
1
2
1
D 2N7002W-T/R7_SOT323-3
2
2 1 2 PR39
6251VREF <27> BATT_LEN# VL
G 22K_0402_1%
PR38 S 1 2
3
10K_0402_1%
2
PR40
100K_0402_1%
PR41
1
1
1K_0402_1% D PJ1
1 2 2 PQ9 @ JUMP_43X39
<19,37> SPOK
G 2N7002W-T/R7_SOT323-3 1 1
+VSBP 2 2 +VSB
1U_0402_6.3V6K
S
3
1
PC17
2
A A

BATTERY CONN/OTP
Custom 1.0
5 4 3 2 1
5 4 3 2 1
P3
B+
P2
PQ10 PQ11
AO4407A_SO8 AO4409_SO8
8 1 1 8 PR42
VIN 7 2 2 7 0.02_1206_1% PL11 CHG_B+
6 3 3 6 1.2UH_1231AS-H-1R2N=P3_2.9A_30%
5 5 1 4 1 2 PQ12
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
AO4407A_SO8
0.1U_0402_25Y5V
2 3 1 8
1
PC126
PC127
PC128
PC137
2 7
3 6
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
5
2
47K_0402_1%
D D
1
2
200K_0402_1%
0.1U_0603_25V7K
PC20
4
1
PR43
PC18
PC22
PC19
DISCHG_G
PC21
PR44
PQ13 CSIN
1
2
PDTA144EU PC131 CSIP PR45
5600p_0402_25V7K 47K_0402_1%
VIN PreCHG
2
2
2 1 2
1
VIN
2 ACOFF-1
191K_0402_1%
2
1
1
PR47 PR48
1DISCHG_G-1
PR46
PQ14 191K_0402_1% 10K_0402_1%
1
2
PDTC115EU_SOT323-3 @ PD8
PR49
1
BATT_ON 2 P2-1 PD7 1SS355_SOD323-2 200K_0402_1%
2
RB751V-40_SOD323-2 ACSETIN
1000P_0402_50V7K
1 1
1
1
PR50 PQ15
1
0_0402_5% 6251_VDD PR52 PDTC115EU_SOT323-3 PD9
3
2.2U_0603_10V7K
2 1 PR51 14.3K_0402_1% 1SS355_SOD323-2
<27> FSTCHG
1
10_1206_5% 2 1 2
2
6
1
PC24
PC23
2
1
2200P_0402_50V7K
150K_0402_1%
PR53
2
100K_0402_1%
PR54
PQ16A 10K_0402_1% PU3 PC25 PQ18
1
PC26
2 2N7002KDW-2N_SOT363-6 0.1U_0603_25V7K 2N7002W-T/R7_SOT323-3
12
1
D D
PR55
0.1U_0603_25V7K
1 24 6251_DCIN
2 1
VDD DCIN
100K_0402_1%
2 BATT_OUT 2 PACIN
1
1
PC27
G @ G
1
PR56
ACSETIN ACPRN @
BATT_ON
S 2 23 S
3
3
ACSET ACPRN
2N7002W-T/R7_SOT323-3
PQ17 PR57
2
P2-2
2N7002W-T/R7_SOT323-3 20_0402_5%
5
6
7
8
6251_EN 3 22 6251_CSON 1 2 CSON
EN CSON
1
D
PQ19
AO4466L_SO8
C PC28 C
3
PQ20
0.047U_0402_16V7K ACPRN 2
PR59 CELLS 4 21 6251_CSOP 1 2 CSOP G
2
47K_0402_1% PQ16B CELLS CSOP PR58 S
3
PACIN 1 2 5 2N7002KDW-2N_SOT363-6 PC29 6800P_0402_25V7K 20_0402_5% 4 @
<34> PACIN 6251_ICOMP 6251_CSIN
1 2 5 ICOMP CSIN 20 2 1
2
PC31 PR60
4
PC30 PR61 10K_0402_1% 0.1U_0402_16V7K 20_0402_5%

<34> ACON
1 2 6251_VCOMP-1
1 2 6251_VCOMP 6 19 6251_CSIP 1 2 PL3 PR64 BATT+
3
2
1
VCOMP CSIP
1
PR62 10U_LF919AS-100M-P3_4.5A_20% 0.02_1206_1%

PQ21 0.01U_0402_25V7K 2_0402_5%
PDTC115EU_SOT323-3 1 2 6251_ICM 7 18 LX_CHG 1 2 CHG
1 4
PR63 ICM PHASE
5
6
7
8
1 2 ACOFF-12 <27> ADP_I 100_0402_1% 2 3
<27,34> ACOFF
1
AO4466L_SO8
PQ22
4.7_1206_5%
8 17 DH_CHG
VREF UGATE
2
10U_0805_25V6K
10U_0805_25V6K
PR67
PR65 PR68 1 2 6251VREF PR69 PC33
10U_0805_25V6K
10K_0402_1% PR66 154K_0402_1% PC32 0_0603_5% 0.1U_0603_25V7K
10U_0805_25V6K
1 6251_SN
0_0402_5% 2 1 0.1U_0402_16V7K 6251_CHLIM 9 16 BST_CHG 1 2 BST_CHGA 2 1
3
<27> IREF CHLIM BOOT
1
PC35
PC36
PR70 PD10 4
PC130
0.01U_0402_25V7K
21K_0402_1%
1
PC34
1 2 6251_ACLIM 10 15 6251_VDDP
2
ACLIM VDDP
1
6251VREF RB751V-40_SOD323-2
1
680P_0603_50V7K
PC37
PR71 1 2 6251_VDD
3
2
1
1
PC38
<35> BATT_OUT BATT_OUT 2 100K_0402_1% 6251_VADJ
11 14 DL_CHG
2
VADJ LGATE
1
G PR73 PR72
2
S 2.2K_0402_1% 4.7_0402_5%
3
PQ23 12 13 PC39
2
2N7002W-T/R7_SOT323-3 GND PGND 4.7U_0805_10V6K
2
ISL6251AHAZ-T_QSOP24
PR74
Connect to EC A/D Pin. 15.4K_0402_1%
B B
1 2
<27> CHGVADJ
1
PR75
CHGVADJ=(Vcell-4)/0.10627 31.6K_0402_1%
6251_VDD 6251_VDD
Vcell CHGVADJ
2
4cell : VDD
2
6251_VDD
4V 0V DIS CP mode (65W*85%)
PR76 PR77
4.2V 1.882V Vaclim=2.39*((2.2K//152K)/(2.2K//152K+21K//152K))=0.25136V PR80 3cell : GND @ 100K_0402_1% @ 100K_0402_1%
Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05) 10K_0402_1%
1
4.35V 3.2935V 1 2 ACIN <19,27>
1
where Vaclim=0.25136V, Iinput=2.76293A PR79 CELLS
PR78 10K_0402_1%
3
PR70=21K 47K_0402_1%
CC=0.25A~3A PACIN PR81
2
1 2
PR73=2.2K 0_0402_5%
IREF=1.016*Icharge 2 5 2 1
1
PR42=20mohm PQ25 PR82
2
IREF=0.254V~3.048V PDTC115EU_SOT323-3 @ 0_0402_5%
4
PR83 <27> BATT_SEL_EC
VCHLIM need over 95mV ACPRN 2
<37> ACPRN 14.3K_0402_1%
2
PQ24A PQ24B
@ 2N7002KDW-2N_SOT363-6 @ 2N7002KDW-2N_SOT363-6
3
A A

CHARGER
1.0
5 4 3 2 1
5 4 3 2 1
Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO
2VREF_8205 PJ3
+3VALWP 2 2 1 1 +3VALW
@ JUMP_43X118
1U_0603_10V6K
D D
1
PC40
PJ4
+5VALWP 2 1 +5VALW
2
2 1
@ JUMP_43X118
PR84 PR85
13K_0402_1% 30K_0402_1%
1 2 1 2
PR86 PR87
20K_0402_1% 20K_0402_1%
RT8205_B+ 1 2 1 2 RT8205_B+
Typ: 175mA PC119 PC120

PJ5 @ 2200P_0402_50V7K @ 2200P_0402_50V7K
B+ 2 1 +3VLP 1 2 1 2
2 1
ENTRIP1
ENTRIP2
2200P_0402_50V7K
2200P_0402_50V7K
1U_0603_25V6
0.1U_0603_25V7K
0.1U_0603_25V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
@ JUMP_43X118 PR88 PR89
110K_0402_1% 121K_0402_1%
PC41
PC49
4.7U_0805_10V6K
1 2 1 2
1
1
PC129
PC42
PC43
PC44
PC46
PC47
PC48
5
5
PU4
2
2
PC45
ENTRIP2
FB2
FB1
ENTRIP1
TONSEL
REF
1
25 P PAD
PQ26
2
C C
4 SIS412DN-T1-GE3_PAK1212-8 4
7 24
VO2 VO1 SPOK <19,35>
8 23 PR91 PC51 PQ27
PR90 VREG3 PGOOD 0_0603_5% 0.1U_0603_25V7K SIS412DN-T1-GE3_PAK1212-8
1
2
3
3
2
1
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2
0_0603_5% BOOT2 BOOT1
PL4 PC50 UG_3V 10
VFB=2.0V 21 UG_5V PL5
4.7UH_FMJ-0630T-4R7 HF_5.5A_20% 0.1U_0603_25V7K UGATE2 UGATE1 4.7UH_FMJ-0630T-4R7 HF_5.5A_20%
1 2 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP PHASE2 PHASE1
1
1
4.7_1206_5%
4.7_1206_5%
LG_3V 12 19 LG_5V
LGATE2 LGATE1
5
5
PR92
PR94
SKIPSEL
PR93 @
VREG5
0_0402_5%
GND
VIN
MAINPWON 2
NC
RT8205EGQW_WQFN24_4X4
EN
1 1 1
2
2
+ 4 4 + PC54
13
14
15
16
17
18
1
1
680P_0603_50V7K
680P_0603_50V7K
PC52 PR95 150U_B2_6.3VM_R45M
PC53
PC55
150U_B2_6.3VM_R45M 499K_0402_1%
2 1 2 2
2
2
B+
1
2
3
3
2
1
1
100K_0402_1%
1U_0603_10V6K
PQ28
VL
1
PC56
SI7716ADN-T1-GE3_PAK1212-8
1
PR96
PC57
4.7U_0805_10V6K
Typ: 175mA
2
ENTRIP1 ENTRIP2 PQ29
2
SI7716ADN-T1-GE3_PAK1212-8
RT8205_B+
6
1
PQ30B
0.1U_0603_25V7K
B PQ30A 2N7002KDW-2N_SOT363-6 B
2N7002KDW-2N_SOT363-6 2 5 2VREF_8205
2
PC58
<34,35> MAINPWON
1
PR97
0_0402_5%
2 1
PR98
100K_0402_1%
VL 2 1
1
2N7002W-T/R7_SOT323-3
PQ31
PR99 PDTC115EU_SOT323-3
1
200K_0402_1% D
PQ32
2 1 2 1 2 2
<36> ACPRN G VS
40.2K_0402_1%
2.2U_0603_10V7K
S PR100
3
100K_0402_1% TONSEL=VREF (1)SMPS1=300KHZ(+5VALWP)

1
1
PR101
PC59
(2)SMPS2=375KHZ(+3VALWP)
3
2
<27,30> EC_ON
2
2 PQ33
PDTC115EU_SOT323-3
A A
3

3VALWP/5VALWP
Custom 1.0
5 4 3 2 1
5 4 3 2 1
PJ6
1.1VALW_B+ 2 1
2 1 B+
1U_0603_25V6
4.7U_0805_25V6-K
4.7U_0805_25V6-K
@ JUMP_43X118
680P_0402_50V7K
680P_0402_50V7K
680P_0402_50V7K
0.1U_0402_25Y5V
1
1
PC132
PC133
PC134
PC135
PC124
PC60
PC61
5
6
7
8
2
D D
PR102 PQ34
255K_0402_1% 4 AO4406AL_SO8
1 2
PR103
PD13
150k_0402_1% PR104
1 2 1 2 1 2 +5VALW
3
2
1
<27,31> SUSP#
2.2_0603_5%
PJ7
@ 1SS355_SOD323-2
1
PL6
15
14
PC63 +VCCPP 2 1 +1.05VS
2 1
1
PC62 PU5 1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%
.1U_0402_16V7K BST_VCCP 1 2 1 2 @ JUMP_43X118
EN/DEM
BOOT
NC
+VCCPP
2 DH_VCCP 0.1U_0603_25V7K
2 TON UGATE 13
4.7_1206_5%
PR106 3 12 LX_VCCP
VOUT PHASE
5
6
7
8
PR105
100_0603_5% 1
220U_6.3V_M
+5VALW 1 2 4 11 1 2 +5VALW PQ35
VDD CS
PC64
PR107 AO4726L_SO8 +
2
5 10 11K_0402_1%
FB VDDP
1
1
6 9 DL_VCCP 4 2
PGOOD LGATE
PGND
680P_0603_50V7K
PC65
GND
PC66
4.7U_0603_6.3V6K
2
2
PC67
RT8209BGQW_WQFN14_3P5X3P5 4.7U_0805_10V6K
3
2
1
PR108
4.12K_0402_1%
C C
1 2
1
PR109
10K_0402_1%
2
B B
A A

VCCP
1.0
5 4 3 2 1
5 4 3 2 1
PJ8
1.5_51117_B+ 2 1
2 1 B+
5
6
7
8
1U_0603_25V6
4.7U_0805_25V6-K
4.7U_0805_25V6-K
@ JUMP_43X118
1
PC68
PC69
PC125
2
2
PR110 PQ36
255K_0402_1% 4 AO4406AL_SO8
PR111 1 2
0_0402_5%
<27,31> SYSON 1 2 1 2 1 2 +5VALW
3
2
1
PR113 PD14
2
47K_0402_1%
0_0603_5% PC71 PL7
PR112
D @ 1SS355_SOD323-2 0.1U_0603_25V7K 1.8UH_MSCDRI-104A-1R8N-E_9.5A_30% D
15
14
1
1
PU6 BST_1.5V-1 1 2 1 2 +1.5VP
PC70 @
EN/DEM
BOOT
NC
.1U_0402_16V7K
2
2 13 DH_1.5V
TON UGATE
1
3 12 LX_1.5V 1
VOUT PHASE
5
6
7
8
1U_0603_25V6
220U_6.3V_M
PR114
1
PC72
PC139
4 VFB=0.75V 11 +5VALW PQ37 4.7_1206_5% +
VDD CS AO4726L_SO8
5 10
2
FB VDDP 2
6 9 DL_1.5V 4
PGOOD LGATE
PGND
PR115
GND
1
11K_0402_1%
100_0603_5% PC74
PR116
+5VALW 1 2 PC73 680P_0603_50V7K
RT8209BGQW_WQFN14_3P5X3P5 4.7U_0805_10V6K
3
2
1
2
1
2
PC76
4.7U_0603_6.3V6K
2
PR117
10.2K_0402_1%
1 2
1
+1.5VP 1 2 1.5V_PGOOD <8> PJ9 +1.5V
+1.5VP 2 1
2 1
1
PR118 PR165
10K_0402_1% 100K_0402_1% PC121 @ JUMP_43X118
@0.1U_0402_16V7K +1.5V
2
2
C C
2
PJ10
2
JUMP_43X79
@
1
1
PU7
1
VIN VCNTL
6 +3VALW
.1U_0402_16V7K
2 5
GND NC
1
PJ11
PC138
PC77 3 7 PC78 +0.75VSP 2 1 +0.75VS
4.7U_0603_6.3V6K VREF NC 1U_0603_6.3V6M 2 1
2
PR119 4 8 @ JUMP_43X118
1K_0402_1% VOUT NC
9
2
PQ38 TP
2N7002W-T/R7_SOT323-3 G2992F1U_SO8
0.1U_0402_16V7K
PR120
+0.75VSP
1
1
D
PC81
PC82
0_0402_5%
1K_0402_1%
10U_0603_6.3V6M
10U_0603_6.3V6M
PC79
<31> SUSP 1 2 2
1
G
2
1
S PR121
3
PC80
2
2
.1U_0402_16V7K
2
B B
+3VS
1
PJ12
1
JUMP_43X79
2
PU8
2
LDO_1.8V_IN 1 6
VIN VCNTL +5VS
2 5
GND NC
1
1
1
PC83 3 7 PC84
4.7U_0603_6.3V6K PR122 VREF NC 1U_0603_6.3V6M
2
2
1K_0402_1% 4 8
VOUT NC
9 PJ13
2
TP
+1.8VSP 2 1 +1.8VS
LDO_1.8V_REF G2992F1U_SO8 2 1
1.24K_0402_1%
@ JUMP_43X118
1
0.1U_0402_16V7K
2N7002W-T/R7_SOT323-3
PR123 +1.8VSP
1
D
PR124
31.6K_0402_1%
10U_0603_6.3V6M
10U_0603_6.3V6M
PC87
<31> SUSP 1 2 2
1
1
PQ39
G
2
1
PC86
PC88
S
3
PC85
2
0.1U_0402_16V7K
2
A A

1.5VP/1.8VSP/0.75VSP
1.0
5 4 3 2 1
5 4 3 2 1
<27> VR_ON +3VS
1.91K_0402_1% @
10K_0402_1%
1.91K_0402_1%
1
1
PR125
PR126
PR127
2
2
<8,19> VGATE
D D
<19> CLK_ENABLE# 1 2
PR128
<8,19>
DPRSLPVR
@ 0_0402_5%
+3VS +5VS
<27>
VR_ON
1
1
@ 0_0402_5%
0_0402_5%
+CPU_B+ PL8
PR129
PR130
HCB4532KF-800T90_1812
1 2 B+
0_0402_5%
1000P_0402_50V7K
2200P_0402_50V7K
0_0402_5%
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0603_25V7K
2
2
1 1
100U_25V_M
100U_25V_M
PC89
PC90
PC91
PC92
PC93
PC94
0.1U_0402_25Y5V
1
PC136
+ +
124K_0402_1%
PC95
PC96
2
2
2 2
1 CPU_VREF
1
5
2
1
0_0402_5%
0_0402_5%
PR131
PR132
1
PR166
2
PR133
2 1 1 2 4
CPU_DPRSLPVR
PC97 2.2_0603_5%
CPU_CLK_EN#
CPU_TRIPSEL
CPU_OSRSEL
CPU_TONSEL
1U_0603_10V6K
CPU_VR_ON
CPU_V5FILT
CPU_ISLEW
PQ40 PL9
2
PR134
PR135
CSD17308Q3 1N SON 0.36UH_PCMC104T-R36MN1R17_30A_20%
3
2
1
1 4 +CPU_CORE
+5VS
1
C CPU_CSP1-1 C
2 3
PQ41 PR136
1
17.8K_0402_1%
TPCA8028-H_SOP-ADVANCE8-5 4.7_1206_5%
41
40
39
38
37
36
35
34
33
32
31
1 CPU1_SNB
PR137
PD11
CPU_VREF
1 2 1SS355_SOD323-2
ISLEW
OSRSEL
TRIPSEL
CLK_EN#
V5FILT
TONSEL
GND
PWRMON
VR_ON
DPRSLPVR
PGOOD
2
PR138 4 PR139
4.75K_0402_1% 69.8K_0402_1%
2
1 2 CPU_DROOP 1 30 UGATE_CPU1 1 2
PC98 68P_0402_50V8J DROOP DRVH1 PR142 PC101
CPU_CSP1 2 1 1 2 CPU_VREF 2 29 BOOT_CPU1 1 2 BOOT_CPU1-1
1 2 680P_0603_50V7K
3
2
1
VREF VBST +CPU_B+
PR140 470_0402_1% PC99 0.22U_0603_10V7K 3.3_0603_5% PC100 1 2 CPU_SN-1
1 2 PH3
2
2
3 28 PHASE_CPU1 0.22U_0603_10V7K PR141 100K_0603_1% TSM1A104F4361RZ

GND LL1
CPU_CSN1
2200P_0402_50V7K CPU_CSP1
PC102 28.7K_0402_1%
100P_0402_50V8J 1 2 CPU_CSP1-2 4 27 LGATE_CPU1 1 2
1
CSP1 DRVL1
1000P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0603_25V7K
CPU_CSN1 2 1 PC103 33P_0402_50V8K PC104
+5VS
5
PR143 470_0402_1% 1 2 CPU_CSN1-1 5 26 1 2 0.033U_0402_16V7K
CSN1 V5IN
1
PC108
PC109
PC110
PC111
PC112
CPU_CSN2 2 1 PC105 33P_0402_50V8K
PR144 470_0402_1% 1 2 CPU_CSN2-1 6
CSN2
PU9
PGND
25 PC106 10U_0603_6.3V6M
2
PC115
PC107 33P_0402_50V8K TPS51620RHAR_QFN40_6X6
2
PC113 1 2 CPU_CSP2-2 7
CSP2 DRVL2
24 LGATE_CPU2
100P_0402_50V8J PC114 33P_0402_50V8K 4
1
CPU_CSP2 2 1 CPU_GNDSNS 8 23 PHASE_CPU2

PR145 470_0402_1% GNDSNS LL2 PR146
CPU_VSNS 9 22 BOOT_CPU2 1 2 1 2 PQ42 PL10
VSNS VBST2 3.3_0603_5% PC116 CSD17308Q3 1N SON 0.36UH_PCMC104T-R36MN1R17_30A_20%
3
2
1
CPU_THERM UGATE_CPU2 0.22U_0603_10V7K
DPRSTP#
10 THERM 21 1 4
DRVH2
1
VR_TT#
1
0_0402_5%
0_0402_5%
1 2 CPU_CSP2-1
2 3
VID6
VID5
VID4
VID3
VID2
VID1
VID0
PSI#
+5VS
1
1
PR147
PR148
17.8K_0402_1%
PD12 PR149
PR151
1SS355_SOD323-2
PR167 4.7_1206_5%
2
11
12
13
14
15
16
17
18
19
20
1 CPU2_SNB
PR150 1 2
2
B B
1CPU_DPRSTP#
20K_0402_1% 2.2_0603_5% 4 PR152

69.8K_0402_1%
2
2
VID6
VID5
VID4
VID3
VID2
VID1
VID0
PSI#
PQ43 1 2
TPCA8028-H_SOP-ADVANCE8-5
1
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
PC117 PH4
3
2
1
680P_0603_50V7K 1 2 CPU_SN-2
1 2 100K_0603_1% TSM1A104F4361RZ
PR155
2
1
CPU_CSN2
CPU_CSP2
PR153 PR154 28.7K_0402_1%
100_0402_1% 100_0402_1% 1 2
2
PC118
0.033U_0402_16V7K
PR156
PR157
PR158
PR159
PR160
PR161
PR162
PR163
PR164
2
1
<6>
<6>
VSSSENSE
VCCSENSE
+CPU_CORE
<5>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
H_DPRSTP#
<5,8,18>
H_PSI#
CPU_VID6
CPU_VID5
CPU_VID4
CPU_VID3
CPU_VID2
CPU_VID1
CPU_VID0
A A

+CPU_CORE
Custom 1.0
5 4 3 2 1
5 4 3 2 1
V ersion Change L ist ( P. I. R . L ist ) for Pow er Circuit

R equest
P age# Title D ate O w ner Issue D escription Solution D escription
D D
3 $GGFDSDFLWLHVIRU(0,UHTXHVW (0, (0,WHVWIDLO $GG3&3&3&3&3&3&
3 &KDQJHUHVLVWDQFHIRU(0,UHTXHVW (0, (0,WHVWIDLO &KDQJH35IURPRKPWRRKP
$GGRQHFDSDFLWRUIRUSUHYHQW ,IWKHUHLVQ
WDGGFDSDFLW\
3 3:5 $GG3&ZKLFKYDOXHLV3)
LQUXVKFXUUHQWWRRODUJH WKH026RI34KDYHGDPJHGULVN
$GGRQHWUDQVLVWRUIRULPSURYH ,IWKHUHLVQ
WDGGWUDQVLWRU
3 3:5 $GG34
GHVLJQPDUJLQ WKHGHVLJQPDUJLQRI34LVQRWHQRXJK
&KDQJHUHVLVWDQFHIRU&38ORDGOLQH
3 3:5 )RUPHHWWKHORDGOLQHRILQWHOVSHF &KDQJH35IURPNWRN
ILQHWXQLQJ
$GGRQHFDSDFLWRUIRULPSURYH
C C
3 3:5 )RUPHHWWKHULSSOHFXUUHQWVSHFRI&RPSDO $GG3&

ULSSOHFXUUHQW
B B
A A

Power PIR
Custom LA7011P 1.0
5 4 3 2 1
www.s-manuals.com

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A B C D E

ZZZ1 ZZZ2 ZZZ3 ZZZ4 ZZZ5

PCB LA-7012P LS-7012P LS-7013P LS-7014P

Security Classification Compal Secret Data Compal Electronics,Ltd.

DMI 点4 C-Link 2Channel Speaker

AZALIA Audio Codec Analog MIC_Int

SPI ROM 6*SATA serial BlueTooth CONN

AR8151/8152 EC USB PORT X1(Left)

Card Reader RTS5139

4 Touch Pad SATA ODD CONN 4

Security Classification Compal Secret Data Compal Electronics, Inc.

DDR3 Voltage Rails

1 LAN 0 RIGHT SIDE

Security Classification Compal Secret Data Compal Electronics, Inc.

PVT ESD solution.

3 XDP Reserve for debug , Please close to CPU side C651

XDP_TDO R10 1 2 @ 54.9_0402_1%

XDP_TRST# R11 1 2 54.9_0402_1%

XDP_TCK R12 1 2 54.9_0402_1%

Security Classification Compal Secret Data Compal Electronics, Inc.

09/29 Add for power noise

PVT for ESD solution

+CPU_GTLREF H_DPRSTP# H_DPRSTP# H_DPSLP# H_PSI#

Close to CPU pin E5 Close to CPU pin B5

within 500mils. (PU9.12) within within 500mils.

Security Classification Compal Secret Data Compal Electronics, Inc.

+1.05VS Place these inside socket cavity on L8

AA12 C43 C44 C45 C46 C47 C48 C49 C50

AA18 AF4 CPU_VID3 <40>

Close to CPU pin

H_D#37 Y14 F11 H_BPRI#

PVT ESD solution.

Security Classification Compal Secret Data Compal Electronics, Inc.

Strap Pin Table M36 RSVD1 SA_CK_0 AP24 M_CLK_DDR0

DDR CLK/ CONTROL/

+3VS AE41 DMI_TXN0

R722 R723 AE40 DMI_TXP0 0.01U_0402_25V7K 2.2U_0603_6.3V4Z R724

@ @ MCH_CLKSEL1 R25 AE48 DMI_TXP2

MCH_TSATN# 3 1 TSATN# P20 SMRCOMP_VOL

Q42 P24 AE35 DMI_RXN0

R728 1 2 100_0402_5% PLT_RST#_R PM_EXTTS#1 P32 1K_0402_1%

BD48 AN36 M_PWROK

BF46 M28 T109

BH6 H36 MCH_ICH_SYNC#

DDR_A_D36 AU13 BD37 DDR_A_DQS#3 DDR_B_D36 BH12 AV47 DDR_B_DQS#1

DDR_A_D46 AY8 BG24 DDR_A_MA2 DDR_B_D46 BA1 BA25 DDR_B_MA1

Security Classification Compal Secret Data Compal Electronics, Inc.

Place the resistor within 500mils

B37 LVDSB_CLK# PEG_RX#_10 Y48

LVDS_A2# LVDSA_DATA#_1 PEG_RX#_14

Security Classification Compal Secret Data Compal Electronics, Inc.

L37 D38 R746 @ R747 1 1 1

VCCD_QDAC: 48.363mA 1.8V_LVDS: 60.311111mA

Security Classification Compal Secret Data Compal Electronics, Inc.

AG33 VCC_11 BG31 VCC_SM_19 VCC_AXG_NCTF_20 U20

AF33 VCC_12 BF31 VCC_SM_20 VCC_AXG_NCTF_21 AM19

BH29 VCC_SM_22 VCC_AXG_NCTF_23 AK19