Circuit Simulation and Analysis PDF

Circuit Simulation
and Analysis byDrSaeidMoslehpour
An introduction to computer-aided circuit

design using PSpice software
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Contributing Editor
Edith Lennon, N2ZRW
Production
Shelly Bloom, WB 1ENT
Jodi Morin, KA1JPA
Maty Weinberg, KB1EIB
David Ping ree, N1NAS
Cover Design
Sue Fagan, KB10KW
Copyright © 2013 by
The American Radio Relay League, Inc.
Copyright secured under the Pan-American

Convention
All rights reserved. No part of this work may

be reproduced in any form except by written
permission of the publisher . All rights of
translation are reserved .
Printed in the USA
Quedan reservados todos los derechos
ISBN: 978-1-62595-005-5
First Edition
First Printing
"orCAD," "PSpice," and

"Cadence" are trademarks of
Cadence Design Systems Inc.
Contents
Foreword
Preface
About the Author
1 Introduction
2 The DreAD User Interface
3 Netlist Element Lines
4 Basic Simulation Types
5 Netlist Control Lines
6 The PSpice Probe Tool
7 Semiconductors
8 Miscellaneous Components
9 Transmission Lines
10 Subcircuits
11 Sample Circuits
12 Advanced Analysis
Appendix: Low-Pass Filter, Operational Amplifier,
Phase-Shift Oscillator, Astable Multivibrator, Hartley Oscillator
Foreword
The circuit design proce ss is usually interactive, with testing along
the way to ensure that a circuit performs as expected, followed by design
changes and more testing. The time-honored way to do this was to build a
physical prototype, test it over a range of range of operating voltages, sig-
nal levels, temperatures and other factors, tweak it and test some more.
In the 1970s, scientists at the Universit y of California, Berkeley, de-
veloped Simulated Program 'with Integrated Circuit Emphasis (SPICE), a
program for simulating circuits on a mainframe computer. Now engineers
could create, analyze and modify circuits using software, coming much
closer to the final design before soldering a single component.
Fast-forward to today, and SPICE, along with its derivatives, is
hugely popular for predicting the behavior of electronic circuits. PSpice
from Cadence Design Systems is a version of SPICE that runs on per-
sonal computers and offers many features, component libraries and
tools for circuit designers. Anyone performing circuit analysis or design
should have a working knowledge of PSpice in order to save time and
gain insight into circuit behavior by answering "what if' questions with
a computer simulation. Students, profe ssional s and hobbyi sts already fa-
miliar with traditional methods of circuit analysis will find PSpice to be
an important tool for learning circuit analysis and design and for testing
electronic circuits in ways they could not easily do in many laboratories.
In the book , Dr Saeid Mo slehpour introduces readers to the basic
functions and tools needed to create simple circuits and analyze their be-
havior using PSpice. To get the most from this book, readers are expected
to obtain a version of this software (see Chapter I), and follow along with
the examples.
David Sumner, KIZZ

Chief Executive Officer
Newington, Connecticut
October 2013
Preface
The first two editions of this book were published in 1988 and
1990 by my colleague, mentor and friend, Professor Walter Banzhaf,
WB lANE, and it was admired by many in the electrical engineering field.
I had this idea of upgrading the book back in 2008, and after five years all
those efforts paid off. What you have here is almost a new book.
PSp ice was initially developed by MicroSim and was used in elec-
tronic design automation. The company was bought by OrCAD, which
was subsequently purchased by Cadence Design Systems. PSp ice was
the first version of UC Berkeley SPICE available on a PC, having been
released in January 1984 to run on the original IBM Pc. It remains one of
the best known and most widely used packages on the market today.
I am using Cadence Design Systems version 16.5 for all simulations
in this book. Although there are many modules within this software pack-
age, I am emphasizing use of the tools available in DrCAD Capture and
PSpice (or in the full package from Cadence Design systems, Allegro
Des ign Entry Capt ure and Allegro AMS Sim ulator) . More information on
this software is found in Chapter 1.
I express deep appreciation to Walter Banzh af who created 1st and
2nd editions, and my handling editor Edith Lennon, N2ZRW. I also thank
the talented audio engineer Brandon LaChance, my former student and
great engineer, who helped with many of the simulations and without
whom this book couldn't have been published. A special word of thanks
to my wife, Parisa, and my mother Giti, and my father, Amir.
Finally I would like to thank you for choosing this book. I hope this
book will enhance your knowledge of electrical/electronic design and
simulation. Please share your suggestions and comments. There is a feed-
back form at the back of the book for this purpose, or send an e-mail to
pubsfdbk@arrl.org.
Saeid Moslehpour, PhD

Professo r of Electrical Engineering,
University of Hartford
West Hartford, Connecticut
October 2013
About the Author
Saeid Moslehpour, PhD, is Associate Professor of Electrical and
Computer Engineering and Department Chair at the University of
Hartford in Connecticut. Dr Moslehpour holds BS and MS degrees
in Electronics from the University of Central Missouri and a PhD in
Industrial Technology and Computer Engineering from Iowa State
University. He is a Senior Master Engineer in the National Association of
Radio and Telecommunications Engineers, a Senior Member, IEEE and
Member, ASEE .
About the ARRL
The seed for Amateur Radio was planted in the 1890s, when Guglielmo
Marconi began his experiments in wireless telegraphy. Soon he was joined
by dozens, then hundreds, of others who were enthusiastic about sending and
receiving messages through the air-some with a commercial interest, but
others solely out of a love for this new communications medium. The United
States government began licensing Amateur Radio operators in 1912.
By 1914, there were thousands of Amateur Radio operators-hams-in the
United State s. Hiram Percy Maxim, a leading Hartford, Connecticut inventor
and industrialist, saw the need for an organization to band together this fledg-
ling group of radio experimenters. In May 1914 he founded the American
Radio Relay League (ARRL) to meet that need.
Today ARRL, with approximately 155,000 members, is the largest orga-
nization of radio amate urs in the United States . The ARRL is a not-for-profit
organization that:
• promotes interest in Amateur Radio communications and
experimentation
• represents US radio amateurs in legislative matters, and
• maintains fraternalism and a high standard of conduct among Amateur
Radio operators.
At ARRL headquarters in the Hartford suburb of Newington, the staff
helps serve the needs of members. ARRL is also International Secretariat for
the International Amateur Radio Union, which is made up of similar societies
in 150 countries around the world.
ARRL publishes the monthly journal QST and an interactive digital ver-
sion of QST, as well as newsletters and many publications covering all aspects
of Amateur Radio. Its headquarters station, WIAW, transmits bulletins of
interest to radio amateurs and Morse code practice sessions. The ARRL also
coordinates an extensive field organization, which includes volunteers who
provide technical information and other support services for radio amateurs as
well as communications for public-service activities. In addition, ARRL rep-
resents US amateurs with the Federal Communications Commission and other
government agencies in the US and abroad.
Membership in ARRL means much more than receiving QST each month.
In addition to the services already described, ARRL offers membership ser-
vices on a personal level, such as the Technical Information Service-where
members can get answers by phone, email or the ARRL website, to all their
technical and operating questions.
Full ARRL membership (available only to licensed radio amateurs) gives
you a voice in how the affairs of the organization are governed. ARRL policy
is set by a Board of Directors (one from each of 15 Divisions). Each year,
one-third of the ARRL Board of Directors stands for election by the full
members they represent. The day-to-day operation of ARRL HQ is managed
by an Executive Vice President and his staff.
No matter what aspect of Amateur Radio attracts you, ARRL member-
ship is relevant and important. There would be no Amate ur Radio as we
know it today were it not for the ARRL. We would be happy to welcome
you as a member! (An Amateur Radio license is not required for Associate
Membership.) For more information about ARRL and answers to any ques-
tions you may have about Amateur Radio, write or call:
ARRL-the national association for Amateur Radio®
225 Main Street
Newington CT 06111-1494
Voice: 860-594-0200
Fax: 860-594-0259
E-mail: hq@arrl.org
Internet: www.arrl .org
Prospective new amateurs call (toll-free):
800-32-NEW HAM (800-326-3942)
You can also contact us via e-mail at newham@arrl.org
or check out the ARRL website at www.arrl.org
Chapter 1
Introduction
Circuit analysis is a necessary part of circuit design. Once a design for

a circuit has been determined, the soundness of that design must be tested
to ensure that the circuit does indeed perform as required and intended.
Often this involves testing for de operating point and performance, with
signal applied, over a range of de supply voltages, input signal levels and
temperatures. The time-honored way to do this was to build a prototype of
the circuit, send it off to the laboratory, and invest large amounts of time
and money in putting the circuit through its paces in the hope that it would
perform as desired.
The Need for Circuit Analysis

A much better method was introduced with Simulated Program with
Integrated Circuit Emphasis (SPICE), a software program developed in
the 1970s to allow circuits to be simulated on a mainframe computer, thus
saving huge amounts of time and money in the early development stages
of circuit design . Using this software would allow electrical engineers to
reduce lengthy calculations needed for electrical/electronic circuit design .
Engineers would design the circuits and view the results in texts or graphical
format. Cadence Design Systems, Inc (www.cadence.com) promotes
the same software under two names: Cadence SPB (www.cadence.com!
products/orcadlPages/default.aspx) and OrCAD (www.ema-eda.com);
they are essentially same products with two different names .
SPICE is an early predecessor of the Cadence PSpice (Personal
Simulation Program with Integrated Circuit Emphasis) software explored
in this book.
To appreciate the capabilities and continual development of PSpice it
is helpful to have an understanding of its origins, but one does not need to
understand the algorithms and mathematical techniques that PSpice uses to
Introduction 1-1
analyze circuits in order to successfully solve circuit problems with PSpice,
any more than one needs a working knowledge of internal combustion
engines to drive a car. However, it is vitally important for anyone using
SPICE (or any other computer analysis /design program) to be a competent
practitioner in the field of electrical and computer engineering. Only in that
way can one check the correctness and reasonableness of the computer's
answers by estimation using sound engineering judgment and/or by working
a sample problem through by conventional means.
PSpice Overview
PSpice is a PC version of SPICE that runs on personal computers
and offers many improvements over other releases. SPICE, along with
its derivatives, is the most popular computer program in the world today
for predicting the behavior of electronic circuits. It was developed by the
Integrated Circuits Group of the Electronics Research Laboratory and
the Department of Electrical Engineering and Computer Sciences at the
University of California, Berkeley, California. The person credited with
originally developing SPICE is Dr. Lawrence Nagel, whose PhD thesis
describes the algorithms and numerical methods used in SPICE. The
software has undergone many changes since it was first developed, and it
continues to evolve .
SPICE is a large (over 17,000 lines of Fortran source code), powerful,
and extremely versatile industry-standard program for circu it analysis and
IC design . A significant number of companies have customized Berkeley's
SPICE for in-house circuit development work. Many software packages
based on SPICE have been developed which use the SPICE2 program, also
from Berkeley, as the core for performing circuit analysis. Most of these
have added useful programs to make the complete package easier to use.
For example, SPICE2 is not interactive, it does not have the capability to
reference a library of semiconductor components, and its graphs are made
on a line printer using American Standard Code for Information Interchange
(ASCII) symbols. Although it did not feature interactive libraries, it enabled
the user to create models for metal -oxide-semiconductor field-effect
transistors (MOSFETs), bipolar junction transistors (BJTs), field-effect
transistors (FETs), and diodes. Some of the commercially available packages
are interactive, include extensive libraries of parts, and have graphics post-
processors that make professional-looking graphs.
SPICE3 was developed in the late 1980s, modified, and rewritten using
the general purpose programming language C. The first stable release of
SPICE3, in 1993, featured advanced component models for MOSFETs.
Initially, SPICE relied on a mainframe-based operation and has since been
1·2 Chapter 1
modified to function on some of the more common operating systems and
personal computers. With this innovation, the acro nym has been amended
from SPICE to PSpice, the P, of course, standing for personal.
At the time, OrCAD, short for Oregon Compu ter A ided Design, was
becoming increasingly popular in the design industry for its ability to create
schematic representations of designs and printed circuit board layouts.
Founded in Hillsboro, Oregon, in 1985 by John Durbetaki and Ken and
Keith Seymour as OrCAD Systems Corporation, the company was acqui red
in the late 1990s by Cade nce Design Systems to be used in conjunction with
the advanced PSpice simulators to funct ion as a schematic capture software
program to interpret a schematic design input by a user for simulation
purposes. Thi s is vastly different from some of the prim itive versio ns of
SPICE that required the user to enter a schematic design into the software by
means of a netlist , a text representation of a schematic derived by the user.
As of this wr iting , the most recent release of the OrCAD /PSpice
software is version 16.6.1 PSpi ce, and other packages based on it, will be
around and widely used for many years to come. As you read this book,
you will see that PSpice, though developed for the design of integrated
circ uits, can be used to sol ve a great variety of non-IC circuit problems
involving power supplies, three -phase power systems, tran smission lines ,
and nonlinear components, to name a few applications. Anyone performing
circuit analysis or design should have a working knowledge of PSpice in
order to save time and money and to gain insight into circuit behav ior
by answering "what if' questions with a computer simulation. "What if'
questions are freq uently not answered if the tedium involved in doing so
outweighs the curiosity of the person asking the question.
Students, profes sionals and hobbyists will find PSpice to be an important
tool for learning circuit analysi s and design and for testing electronic circuits
in ways they could not easily do in many laboratorie s. By learning a version
of SPICE, users will be preparing for the kind of circuit simulation they will
encounter in indu stry. They should, however, be competent in traditional
methods of circuit analysis before embarking on computer methods.
A Word on Nomenclature
Severa l different packages of the Cadence design and analysis software
are available and were used in preparation of this book . At the time the
book was written , Version 16.5 was most current, but version 16.6 is now
available. Regardless of where it was obtained, the software packages are
ident ical and feature s differ only in name. In later chapters of this book you
will see examples created with the various packages.
Introduction 1-3
EMA Design Automation
If the software is obtained from EMA Design Automation (www.ema-
eda.com), the software will be called:
Schematic capture - DrCAD Capture or DrCAD Capture CIS
Circuit simulation - PSpice ND or PSpice Adv anced Analysis
Cadence Design Systems

If the software is obtained fro m Cadence Design Systems (www.
cadence.corn), the softwa re will be called:
Schematic capture - Cadence Allegro Design Entry Capture or Allegro
Design Entry Capture CIS
Circuit simulation - Cadence Allegro AMS Simulator
Demo Version
Demo versions are available for download from the Cadence website
at www.cadence.com/pl·oducts/orcad/pages/downloads.aspx. The demo
package includes DrCAD Cap ture CIS Lite and PSpice AID Lite, which are
fully functional versions that can be used to explore the examples in this
book. There are some limitations on circuit and analysis complexity, but
these are very useful and powerful tools.
Support Files
Modeling files for some of the examples described in this book are
available from the ARRL website at www.ar rl .or glcircuit-simulation.
Notes
'Source for company history and development, www.fundinguniverse.com/company-
histories/cadence-design-systems-inc-history/.
1·4 Chapter 1
Chapter 2
The O,CAD User

Interface
In the last chapter, the main topics of disc ussion were an overview
of the Cadence software. You were also provided with a brief history, an
outline of the different incarnations of the Cadence/PSpice software, and a
few general statements giving an overview of its capabilities.
Familiarization and Preparation of the

Design Entry User Interface
In this chapter, you will become familiar with the graphical user
interfaces (GUI s) utilized in the Cadence software, one of which is the
schematic capture tool, Cadence A llegro
Design Entry, and the other is the Cadence
NewProJo<l
Allegro AMS Simulator. (In Chapter 1 we
OK
Name -;:- _ learned that these products are called DrCAD
Chapter 2 ~el
Capture and PSpi ce ND in the EMA Design
Createa tIew ProjectUsn g !:lolp version and DrCAD Capture CIS Lite and
o am10g 01M ~edAID PSpi ce ND Lite in the demo version. We'll
Tip for New User:
refer to them as Design Entry and AMS
EC Board Wizard Create a new Analog or
Mixed AID project. The
Simulator, but the screens look and work the
-lib 0 P,og,ammable!.ogicw cerd
new proiectmay be blank
or copied from an exi:.ting
template.
same for either version .) By looking at three
things - the circuit schematic diagram, the
~ O~Chemalic simulation settings, and the output file - you
will gain an appreciation of what the Cadence
LQcation
software can do and start to use it yourself.
B!ow:e... A good way to begin learning PSpi ce is to
create input files via Design Entry schematics
similar to the one s in this chapter and then run
Figure 2.1 - NEW PROJECT window. analy ses of them .
The DreA D User Interface 2-1

Before beginning any type of simulation using the Design Entry and AMS
Simulator, you must create a blank project. Upon selecting the Design Entry
software icon, you will be presented with the window shown in Figure 2.1.
This window allows the user to designate a name for the project and
select a directory in which the project can be stored. In order to carry out
the bas ic simulations covered in this text, it is important to select the button
labeled ANALOG OR MIXED AI D. A common mistake made by new users
of the Cadence software is the selection of the SCHEMATIC file type. This
schematic file type will only allow the user to create a schematic design of
a circuit, but will not allow a netlist or simulations to be generated.
The project used to generate the schematics and simulations that
illustrate this chapter has been titled, "Chapter2." When creating your own
projects, you may store them to a destination of your choosing by either
entering a directory manually in the LOCATION text box or by using the
BROWSE butto n and selecting a folder. After creating a project, you will be
presented with the screen shown in Figure 2.2.
Th is is the Design Entry GUI. Before inputting a schematic design, it
is important for a user to become fami liar with the icons , drop -down menus,
and workspace. The icons along the right side of the screen are the action
iconslbuttons that allow for some of the most basic operations necessary
for schematic design. These actions include cursor selection, wire/bus
Figure 2.2 - DesignEntry workspace.
2-2 Chapter 2
placement, part placement, net alias naming, and ground placement and
will be covered in this chapter (see Figure 2.3).
The buttons across the top are shortcut buttons for file management
options, such as saving, opening, and creating new files, in addition to a
ZO OM function. The ZO OM function can change the user's perspective of
the schematic design: zooming in or out allows for a close-up view of a
particular portion of the schematic or a wide view of the schematic as a whole.
Other buttons along the top of the screen can be used to place measurement
probes and create a simulation profile that defines the parameters of the
simulation to be conducted on a given circuit (we will discuss all of these
cadence in the following examples).
The remaining central portion of the screen is the workspace, which
is where the user can develop or draw a schematic design, placing and
connecting components from the PSpice libraries within the software. Also,
take notice of the text box in the lower right corner of the workspace. In this
text box, you can provide a title and description for the schematic design .
This can be especially helpful when performing analysis on complex projects.
When working on a project with multiple pages and schematic designs, titles
and descriptions can help you differentiate one design from another.
Before developing and testing a schematic design, you must ensure
you have the desired components and libraries available in the Design Entry
software. To do so, click the PLAC E PART button on the toolbar at the right
of the screen (shown highlighted in Figure 2.4). After clicking the PLACE
PART button on the toolbar, the right side of the
• • • • •~ (a!l!!ld~
e n~(e~-~.~.i screen will open as shown in Figure 2.5 .
."• The only default library available to a user
~------- is the DESIGN CACHE . The DESIGN CACHE will
catalog and keep track of all of the existing
Figure 2.3- y components of a particular project, allowing for
DRAW ING toolbar. - -- - - ,
easy access to a component frequently used in a
design. For example, if you are drawing multiple
band-pass filters using inductors, capacitors and
resistors in the Design Entry software, after you
place one of each into the schematic, you will
be able to quickly find these components in
the Design Cache library for future use, rather
than having to search through the libraries they
originally came from. Since your new project
has just been created, no components have
Figure 2.4 - PLA CE been placed as yet, so your DESIGN CACHE will
PART button. Figure 2.5 - ADD LIBRARY
button. be empty. To proceed to the schematic design
The OreAD User Interface 2-3

r
[!g Br<>WS<' Fil~
Look,, : pspce
Nam e Date mo d ified

0;. edveo ls 8/17/2011 5:06PM
Rec ent Plac es
m o deled 8/17120114 :59 PM
~ l_s h ct 8/17/2009 5:41 PM OrCAC
d 74ac 8/17/2009 5:41 PM OrCAC
Desktop ~ 74act 8/17/20095:41 PM OrCAC
S 74als 8/17/2009 5:41 PM OrCAr
:!: 74. s 8/17/20095:41 PM OrCAC
Libraries :!!:74f 8/17/20095:41 PM OrCAC
~ 74 h 8/17/20095:41 PM OrCAC
~ 74 hc 8/17/2009 5:41 PM OrCAC
Comp uter ~ 74 h ct 8/17/2009 5:41 PM OrCAC.
~ I, .J
'"
Re name:
Netwo rk
fiesd!l1>e:
Figure 2.6 - BROWSE FILE folder contains all available PSpice libraries.
---:; ".
, ! ~ : ; P.,t ~ ..X
/I
!~ -R - - - -- - -
J' J' ,~",~.~;t;:;7;1XT'"""AL

QZS1(}.iEGtxTAL
C--- --:l"7.
.
QZS1MEGJXTAl
QZS327S8IXTAl
-
Figure 2.7- Active component libraries.
2-4 Chapter 2
cataloged in the PSpi ce library using this abbreviation. The resistor component
is immediately highlighted on the PART LIST . At this point, the user can either
press ENT ER or double-click the highlighted component to attac h it to the
mouse cur sor for placement. Notice the highlighted icon in Figure 2.7; this
is the AMS Simulator icon . The presence of this icon while a component is
highli ghted in the PART LIST tells you that this component can be used for
simulations and circuit analysis. If this icon is not present, it may indicate
that a library has been added that has parts that are not compatible with the
AMS Simulator. While it may be used to create a schematic drawing, the part
cannot be used for analysis.
Drawing a Schematic Design

Let' s begin with a de circu it containing a battery (independent voltage
source) and three resistors. The circuit diagram is show n in Figure 2.8.
This schematic design can be entered into the Design Entry software.
The two component types R1
84
uti lized in this circuit are 17
the dc voltage source and

the res istor. As we learned, 6V J::~
.1V1
R2 R3
10 40
the abbreviation R is used
to cata log the resistor in the
PART library. The dc voltage
source is cataloged under the __
abbreviation of VDC. On the ""'0
'--------------------'
page, place one de voltage Fig ure 2.8 - Basic schem atic design using one dc
source and three res istor s. source and three resistors f rom PSpice lib raries.
Once the component s have been placed, they can be l=i~~.~i~j
repositioned to allow for the configuration shown ~
in Figure 2.8. Notice that the defau lt placement of a e xl
resistor in the Design Entry software is horizont al,
similar to the pos ition of R1 in the schematic
shown . In order to plac e the resistors vertically,
similar to R2 and R3 in the parallel branches of the
sche matic, simply right-click the com ponent and
select ROTATE. Another way to rotate a component
GJO
is to click on the part so that is highlighted and
then press the R key on your keyboard. The defau lt
cursor in the Design Entry software is the SE LECT
Figure 2.9 - SELECT
too l, which enables the user to place and move tool has been enabled in
parts. The SELE CT tool is enabled in Figure 2.9. DRAWINGtool bar.
The OreAD User Interface 2-5

To change the cursor to the WIRE tool, select the icon directly below
the SELECT tool on the toolbar to the right of the screen . Once the four
components are properly oriented, they can be connected with the WIRE tool
to resemble the schematic diagram in the example shown in Figure 2.8. Click
and hold the left mouse button while drawing lines to connect the component
terminals (Figure 2.10), and you will see that components will be placed
with a default value. In the case of the
de voltage source, the default voltage
R1
value is 0 V; in the case of the resistor,
1k the default resistance value is 1 kn.
V1 These values can be modified to
OVd '--,::- R2 R3 fit the parameters and specifications of
1k 1k
our schematic design in Figure 2.8. To
modify a component value you may
employ one of two methods . First, using
the SELECT tool, hover the cursor over
Figure 2.10- Components have been placed into the DESIGN the line of text that declares a value
ENTRY window, but component values and net names have not next to the component. Double -click the
yet been declared.
line of text and you will be presented
with a window titled DISPLAY PROPERTIES (see
Display Properties Figure 2.11). By double -clicking OVdc, the default
Fonl
voltage value, the DISPLAY PROPERTIES window
Name: DC
Arial7[delault) is now active. To change the value of potential that
Value: L()V~c __.J ~ ~ '. Del~ is present in this dc voltage source, simply enter a
Di,playFormal
Colo!
new voltage value into the VALUE textbox and press
el Do Not Displey the OK button . For this particular schematic design,
(~I ValueOnly 'Imel the value of the dc voltage source happens to be
o NameandValue Rotation
~ N ame O nly
(I') l BO' 6 V. Using this same method, change the value of
o Both" Value Exists {) 270' R1 from 1 ill to 4 n, R2 to 10 n, and R3 to 40 n.
OK \ 1 Cancel I I Help
There's another method that can be used to
display and alter all component parameters. Use
Figure 2.11 - DISPLAY PROPERTIES window for dc the SELECT tool to highlight a component and then
voltage source V1.
double -click on it, which will open the PROPERTY
cade ri'i
.
RYAl DC l.oalbofox..coordlMllt l outiotly -Coontorwlte SOCIrc..,m

{/ ", >' , ' -'/ ' /i.:.<" Woe / ,/, 1 J j(J 15(; 'iOC .Ner-r4J
Figure 2.12- PROPERTY EDITOR window.
2-6 Chapter 2
EDITOR tab, as shown in Figure 2.12. With the PROPERT Y EDITOR tab open,
you can change more than one parameter at a time . After the parameters
have bee n altered, click the APPLY button to save changes to the component.
With the correct components, values, and wiring, the schematic begins to
take shape (see Figure 2.13).
Before moving on to the simulation, you mus t make two more
alterations to the schematic. To run any type of simu lation using the AMS
Simulator, the circu it needs a reference grou nd. Look ing back to the original
schematic, note that the circuit ground is attached to the negative terminal
of the voltage source. To replicate this in the Design Entry software, look
to the toolbar to the right of the screen and click the button with the ground
schematic symbol (see high lighted portion of Figure 2.14). You will be
presented with anot her part directory in a window titled PLACE GROU ND
(see Figure 2.15).
The ground symbol is cataloged using the
R1 number O. Place and connect this schemat ic
symbol to the rest of the schematic design
V1
as seen in Figure 2.8. The schematic design
6V ~ R2 R3 is almost complete, but you can make one
10 40
last alteration to your circuit by adding Net
Aliases. Net Aliases are names chosen by the
user to reference any node in a given circuit.
The example schematic shown in Figure 2.8
Figure 2.13 - Schematic design from Figure 2.10 has been names the node at the positive term inal of
modified to declare new component values. the voltage source 17, and the node between
Ptece Ground
caden ce 1- B x:
Symbol:
OK
~ el
--=ffi=-- I AddLb",y...
l.ibreries:
o I Remove Lib<ory I
Q i!CJ
Neme:
UseO/CAPSYM syrnbol tc place 0 de ground !

C U~tGroup Glcund L-----===~_:J I I
EJ Show Un/'IamedNetriroup
Figure 2.14 - PLACE Figure 2.16 - NET
GROUND button. ALI AS button.
Figure 2.15 - PLACE GROU ND win dow.
The OreAD User Interface 2·7

Pla<:e Net Alias
R1 and the parallel branches is named
84. To insert these node names into the
Alias:
Design Entry schematic design, click
Cancel the NET ALIAS button located on the
Help
toolbar to the right of the screen (see
Figure 2.16).
Color Rotation Next, open the PLACE NET ALIAS
I~; 0 ~ 90 e> 180 f) 270 window . In the ALIAS text box, the
user is allowed to enter any desired
Font
Change... I Use Default 1 Arial 7 (default] alphanumeric value (see Figure 2.17).
Pressing OK will attach the user-defined
node name to the cursor, and it can be
NetGroup placed on the schematic page at any node
o NetGroupAware Aliases of the schematic design. After placing
and connecting the ground symbol and
Net Alias names to the schematic, it
Figure 2.17 - NET ALIAS window. should resemble the schematic shown
in Figure 2.18.
In Summation
R1 This chapter has outlined some
17
4
of the fundamental concepts of
schematic design using Cadence
VI
6V ~ R2 R3 Allegro Design En try or DrCAD
10 40 Capture. It is crucial that the user have
a strong understanding and a good
famil iarization with the schematic
workspace to take full advantage of the
Cadence software package. The next
chapter provides a further explanation
Figu re 2.18 - Completed schematic design. of the interconnections between the
components of the schemat ic drawing
seen in this chapter and describes these components and interconnections
in the form of the circuit's netlist.
2-8 Chapter 2
Chapter 3
Netlist Element
Lines
In the previous chapter we introduced the Cadence Allegro Design

Entry (or OrCAD Capture) software and demonstrated the basics of how
to create a schematic design . In the Design Entry workspace we created a
circuit consisting of three resistor s and a de voltage source; this circuit has
been recreated as shown in Figure 3.1.
Generating a Netlist from a Schematic De sign

Before we move into the discussion of simulation types and simulation
profiles that can be set up within the Cadence software, it is important that
you have a rudimentary understanding of how the software will interpret this
schematic design . To expand upon this topic , we will introduce the concept
of the circuit's netlist.
A netlist is a text file that provides a complete list of all of the comp onents
used in a schematic design. Using a specified notation, this list also describes
all the different nets, or points of connection, between
R1
each of these components. Therefore, every circuit
17 64
you create will have an associated netlist. We will
begin by outlining the process involved in generating
V1
R2 R3 a netlist based on an existing schematic design , and
10 40
~
61/
then making this netlist visible to the user. After the
T
---.L
netli st is generated, we ' ll see how to interpret the
~o
notati on used in each element line of the netlist.
In this first example, we see that the circuit in
Figure 3.1 - Three-resistor circu it. Figure 3.1 has been drawn into a new project titled
Netlist Element Lines 3-1

,.........
. ... cidf ncf ~ ••
4 .,
Figure 3.2 - DrCAD Capture/Allegro Design Entry window, SCHEMATIC project tab active .
caden" .• •'
Df... .·'. "'"'-"'"

r.:=- EJ OGJft'. eo
t fi) .\IIdloot ftoo
C!J 'A"":MAncl
(lll:i:!l
. CJ ~ e- ...
D ......
• D "'-
.. CJ ~~~_ft
= ' =.. · L·· · I)··
~£RRClR(ORCAP-XDleJ ~~ ~_(om:d1tleillltll:M'~-.dretry
l E.dng "c'OrCAl)DrCAD_:6~U.. ...IolZ~

IEO( OR:CAP-J2OO5J -Done-
. ure"pSbll'p
tiF O(ORCAP-32002\ NeGISl:nQ melJe""..ql

~E?£~~ ) _~_~ __ . . _ •. •
ee- .psl-4"C0RCADl0RCAD_ 16~_UT£\TOOl'SCN'~lon· .n"C'ORCADIORCAD_1 6~_UTE\TClOl.SCfo,PTURF~
Figure 3.3 - DrCAD Capture/Allegro Design Entry window, PROJECT

HIERAR CHICAL tab.
" Netlist" (see Figure 3.2). After sav ing the circuit, click the proj ect tab
(labeled NETLlST) to display the project files (see Figure 3.3).
The design shown in Figures 3.1 and 3.2 is located on Page I of the
project's schematic. Click the PAGE 1 icon to highlight this page, as shown
in Figure 3.3. From within the toolbar that spans the top of the user interface,
click the CREATE NETLIST button (available in the TOOL S menu)) to open
the CREATE NETLIST window (see Figure 3.4).
3-2 Chapter 3
~
~ OM. ~ I'omIIt _
~ OM. &bQrwI1'omIIt_
T 0:
Otoc<nd
00 lIoIllooO!n:t ..---.------------.-_.--...-.-.
T~ •
............................. ,
~ """" ORC -... for em.. ..., W_

- ~ Corrc>ocbIlY /!!odo (16.2 "" Pllor~l
_~ ; ~0UlU
C;I£)RC.\IroRCAluu j i mlOOLS'OJ'TURE\Hotht\Notnot
Figure 3.4 - CREATE NETLIST windo w.
cadence _ .. xi
. • .""rct II£nlSf
V VI 110 t
. •-.1
~. "-a2
IT . <I <I 'Ie- o, o
0 I i 10 TC- O. O
; .:U 0'" iO TC- O. O
Figure 3.5 - Netlist window for three-resistor circuit in Figure 3.1.
Select the PSPICE tab in the CREATE NETLIST window. Under this tab,
use the NETLIST FILE: textbox to enter a filename and destination to save the
netlist file. For the purposes of this example, the netlist file has simply been
titled Net.net. After clicking OK, the netlist file is created and will open as
a new tab in the Cadence softwa re (see Figure 3.5) .

Interpreting the N e t li st
Figur e 3.5 present s the user with the netli st associated with the
schematic from Page I of the schematic design. Figure 3.6 is a close -up
of the data displayed in Figure 3.5 and legibly displays the five lines that
comp rise the newly gene rated netlist.
The first line reads ' source NETLIST and informs the user of the source
schematic of the data displayed in the lines below. In this case, the source
is the "Netlist" project created earlier. The next four lines of the netlist are
referred to as element lines. The se element lines reference the individual
comp onents of the schematic, outl ine their nodal connections, list their
values, and can even allow the user to designate other modifications to the
underlying parameters of each part. The second line reads V_V1 1706. The
first letter of this element line, V, designates that this element line indicates a
voltage source. This is followed by an underscore, and then the name of the
voltage source component as it is listed in the schematic design. Referring to
the schem atic design, the name of the de voltage source is V1 and is visible
in this element line.
Recall that when we created the schematic design for this three-resistor
circuit, Net Alias names were provided at different nodes of the circuit. An
alias name of " 17" was designated at the node where the positive terminal
of the de source connects to the first terminal of R1, and an alias name of
"84" was designated where the second terminal of R1 connect s to the R2 and
R3 resistive branches. With this in mind, let' s look at the second half of this
.U!JI OrCAD Capture CIS - Lite - IC:\OrCAD\OrCAD_16.5_'

iJ Eile 1dit 10015 Qptions Window 1:ielp
SCHEMATIC1 -NeUist ....
Start Page )(Em1 Netlist* ](~ PAGEl

J
-. s o u r ce NETLI ST
I<
-. V Vi
-
17 0 6
~
-
.
R R1 17 8 4 4 TC= O, O
~ : R R2 0 8 4 10 TC= O, O
- . R- R3 0 84 40 TC= O, O
-:::
Figure 3.6 - Netlist close-up showing the five element lines.
3-4 Chapter 3
°
element line, which reads 17 6. The first number, 17, is represen tative of the
nodal connection of the positive terminal of the voltage source. The second
number, 0, is representative of the nodal connection of the negative termina l
of the voltage source . Even though the user did not actively create a net alias
of "0" at the negative terminal, this is the default net name at the point of the
circuit that has been designated as circuit ground. The third numerical value is
the magnitude of voltage . In the case of this design, the de source is set to 6 V.
The next three element lines reference the three resisto rs and delineate
their interconnections in the schematic design. The third line in the netlist
reads A_A1 17844 TC=O,O. As was seen with the voltage source, the first
letter of this element line designates the type of component that is being
referenced. In this case, A mean s that this component is a resistor. This is
followed by an underscore and then the name of the resistive component,
A1, as listed in the schematic design . The three numerical values that follow
the component name, 17 84 4, are net alias names and component values.
The first number, 17, is net alias" 17" and signifies the connection of the
first terminal of resistor A1. Looking back to the voltage source element
line, note that the positive terminal of the voltage source connects to net
"17" as well ; therefore, we see that the positive terminal of voltage source
V1 connects to the first terminal of A1. The next number in the element line,
84, indicates the connection of the second terminal of A1 in the schematic
design to net alias "84 ." The third value, 4, tells the user that component A1
is a 4 n resistor. The last portion of the element line reads TC=O,O. TC stands
for temperature coefficient and will delegate certain physical changes in
resis tance with respect to change in temperature in increments of 1 kelvin .
The default values for both temperature coefficient values are zero, so any
simulation results yielded from this netlist would mimic ideal conditions.
The next two element lines map out the connections of the last two
resistors in the circuit, A2 and A3. Looking at these two element lines, it is
evident that these resistors are in parallel. The first terminal of A2 and A3
connects to circuit ground, and the second terminal of each resistor connects
to net alias "84", which also happens to be the second terminal of A1. These
element lines also describe the values of resistance for A2 as IOn, and for A3
as 40 n. As was seen in the A1 element line, the TCs have not been changed
from their defa ult values of 0,0 for either A2 or A3.
Generating a Netlist Without Net Aliases

When creating a schematic design, it is not necessary to create net alias
names for every node in the circuit. A netlist can be generated on a schematic
with no designated net aliase s. To illustrate this point, the net aliases" 17"
and "84" have been removed from the circuit shown in Figure 3.1 and the

R1
schematic has been saved in the "Netlist" project
(see Figure 3.7). The schematic layout remains
4
the same, the net aliases have been removed, and
R2 R3 a netlist has been generated (see Figure 3.8).
V1 10 40
Upon generating a netlist or carrying out a
BV ~f simulation of a schematic design, the Cadence
---.L
t -- - - - - - - - - -4-- -----' software will assign arbitrary net names to any
70
unnamed node. Looking at the netlist from
Figure 3.8, we see we are dealing with the same
Figure 3.7 - Schematic of the three-resistor circuit schematic design, components, component
in Figure 3.1 with net aliases removed.
names, and values, but instead of listing net names
" 17" and "84", as seen in Figure 3.6, the user is
provided with random net names, "NOOI25" and
"NOOI32", respectively. After creating the netlist,
the schematic design in the Design Entry window
will not change, regardless of the fact that net
names have technically been assigned. In effort
to synchronize the schematic design with the
newly created netlist, net names "N00 l25" and
• 5 0 UrCe U'ETLI ST "NOOI32" have been entered manually into the
V_V1 N0012 5 0 6
: R_R1 N00125 N00132 4 I e- o , O schematic design (see Figure 3.9). Now it is easy
R_Rl o N001 32 10 Ie-o,O to see the parallels between the original schematic
R_R3 o N00132 40 Ie-o,O
with included net names and the second schematic
with net aliases removed; in both situations the
Figure 3.8 - Netlist for the schematic in netlist is derived using the same basic format.
Figure 3.7 with arbitrary net alias names assigned
by the software to unnamed nodes.
R1
N00125 N00132
4
R2 R3
V1 10 40
6V .:...~
T
---.L
70
Figure 3.9 - Schematic design from Figure 3.7

changed to incorporate arbitrary net alias names.
3-6 Chapter3
RLe Netlist
To take this process one step furth er, a basic series RLC (consisting of
a resistor, an inductor and a capac itor) schematic design has been created
and net aliases provided (see Figure 3.10).
The first two exampl es
gave the read er insight into L
the layout of the element R
2 3
lines used for both a voltage 1k 10uH
source and a resistor. With
"1__
wc C
the int roduc tion of a ca -
pacitor and inductor into the J1n
schemat ic design, the same
general layout will be seen
with the new element line s,
but there will be a slight dif- Figure 3.10 - Series RLC circu it.
ferenc e in the nomenclature
used to describe these com-
ponents. The netlist has been
gener ated and can be seen in
Figure 3.11. :
The induct or element •
line reads L_L 2 3 10uh and
follows the same format as
the voltage source element
PAGEl
line. The L indi cates th at
this element line is that of .. source NETLIST
R R _ 2 lk TC=O, O
an inductor. Th is is followe d
by an underscore , then the L r. 2 3 l OuR
C C o 3 I n TC=O, O
component name used in
V VDC 1 0 14V
the schematic. The first two
num erical values are the Figure 3.11 - Netli st for the RLC circ uit from
nodal connectio ns of the two Figure 3.10.
terminal s of the inductor, and
the third numb er rep resents the compo nent's value, in this case , 10 !-tH.
The capacitor element line reads C_C 0 3 1 n TC =O,O and closely follows
the format of the voltage resistor element line. The letter C indicates that
this element line is that of a capacitor. Thi s is follow ed by an under score,
then the component name used in the sche matic. The first two numerical
value s are the nodal connections of the two terminals of the capacitor, and
the third number represents the componen t's value, in this case, ] nF (1n in
the netli st). Just like with the resistor, the temperature coefficient (TC) of

the capacitor can be modified so that the capacitor more closely mimics the
behavior of a real capacitor as opposed to an ideal one. This TC models a
change in capacitance with respect to a change in temperature in increments
of 1°C.
In Summation
At first glance, it may not seem important to dissect the netlist as we did
in this chapter. After all, it is easy enough to use the design entry features
of the DreAD software to draw a circuit to be simulated, but a thorough
understanding of the netlist will certainly help you with other aspects of
design and troubleshooting. A netlist provides an excellent representation
of all the interconnections within a design as well as the fundamental
parameters of these components. The netlist concepts discussed in this
chapter will be referenced later in this text.
3-8 Chapter 3
Chapter 4
Basic Simulation
Types
We now have a complete sch ematic design drawn in the Cadence

A lleg ro Design Entry or QrCAD Capture schematic capture software,
complete with node names, designated component values , and ground. At
this point, the user is free to begin any desired simulations or circuit analysis
of the schematic de sign. Later in this chapter, readers will be introduced
to some of the fundamental circuit simulation and analysis techniques that
can be utiliz ed in Cadence Allegro Design Entry and Allegro AMS Simu lator
(or QrCAD Capture and PSpi ce AID ). To explore these different simulation
type s, sample simulations wi ll be performed on the simple three-resistor
circuit de sign already constructed in Chapter 2 and shown in Figure 2.18 ,
in addition to three other schematic designs.
Bias Point
Th e first simulation to be conducted on the three-resistor circuit is
that of a Small Signal Bias Solution or Bias Point Calculation. This type of
simulation will perform voltage calculations from each node of the circuit
with res pect to ground, curre nt calculations within the circuit, and the
~ OrCAD Captu re CIS - Lite - [C:\ARRL\Cade nce Po

E.rnI File Design Edit View Tool s Place S
~ SCHEhtATlCl -3 Resisl "r 1t2Yf1 JV
Figure 4.1 - NEW SIMULATION profile button.
Basic Simulation Types 4-1

calcu lated power dissipated in each component of the circuit. Before the
circuit can be simulated, the user must set up a simulation profile.
To create a new simulation profile click the SHORTCU T button
highlighted in Fi gure 4.1. Clicking the NEW SIMULATION button presents
the window shown in Figure 4.2, which prompts you to enter a title for the
simulation you wish to run. Any alphanumeric combination can be entered
into the title box . In the NEW SIMULATION window, you see that the name "3
Resistor Circuit" has been chosen for this example, and it merely serves as a
descripti on of the schematic design. After choosing a name for the simulation
profile, click the CREATE button , which causes a window titled SIMULATION
SETTI NGS to open (see Figure 4.3). Note that "Simulation Settings" in the
title of this window is followe d by the name chosen in the new simulation
window, in the case of this example that is "3 Resistor Circuit". This is a
helpful feature offered by the Cadence software,
bec ause it allows the user to be mindfu l of the
New Simulation simulatio n paramete rs that are being altered. In
a case where analyses are being performed on a
Name:
Create
more complex design, the user can have more than
3 R esistor Circui~ one simulation profile in a project.
Cancel
Now let' s turn to the first simulation to be
Inherit From:
demo nstrated, the Small Signal Bias Solution.
In the active SIMU LATION SETTIN GS window,
Root Schematic: SCH EM.II,TIC1 select the ANALYSIS tab. Under that tab is a drop -
down menu labeled ANALYS IS TYP E. Open this
Figure 4.2 - NEW SIMULATION window. drop -down menu and select BIAS POINT to apply
the changes that you made to the simulation
profile. Now the simulation parameters
Simulation Setti ngs· 3 Resistor Circuit are in place to run the Small Signal Bias
I I~J ~' ::;:~ ==~ ==- =-
:::::;I==.~ =;:lo;;r-==
. CcIoctlo==
n==-;=Ip,w.==Wndaw
===:- j --~ Solution. After clicking the OK button,
~type . Ihxput File Ilptions you will be returned to the DESIGN ENTRY
[~pOri' " ·-. _,, ······--..-1.. . 0 [nclode detailed biee point information fornonlinear controred
J
sources and semiconductors (o P)
window. To run the simulation, refer to the
o Pelform2 en:.iliyityM1 a!y: i$ IS ENSj toolbar that spans the top of the screen and
~1..re (Sweep)
-l Save BiM Pm
click the button highlighted in Figure 4.4 .
I
1load £la, Port Notice that prior to creating a
! simulation profile, this button is grayed out
and cannot be selected. Only after creating
the simul ation profile as described in the
prev iou s paragraph will this button be
enabled. After clicking on the SIMULATION
button, wait a few moments for the
simulation process to complete. You will
Figure4.3 - SIMULATION SETTINGS window, Bias Point.
4-2 Chapter4
know that the simulation is complete
when the progress bar displayed on
the screen reaches 100%. Referring
to Figure 4.4 , note the three shortcut
Figure 4.4 - RUN PSPICE button . buttons to the right of the SIMULAT ION
button, labeled v, I and W. These buttons
toggle the labels for the calculated values
~ of voltage (V), current (I) and power (W)
R1 ..·
17 gathered from the simulation results.
j I DIm These values are displayed as labels on
the initial schematic design. All three
6V
'. V1
.:..c__
r 'CO
- [ J-
IIiI!El!i.'! S R2 J R3
mea surements have been toggled on
and are visible in the simulation output
shown in Figure 4.5.
In Figure 4.6 only the voltage
Figure 4.5 - Bias Point results displaying voltage, current measurement button has been enabled;
and power. therefore only values of voltage are visible
on the schematic drawing. These voltage
values are the amount of potential present
from the labeled point with respect to
ground. In Figure 4.7 only the current
measurement button has been enabled;
therefore onl y values of current are
visible on the schematic drawing . These
current measurements are the amount of
current present in the labeled path . In
Figure 4.8 only the power measurement
button has been enabled; therefore
Figure 4.6 - Bias Point results displaying only voltages .
only values of power are visible on the
schematic drawing. These values label
the individual components of the circuit
with the power dissipated within them .
IiI!IiI!m R1
When you compare the simulation results
17 64
4 seen in Figures 4.6 , 4.7 , and 4.8 to the
mI!I!1rlm... ..1Iil'iJ!m results seen in Figure 4.5, you will notice
V1
R2 R3 that the user can either display or hide
10 40
6V .:..c__ whatever value s are desired at a given
TIiE!I!m time. Similar to moving a component or
component label during the schematic
design process, measurement labels
can be moved to any destination on the
Figure 4.7 - Bias Point resu lts displaying only currents.

Figure 4.8 - Bias Point results displaying only wattages .
schematic page just by clicking and dragging. After the simulation has been
completed, if you wish to modify your design to obtain a different wattage,
voltage or current, you must edit the desired component values using the
method discussed in Chapter 2; you then simply run the simulation again .
DC Sweep
The next type of simulation covered in this chapter is the DC Sweep.
Using the methods discussed in earlier chapters, create either a new project
or simply add a new schem atic page using the option in the file menu , and
then draw the circuit shown in Figure 4.9 .
This is a three-resistor circuit with two de voltage sources. As we saw
in the previous simulation, the user is able to perform a Small Signal Bias
Solution to determine the voltage, current , and power in various points of the
circuit. The DC Swee p simulatio n allows you to vary a specific component
value and displa y an output plot of current, voltage or power based on the
specified or incremental changes in component value . After creating the
circuit shown in Figure 4.9, you must create a new simulation profile. This
can be done in the same manner as it was in the previous simulation. For
this example, the simulation has been titled "DC SWEEP 2V 3R". After
naming the simu lation , you are presented with the SIMULATION SETT INGS
window (see Figure 4.10),
In the SIMULATION SETTING S window, change the analysis type to DC
Sweep using the drop-down menu to display the simulation parameters shown
in Figure 4.10. For this simulation we will be sweeping the voltage value
for the dc voltage source labeled VRIGHT. To sweep this component value,
select VOLTAGE SOURCE in the SWEEP VARIABLE portion of the window, In
the NAM E text box to the right enter the component name that you wish to
sweep exactly as it appears in the schematic design . For this simula tion, we
will sweep VRIGHT from a v to 10 V in 0,5 V incremental steps . To define
4-4 Chapter 4
RLEFT RRIGHT
25
21< 1k
RMIDDLE
3l<
8Y
Figure 4.9 - Two-voltage source circu it.
:'.:"'IabonS<t!;ng• • DC~ lV.}R

~ ....,.w,.;.
~-
•
-
Ootionc o...CllIeda> PIobe Wrdow
- ~
",.w,.;. _: Sweep variable

......... ."._-------_.
!PCS;;;;;;;
~
m" l ~ I !~) ~oltage source tla me: VAIGHT

0 0 •
{) ,CuHent source
Qpl:ions:
........._.. -_... o parameter
!ilob~
Hodel ~:':jJe I -I
r
0
bi ' o ,Model oe emeter H.:,d,:tlm,l1l!!' '1

EJSecondaoy 5.......,
rJ fobte C5ICliWorstCase e> Iemperalure !:,'I .)r''\e l ~r n,~rr.!'"
EJP""""'"" S.......,
E]T- . . . lSweep) Sweep type _
....._......._._..__.. ....•
D Save Bias ?on S tart value: rN
(t ) !:ioecu --
EJIDa<! Bas P.... Endv.§Ue: lrN
~ Log,uitbmic ~~_::~. _.... J
increment .'N
, _ _ _ _ _ o _ _ _ _ _ _~ .
O Valueli:;t !
OQ ~ ~~ ~
Figure 4.10 - SIMULATION SETIINGS window, DC Sweep.
these parameters within the simulation profile, enter a start value of "OV",
an end value of " lOV", and an increment of ".5V" into their respective text
boxes. Since the sweep is across only a small range of voltage , select a
LIN EAR sweep type. A LOGA RITHMIC sweep can be selected to accommodate
a wide range between start or end values whether you are sweeping across
voltage, current or resistance.
Notice the text box at the bottom of the window labeled VALUE LIST;
if that is selected, it enables you to enter user-defined component values,
and the simulation will sweep across these values only while generating an
output. After entering the desired DC Sweep parameters , apply the changes
to the simulation profile and run the simulation. After the simulation is
complete, the Allegro AMS Simulator will open , display ing a blank page
where the output plot will be displayed (see Figure 4.11).
The simulation has performed a noda l analysis on the circuit as the
value of VRIGHT changes from 0 V to 10 V. Using the AMS Simu lator we
will note the impact of the change in voltage across the resistor RMIDDLE

• ... a
[Idene! ,.,
- YI I.
.~
.t .
V-,.'R1tiHT.1D
i
~~ J\w_X[ )
Figure 4.11 - PSpice A/DIAllegro AMS Simuiatorwindow, also referred to as PROBE .
as the sweep takes place. To

observe this change, select ADD
I(ALE FT) TRACE S from the TRACE menu.
I(ALEFT ,')
I(AMIDDLE)
I(AMIDDLE.' )
This will open the window shown
I(ARIGHT)
IIRRIGHT,1)
; Volage:
I in Figure 4.12.
I(VLEFTI _.: Curentc @
I(VLEFh l
I(IIRIGHTJ
ABS(}
ARCTA NII
The left column displays a
JZ Powef
I(IIRIGHh l ATAN( )
VIOl O tl oite r¥''ilIH: ! AVGI I list of measurements of voltage,
V 20 AVGXLI
Vl301
~ Aia: N amet CDSI
01 )
) current and power that can be
VlALEFT,')
VlALEFT,2) o SlbcfcUlINode1 DBll
ENVMI>XI. ) taken at any given node in the
VlAMIDDLE,,) ENVMIN{. )
VlAMIDDLE,2)
VlARIGHT,,)
EXPll circuit. For example, if there is
Gil
VlARIGHT'2)
V(VLEFhl
IMGt)
LDGll a trace expre ssion V(R1:1) listed
VlVLEFH LO G' ~ )
040 vaMbie: Isted
VlVA IGHh )
V(IIRIGHT:-l
Mil in the column, it simply mean s
MI>XII
FtJ Li:t that the trace to be plotted will
T rbCe E lCPfe aion ~l _ _ _I DKJ [c.ncd 1~ show a voltage measurement
from terminal I of component R1
Figure 4.12 - AD D TRACES window.
with respect to ground . Also take
notice that if you provided a net
alias to any node of the circuit in the schematic design, it will be displayed
in this list. In the case of this schematic design the node between RLEFT and
4-6 Chapter 4
RRIGHT has been given a net alias of "25". In order to display a plot of the
voltage across RMIDDLE , either find V(25) on the TRACE EXPRESSION list or
enter it into the text box as shown. Press ENTER to plot the trace. The ADD
TRACES window will close and the plot will appear in the AMS Simulator
window (see Figure 4.13).
The X axis labeled V_VRIGHT displays the swept voltage range defined
in the SIMULATION SETTING window as "OV" to " IOV". The Y axis displays
the range of calc ulated voltage across RMIDDLE . At any point , the user
can double-click any open space surrounding the X or Y axis to the AXIS
SETTI NGS menu (see Figure 4.14).
The AXIS SETTINGS menu allows the user to customi ze the AMS
Simulator workspace by selecting grid line types using the options under
the X GRID and Y GRID tabs or axis labels under the X AXIS and Y AXIS tabs.
cadence - " .
SD-IEMATICl.QCSWH P
1U 2U 3U su 6U 8U 9U , 1\1
.~- - - -- ._ . . . _ - - - - - - - -- - - - - - -- - - - - - - --- - - - -
~-----
'~C4ItDr; T,... ~
xv. ..
-
SI"t .O V} / RIGHT - 10 End. 10
~~J..~---
FOf ""' ~l fl 1....
Figure 4.13 - Plot of voltage measured from node 25 with respect to ground.

Using this window, the Y axis has been given the title "Voltage Acro ss
RMIDDLE" (see Fig ure 4.15).
You can now begin to interpret and analyze these simulation results.
One way to do so employs the CURSOR function of the AMS Simulator. To
enable the cursors, click the CURSOR button highlighted in Figure 4 .1 5. Note
the presence of two cursors on the voltage
.. _----~~-~
AxisSetting, trace. The cursors can be moved to any data

point on the trace visible on the plot. The
X Al<i, @ X Grid Y:...:G:;;rid:;;!~~~~~~~~~_,_~--,
l-I
left mouse button will move one cursor, and

o Automotoc the right mouse button will move the other.
M ~or Minor
Spocng Interval: between MaiOl
Figure 4 . 15 illustrates the operation of the
~ L~e..:r @2 10
4 cursors on a trace and demonstrates how to
~ Log l:t Cf...-cClC-:=;! 5
mark a data point. Two random data points
Grid, Grid,
~ l ine: '0 toee have been selected using each cursor. To the
AJ. lnter:ec tion: : At Intersections:
o Doh (; Qlhcr Wllho Dot: m3pl 0 WIth OI.her rMjof right of the button that enabled the cursors,
o+ 0 w.th otherm'nOf e:J + 0 \\',thother rnr,OI you will find a bank of buttons that allow
None e. None you to position cursors on various positions
fl Tic ks imide plot edge ~ Tick: in:ide plot edge
of the trace . The button to the far right will
0 11umbe<, "",ide plot edge
mark data points in ordered pair format at the
position of each cursor. In the bottom right
Figure 4.14- AXIS SETTINGS window.
corner of this window, note the presence of a
cadence - " x
SQiEMA.T ICHlc
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C.....Of(/.IJ\OrCAOJ&.5_llfc',tocll\c~. .~~~MATIC1~{KtIW)
- -
= 10
- -- - -- - - - - - - ---
100"'"
Figure 4.15 - V(25) tracewith markeddata points.
4-8 Chapter 4
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.. U( 25 )
10 2. 3U . •-
Su
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" •• l OU
Figure 4.16 - Plot copied to clipboard.
sma ll spreadsheet window. Thi s spreadsheet window will ident ify the X and
Y values based on individual cursor positions, allowing you to view exact
values according to simulation results without having to mark a multitude of
data point s. However, for the purpose of this example, two data points have
been marked based on cursor pos ition. At the instance when component
VRIGHT is equal to 4.1 770 V, the voltage across resistor RMIDDLE is 448.914
mV, and when VRIGHT is equal to 5.1770 V, the voltage acro ss resistor
RMIDDLE is 96 .514 mY.
Based on the screenshot of Figure 4.15 , you may find it hard to decipher
marked data values or read a plot with multiple traces. To mak e this process
eas ier you may refer to the AXIS SETTINGS window mentioned earlier and
impl ement changes to the gridlines to make the plot more legibl e. If you
wish to cop y the output plot of the AMS Simulator to another document,
simply use the WINDOW menu and select COp y TO CLIPBOARD ; this will
open an active window that lets you select the color scheme for the copied
plot image. To demonstrate the se changes and how they can be applied, the
gen erated plot using these features (a black and whi te image with minor
grid lines removed from the X and Y axis) is shown in F igu r e 4.16. Not e
that the layout of the trace , axis, and labels is identical, but the plot is much
easier to read . No te also that the X and Y values of the two marked data
points remain intact as well.

AC Sweep
The next analysis to be discussed is the AC Sweep. This simulation
allows the user to provide a constant value of ac voltage to a circuit while
varying input frequency across a defined range. Figure 4.17 is a schematic
design of a simple RLC tank circuit.
This circuit design uses components that have not been used or seen in
previous examples. These components, as listed in the PSpice component
library, are the ac voltage source VSIN, capacitor C, and inductor L. In creating
the schematic, you can define these component values using the same process
described in the beginning of the chapter. Using the ac voltage source VSIN,
you have the option of applying an offset voltage and setting amplitude,
frequency and ac voltage . You're given the option to apply an ac voltage value
and amplitude because the ac voltage value is used as a constant value for the
AC Sweep simulation and because the values of amplitude, frequency and
offset voltage are used for other simulation types. One of these is Transient
Analysis, which will be discussed at the end of this chapter.
Note also the presence of the resistor component R2. This is not a
typical design for an RLC resonant tank circuit, but the Cadence software
will require the presence of this resistor as it sees the inductor in the same
series path as an ideal component with no internal resistor. Component
R2 merely simulates the internal resistance of a real inductor. Running
a simulation without this series resistor will result in an error, since the
Cadence software will see a branch with a 0 n internal resistance. Once
the circuit is complete, create a new simulation profile just as was done in
the previous examples. Again, you will open the SIMULATION SETIINGS
window after naming the simulation (see Figure 4.18) .
R1
1
W'v
1k
IV1
L1
1mH
1
I
i'
VOFF=1V C1
VAMPL= 1 "v .2533uF
FREQ= 10kHz
AC=1V
R2
3
Figure4.17- RLe tank schematic.
4-10 Chapter 4
Simulation Settings - AC Sweep Tank Circ uit (gJ
£>,nalysis type: ' ACSweep Type - - - - ·

1ACSweep/ Noise iv 1
r o j,inear -S.tartFrequency: 15kHz 'I
.Qptions: , 0 LQgarithmic I nd Frequency: 115kHz 1
I IDecade "I 1I
~onle
GeneralSettings Points/Qecade: 500
CarlolWorst Case L 1
-.J
D Parametric Sweep r Noise Analysis - - - - - - -
D Temperature (Sweep)
D Save Bias Point i D Enabled 0ld'putVo!tage
D LoadBias Point
L
I/y.Source.
-:=J
[ntervel
_______ J
Output File Options

D In" lude detailed bias point information for nonlinear
controlled sources and semiconductors [.0 PJ
'----- - ----
OK I[ Cancel II Apply II Help
Figure 4.18 - SIMULATION SETTINGS window, AC Sweep.
"""""""1n'll~ ·..... ~ ' r01t·~

i.'- t* r_ ~!r-_tt.c t p W. . . ttaff 'i. cident; - 6-=i
113 • I.:) a
~ j .. • .JQ
, ("",..."e,,,,-,, '1_
Ie< ~ &\ til. " • Ow Yl ... E3 .! ~s :e~ lii li..... _ ... __ ... .. ~ I
...-
•
~
e.
"'-~I
1
gUIRU
I" " "'." "''''I
~ ; / \
.i"- / \
l'jo
I
.au"""
e
u_
.:
I -. <,
..- - ~ I-""
.--/ '-----.......
-
...., I-
5lUIz ,,(.z 1KHz ..., 'KNz ' • •.1 1tKHz 121 MI' 13ICK: 1W.% 15KHz
'''liz
'.
• IIJU)
._ . -- ... -- . .- _.- - --- rr e qv.nc, _ .- .-_ . --- - - - --- - - _. - -
• ""'-J
*HIfI\..... n
Figure 4.19 - Voltage measured from node 2 with respect to ground (across the LC tank branches).
X40..ou ".un Fng. UJO(o4] .- '-
Basic SimulationTypes 4-11

For the purpose of this example, the simulation has been titled "AC
Sweep Tank Circuit," as indicated in the title bar of the SI MU LATION
SETTI NGS window. Using the ANALYSIS TYP E drop -down menu, select AC
SWEEP/NOISE. Enter a start frequency, where the AMS Simulator will begin
plotting measurements, and an end frequency, where the AMS Simulator
will stop . The text box labeled POINTS/DECADE will allow you to define
the resolution of the plotted trace . This value represents the number of data
points per decade across the frequency spectrum; the greater the number
of data points, the higher the resolution and definition of the plotted trace.
Points per decade can be changed to points per octave depending on how
you wish to view your outp ut plot. Lastly, since we are sweeping across a
wide frequency range, the logarithmic sweep type has been selected. After
applying these changes, the circuit is ready for simulation.
Run the simulation and plot the voltage measured from net alias "2"
using the TRACE EXPRESSION text box in the ADD TRACES window. Again,
this trace expression, V(2), can be found either in the list to the left of the
ADD TRACES window or entered into the text box. This trace represents the
output voltage of the resonant tank circuit as the frequency changes from
5 kHz to 15 kHz . The X axis of this plot represents frequency and the Y
axis represents the measured voltage from net alias "2". To provide a more
user-friendly, legible output plot, the grid lines have been altered and the Y
axis has been titled "Voltage Net Alias 2" (see Figure 4.19) .
In the previous example, the CURSOR tool was briefly mentioned; we'll
enab le that now. The bank of buttons to the right of the CURSOR ENAB LE
button in the top toolbar accesses the cursor placement tools . The button
to the immediate right of the CURSOR ENABLE button will drop the cursor
at the maximum voltage value of this parabolic curve. In Figure 4.19 , the
maximum value of voltage has been marked using the button to the far
right of the toolbar. This maximum value occurs at the resonant frequency
of this circuit. Since inductive reactance increases as frequency increases
and capacitive reactance decreases as frequency increases, there will only
be one frequency where these two reactances will be equal.
Again , the peak of this curve indicates the resonant frequency and has
been marked with an ordered pair. The X value of the ordered pair at the
peak of the curve is measured at 10,022 kHz . This tells us that resonance
occurs at this frequency. The measured voltage at this resonant frequency,
the Y value of the ordered pair, is 568 .809 m V. This plot is once again
generated in grayscale using the COpy TO CLIPBOARD function and can be
seen in Figure 4.20.
4-12 Chapter 4
U"IIIU
~m)7
0
1\
1
··
t (,OlJ56K,567
9 SlIaU
·" ....
H
•1
/ \
·•
i
$,.""" I
1/
\
...... / ~ <,
...... /
V '----- h..
r======
...
'" , II \1( 2 )
~
51Hz
-----
611Hz 7KHz 111Hz 911Mz 1• • z
f r.qufnc y
1111Hz 12KHZ 1U Hz 11HtHz 1SkM:r. 16Klfz
Figure 4.20 - Plot copied to clip board.
Transient Analysis
In the final example of this chapter, an RC circuit will be connected to
a pulse voltage source, and an analysis of circuit voltage versus time, called
a Transient Analy sis, will be performed. The pulse voltage source has not
been seen in prior examples. The component is listed in the PSpice library
as VPULSE . The result of the Transient Analysis will appear in the output file
in tabular form and as a graph of voltage versus time . The circuit is shown
in Figure 4.21 .
The single pulse input source goes from 0 V to I V after 10 us of
RA
~1
1
V1 -ov V1
V2=1V CA
TO= 10u
TR=1n
JL T 20n
TF= 1n
PW =80u
Figure 4.21 - RC circ uit with pulse voltage sou rce.

delay (relative to the beginning of the Transient Analysis), with rise and
fall times of I ns, and has a duration of 80 us, As in the previous examples,
you mus t create a new sim ulation profile. Start by naming your simulation.
For the purpose of this example, the sim ulation has been titled, "RC Pulse
Transient," as indi cated in the title bar of the SIMULATION SETT INGS window
(see Figure 4.22).
- - -- -- - ,,'< ~
~ -~
Figure 4.22-
SIMULATION
SETIINGS window,
Transient Analysis.
160u second: (TSTOP)
ITrnelloman (T. - r t l · 1 RlXlto lime:
Qooons;
SllJfl savi-,odo!ta "' Iel: -0 - - second:
Tra-u:ient optiom
1':I _ . CaIoIW"",c... Maxirntrn:lt? size: 50 second:
I':IP- 5we<l> EJ Skip the i'IiI:~ trMsient bias point caeutation (SKIPB?)
!':I T.......-e (Sweep)
I':lSave _ Pcri
I
E1Load& , Fcri
EISave 01ec:k Peri,
[ ] Run in resumemode
IO...... F.. O~· 1
[J Re" "' SinUalion
Figure 4.23 - Voltage

~~~~tt~~~~i:~~~==l2::==---- ~ci!.l!d.!:.!.n!.lC"E....:.• .;;.•..:;.
x measured from node
!'! 2 with respect to
...
-- I
ground.
/ 1 \~ l.,.!If1tJWoot
1 .'1
....
i/ \ I
'.M
1
/ 1\ I
I .:'
/ ~I
~
.. Illl( ~)
/ .... .... .... ....
u•
.
,. , U'IlI "
,-------
... 16 ""
.~
1_ _ • n::l:G I__ * 1iI«

f .... ~Ioll « .. ...._ --,.-
- ..... ~ *IO"",....f_ ..
.......
......,
e-....................... _
"*"-'c... _fl:t t _ .....
1 •• \ "..,.,."Jl.w.- xc;:..]
I :::::=:.....
1, 1 .,.......)I~ ~-
,'=- ~
..
4-14 Chapter 4
U 1. DU
~ r---
-: \~
D
1 !mu,961 .63<l m)
t
•9
e ' .8U
O.6 u
/ \
l .ltU
1
/ \
/ ~
<.
---
1 .2U
011
Is
• U( 2)
/ 2llus "'Ous 6 Gus 8 Gus
li,..
1 0 005 12Cl.ls 1JtDus 160Us
Figure 4.24 - Plot copied to clipboard.
In the SIMULATION SETIINGS window, select the TIME DOMAIN analysis

type using the drop -down menu . To accommodate the pulse width defined
in the schematic design, a total run time has been set to 160 us. Data will
be calculated and plotted starting at time 0 s. The step size will define the
resolution of the trace displayed on the plot, and a smaller step size will
yield a higher resolution as there will be smaller incremental steps between
plotted data point s. The step size chosen for this simulation is 5 us. After
appl ying these changes, the circuit can be simulated.
Figure 4.23 displays the measured voltage from net alia s "2" from the
RC circuit. Thi s plot demonstrates the change in voltage as time progresses
from 0 s to 160 us. The Y axis has been labeled "Voltage," minor gridlines
have been removed to mak e the plot easier to read, and the maximum
voltage has been marked. The order ed pair reads (90.001 u, 981.835m).
Thi s indicates that the maximum voltage, 981. 835 mV, occurs at 90 .001
us. Lastly, the plot has been pasted in grayscale with these format changes
in Figure 4.24.
In Summation
These four basic simulati on types are the crux of this text, and it is of
the utmost importance that you develop a level of comfort with these before
reviewing the examples in later chapters. Being able to carry out each of these
simulation types can tell you a lot about the behavior of a particular circuit.
Basic SimulationTypes 4-15

Chapter 5
Netlist Control
Lines
By now you should be getting accustomed to operating the PSpice user

interface. You have been pre sented with an introduction to a circu it's netl ist
and are familiar with the most basic simulation procedures that the PSpi ce
software has to offer. Now that we have cove red the se basic simulation
techniques, we can delve further into the topi c of the netli st.
The Complete Netlist - Bias Point Simulation

As discu ssed in Chapter 3, yo u can develop a schematic layout in a text
format using what we have referred to as element lines. In addition to these
element lines , control lines can be added to a netlist to describe a simulation
type and to list its parameters. In this chapter, we will review each of the
simulations covered in the previous chapter and view the control line s that
were inad vertentl y added to the netlist durin g the simulation proce ss.
Our first circuit (see Figure 5.1 ) is the simple three -resistor circuit used
to demonstrat e the Small Sign al Bias Soluti on. In the last chapter all the
circuit currents, voltage drop s and power dissipations were made availabl e
in the Allegro Design Ent ry or DrCAD Capture
Rl software. Now we will view the simulation results
64
attached to the netli st in the Cadence Allegro
AMS Simu lator or PSpice AID window. Th e
R2
10
R3
40
circuit shown in Figure 5.1 had been drawn into
the Design Ent ry software, saved as "3 Re sistor
Circuit" and simulated using a Small Signal Bias
Soluti on simulation profile titled "3 RESISTOR."
After running the simulation, you will see the
Figure 5.1 - Three-resistor circuit schematic. simulation results just as you did in the previous
Netlist Control Lines 5-1

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Figure 5.2 - Simulation output file, Bias Point.
chapter, but take note of the blank AMS Simulator window that opened
after the simulation was completed. Bring the AMS Simulator window to
the front and click the button highlighted in Figure 5.2 on the toolbar to the
left side of the screen. This button is labeled VIEW SIMULATION OUTPUT FILE
and displays a text representation of the simulation result. After clicking
this button, the blank AMS Simulator window will change and you will be
presented with a window that closely resembles that shown in Figure 5.2.
The top portion of the screen should look familiar. It is the same netlist
that was tested in the netlist chapter. This netlist is followed by a simple
command, .END. This signifies the end of the netlist and will be seen at the
end of every circuit netlist that is simulated in the software. This particular
simulation type has no control line. With no control line present, PSpice
will carry out a Small Signal Bias Solution by default and will consider
the presence of a de voltage source and perform the associated dc bias
calculations at each node of the circuit. In the instance of a circuit that is
purely ac, you will see a Small Signal Bias Solution in this window, except
that all of the de values will be listed with a magnitude of O.
Just to clarify and help you clean up the layout of this netlist, note
that any lines of the netlist that begin with * or a series of multiple *
chara cters (such as *****) are insignificant to actions of the netlist. The *
symbol denotes a comment line and can provide the user with helpful notes
regarding the construction of the circuit or parameters of the simulation.
The comment lines displayed above them in this figure are a direct result of
simulating the circuit using the Design Entry schematic capture software and
5-2 Chapter 5
are generated at the same time that the PSp ice software creates the netlist.
In these comment lines, we have the date of the simulation, the destination
of the source file, a title heading for the Small Signal Bias Solution results,
and the default environment temperature of the simulatio n.
At the bottom of the screen , each node voltage is listed, followed by the
total circuit current and the total power dissipated in the circuit. These are
the same values that were seen in the previou s chapter when the simulation
results were viewed in the Design Entry window.
The Complete Netlist - DC Sweep Simulation

Next we will examine the control line used in the netlist for the DC
Sweep simulation type . We will follow the same succession as we did with
the previous chapter, so the second circuit will be used to illustrate this
concept. The circuit shown in Figure 5.3 was drawn in the De sign Entry
software, saved as "DC Sweep 2V 3R" , and simulated using a DC Sweep
simulation profile titled "DC SWEEP". As in the last chapter, the voltage
source VRIGH T will be swept from 0 V to 10 V in increments of 0.5 V. These
values were entered into the SIMULATION SETTINGS window prior to the
simulation of this circuit.
As usual , you are presented with a blank AMS Simu lator window. As
was done with the first circuit, click on the VIEW OUTPUT FILE button at the
left of the screen to view the output file (see Figure 5.4). At the bottom
portion of the screen, the element lines of the netlist are visible. The control
line is seen toward the top portion of the screen and reads as follows:
.DC LIN V_VRIGH T OV 10V .5V
The first component of the control line, .DC, designates that the
simulation will be a DC Sweep; LIN mean s that this will be a linear sweep ;
next it is declared that the component to be swept across is the voltage source,
VRIGHT, referenced in the netlist as V_VR IGHT. The last three numerical
RLEFT RRIGHT
20 25 30
2k lk
l VLEFT RMIDDLE VRIGHT

10V -=- 3k --
8V
T
I
1-
-0- 0
Figure 5.3 - Two-voltage-sou rce circui t.

cadence - iJ )(
Loca l Llhrarlf!'S
Fro. [PSPlCE KETI.IST ) s ection of C '-OrCl~AD_ 1 f> 5_Litc'tools'PSPlce' E'Splc c . i n l t i Ie :
I . h b "no.d . h b "
.. .. .. P.ESUHIIIG "OC SVEEP.cu o .... .. .

E1ID
J0 8 CONC1.00ED
........ 0<4/01/ 12 22 · 4 9 2<4 E'Sp lce La t e ( l p r l l 20 11) IDI 10813 • • • •
. .. Profi le : "SCHElfl T I C1- OC SIlEEP" [H : ' Chapter"J F l g ur e :s' OC Svee p 2Y 3R-E'Sp lceF i le:s 'SCIl EKATI Cl 'OC SVEEP . Sla 1
J OB STATI STI CS SUMMARY
. 11
".''':S\''EI' ~
for Hllp, P"!" Fl V'IF1GHT=1 0 10')<'
Figure5.4 - Simulation output file, DCSweep.
values are the parameters that were entered into the SIMULATION SETTINGS
window, and they state that the voltage will be swept from a starting value
of 0 V de to an ending value of 10 V in 0.5 V increments.
The next line , .PROBE, writes the simulation analysis result s to an
output data file. The line following this, .INC, declares the source schematic
file. At the very bottom of the window we see the .END comm and signifying
the end of the netlist.
The Complete Netlist - AC Sweep Simulation

Next we will inspe ct the control line used in the netli st for the AC
Sweep simulation type, referring to the third circuit from the last chapter to
demon strate the usage of this control line. The circuit shown in Figure 5.5
was drawn in the Design Entry software, saved as "AC Sweep Tank", and
simulated using an AC Sweep simulation profile titled, "AC SWEEP TANK
CIRCUIT".
After running the simulation and opening the simulation output file,
you will be presented with the window shown in Figure 5.6. Similar to the
output file of the DC Sweep , the control line is at the top of the wind ow, the
netlist is in the middl e, and the Small Signal Bias Solution is at the bottom.
The circuit shown in Figure 5.5 utilizes an ac voltage source, V1. This ac
source outputs a I Vpk-pk sinusoidal waveform with a + 1 V de offset. As
5-4 Chapter 5
R1
1
'1M
1k
L1
I 1mH I
V1
1
VOFF = 1V
VAMPL =1 'V
FREQ= 10kHz
AC =1V /' R2
T
C1
2 533uF
Figure 5.5 - RLC tank circu it.
cidenc e - ~ )(
• • n~l"$is d U ec t l VOS '

I.e DEC sao Sit 1<;\0;
PROBE V{o lias C"» 1 ( 4 11 0 1:(. » ll(", llIl.S( " » D(alill= (.» NOI S E ( a ll a l'i{* )
INC ' . . 'SCHEHU I Cl , net ·
• ••• INCLUDING SCHEHATICI . ne t .......

.. ecurce AC SVEEP TANI(
_VI I I) Ae I V
S UI IV I V HlkF.:: 0 0 0
Rl 1 a 110. Te - O. (1
11 2 HU H' laN
_Cl 0 2 , ~ S:n "F rc- e.e
R_R2 0 NIU H 3 rc- e. n
..... RESUHIllG · l e S1JEEP TAIIl( CIRCUIT .c i r " . ...
o EIID
; 04 /01 1"12 23 :06 :0 4 • • • •••• PSplce LIte ( Apr l1 2011 ) lOS 1 081 3 ..
• • Profile ·SCHElllTICl-lC S'lIEEP ntu: CI RCUIT" [H : '.Cha p t er 1 Flgure:' AC S. ee p' lC SVEEP TANK- PSPl ceFl1l!'s'<SCllElllTICr...\C SVEEP TAKX C
SKill SI GNAL BIlS SOLUTION TDtFEP.1TURE " 27 000 DEG C
MODE VOLTAGE MODE VOLTAGE NODE VOLTAGE
. 00 1 0 ( MI U h ) . DO-sa
I JCsww _ ~H: swm .

for Htlp..ptlKH ,."
Figur e 5.6 - Simulatio n output file, AC Sweep.
previously stated, the PSpice software will always perform a Small Signal
Bias Solution. The presence of this offset voltage will contribute de nodal
voltage s that will be seen in the Small Sign al Bias Solution.
The construction of the netlist is relatively straightforward, and we now
understand that the node voltages seen at the bottom of the window are a
direct result of the de offset. This brings us to a discussion of the AC Sweep
control line. The AC Sweep control line reads as follow s:
.AC DEC 500 5K 15K

The beginning of this control line, .AC, tells us that an AC Sweep will be
performed, and DEC declares that the X axis of this frequency response plot
will be divided into decades, as opposed to octaves, across the logarithmic
scale . These prompts are followed by three numerical values that further
define the parameters of the AC Sweep simulation. These are the same
values that you entered into the simulation settings window in the Design
Entry software. The numerical value 500 states that there will be 500 data
points per decade, and the last two values, 5K and 15K, set the range of the
frequency sweep that occurs during the simulation.
The Complete Netlist - Transient Analysis Simulation

RA
Now we move on to the fourth circuit of the previous
~
chapter, which simulated a simple pulse voltage across
an RC circuit. The circuit shown in Figure 5.7 was drawn
V1=OV into the Design Entry software, saved as "RC Transient"
V2 =1V CA
ID=10u 1n and simulated using a Transient Analysis simulation
TR=ln
TF = 1n profile titled "PULSE TRANSIENT".
PW=80u
Upon opening the simulation output file shown in
Figure 5.8, you will observe a layout similar to what was
-=- 0
seen with the previous simulations. The control line is
Figure 5.7 - RC circuit with pulse voltage
source . near the top of the window, the netlist is near the middle,
cadence - il X
Pre hl e l lbrarl e :
Local I. l b r .-.:ru.s
Fro. [pe..PICE MrrlI ST ] section o f C "'OrCAO'OrCAD_ll> . S_litet"t ool: '-PSP l c.e" PSpice il'lo1 ti le :
. li b " noad. .lih "
Analvs 1s d Irec tives "
TP.AM 0 rs ac c Su
PIlOEE Vea lills e* » 1(.11•• C"» VC",1i4SC * l ) DC.lusC .» KOI SE( 6lia s ( * »)
I KC ' .. '5CHEl!Io.TICl .DOt"
••• I NClUDI NG SCHElU.T I Cl . ne t ••••

.. s o u r ce F.C PULSE TRANSIEMT
Rl 1:2 lk TCa O. O
_0 I) 2 In TC- O. O
_ VI 1 o
.;; PULSE C'J rv icc 1!"1 In \lOu
••• • RESUHING " Re TrllnS l ent .cir " • • • •
"""o END
..
.,,
• · 04/ 01/ 12 23 15 -2 6 PSpiee LIte ( Ap r i l 2011 ) ••••••• IDI 1 0 Bl :1 It
...
•• Pr ofile : "SCHEIU.TIC I -RC Tr an sient ' [ H, '-Cha p t e r J Fi9ure .. "Tran~ i ent "J\'C PULSE TRANS IENT- PSp l eeFil e s " SCHElfATI C1'RC Tr "'n::nent . si a 1
, I NITIA L TRANSI ENT SOLUTION TEKPERATURE ~ 27 ,000 DEG C
..'".
r
~'-i NODE VOLTl GE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
" 1) OOIlOQ ( n 0 ecce
~ l'lR::T_ ,--- - - - - -- - - - -.J

-- - - - - - -
Figure 5.8 - Simulation output file, Transient Analysis.
5-6 Chapter5
OCSWEEP2V)R.bt - No< Figure 5.9 - Complete
NAt £de" FOfmIt V.ew Http netl ist file for DC Sweep of
OCSWEE.P2V3 R. CIR two -voltage -source circ uit,
V_Vl EFT 20 0 10
FLRlEFT 20 25 2k: TC-Q . O
created in Notepad.
FLR.'4I DDLE 2 5 0 3k TC-o,O
FLRRIGHT 25 30 lk TC-O ,O
V_VR I GHT 0 30 8
• DC V_VRIGHT 0 10 • 5
• P ROBE
. [ Nq
l n g, Col S
and the Small Signal Bias Solution is at the bottom. We saw the impact that
an offset voltage could have on the results of a Small Signal Bias Solution
in the previous example. In this example, there is no de potential; regardless,
the software carries out the Small Signal Bias Solution and labels the value
of voltage at each node as 0 V.
Looking to the top of the window, we see the control line for the
Transient Analysis simulation profile , which reads as follows:
.TRAN 0 160u 0 5u
The command .TRAN mean s that the simulation will be a Transient
Analysis . The next two numerical values define the range of time for the
simulation. In accordance with the example, the simulation will run from 0 to
160 us. The next number, 0, means that simulation data will be saved starting
at the time of 0 s. The last number, 5u, is the step size, which as discussed in
the previous chapter, helps define the resolution of the output plot.
Simulating a Circuit Using a Netlist File

After reviewing all the exampl es put forth in this chapter, you may be
wondering why it is necessary to be able to interpret netlist data if the PSpi ce
software can create netli st data for you during the simulation process. With
a solid understanding of the concepts of different element lines and control
lines , you do not need to dra w a schematic into the Design Entry software
and use the schematic capture function of the PSpice software to generate
and simulate the netli st. You can begin by creating the netli st in a text
document and simulate the circu it using just the Allegro AMS Simulator.
This procedure will be demonstrated below using the dc circuit from the
second example (Figure 5.3).
In Figure 5.9, a text file using the Not epad program has been created and
saved as "DCSWEEP2V3R". The top line of the netlist that we will create

will be the name of the circuit file that will be simulated. You may choose
any name or reference you like, but it must be followed by the suffix ".CIR"
(DCSWEEP2V3R.CIR). Next we have the element lines that describe the
interconnections and values of the components that make up the schematic
design. In an effort to keep this example as simple as possible, the names
refe rencing the individual components of the Figure 5.3 circuit have been
kept the same and match the element lines shown in the simu lation output
file in Figure 5.4. Next we have the DC Sweep control line followed by our
probe com mand and end command. Notepad saves files as text format (.txt
extension). After saving the Notepad document, using your desktop browser,
go to the destination of the text file and change the extension from ",txt" to
".cir."
When creating a netlist, it is important to use a simple text editor such
as Microsoft Notepad or WordPad. If a user tries to create a netlist in a more
complex word processing program such as Microsoft Word, Corel Word
Perfect, or Apple Pages, any simulation will likely fail due to the presence
of hidden characters saved in the document for page formatting purposes.
Next, open the A llegro AMS Simu lator and selec t OPEN in the FILE
drop -down menu. Select the destination of the netlist text document that you
have just created. In Figure 5.10, the newly created text file is visible in the
IJf Open .
1 Name Date modified Type

~j
L.~ " • .._ _. •
i'!iJ DCSWEEP2V3R 4!l12fJ12 12:01 AM CIRFile
Recent Places
Desktop
Libraries
Co mputer
4 C:: -- ~----l ii - ----- - - ~
Networlc
Rename:
Open5!s:
Figure 5.10 - Netlist fil e from Figure 5.9 as seen in OPEN window.
5-8 Chapter 5
DCSWEEP2V3 R• PSpi« AIDl it• • IDCSWEEP2V3R (active») OPEN window. Note that since
i ~ f ile Edit ~ew ,Sim ulation j rece Elot T,Qols ~indow Help
the file extension has changed,
the icon now resembles that of
a schematic design file; note
also that under the file type
CSVEEP 2V3R . CIR
V_VLEFT 20 0 10
R_ RLEFT ~ O 25 2k TC= O. O
column , this document is listed
R_ RMID DLE 25 0 3k TC- O. 0
R_ RRIG HT ~S 30 1< TC= O. 0 as a "CIR File" . Open this file
V_ VRIGHT 0 30 8
.DC V_V RI GHT 0 10 . S to create an active window that
. P ROBE
. EllD resemble s Figure 5.11.
The netlist that was ju st
created using the text editor
is now vis ible in the AMS
Sim ula tor window. At the
top of the window, pres s the
Figure 5.11 - Netlist active in the AMSSimulator window.
green button labeled RUN.
This will simulate the circuit
file outlined in the netlist as
Add traces
S ~ O ul pul V_ FlI'lCtion: MacfO:
01
"DCSWEEP2V3R".
IAnalog0""0"'"arcl FUldions ~ I After the simulation is
IIR_RLEFTI
0 " noloo
. complete, you will be present-
. II
IIR_RMIOOLEI []
IIR_RRIGHT)
:~_VLEFT )
O f!iootol ed with a blank output plot as
I VRIGHT 0 y oltaoc:
I
V(25)
I
@
in the previou s chapter. Now it
til u.,renl:
V(30)
V VRIGHT
ABSIJ
ARCTANI)
is easy enough to resume using
~ .Eowef
WiR_RLEFTI ATANI )
W{R_RMIDDLEI D II ,;,c (V'/ H, J AVGI) the software as if you had ju st
WJR_RRIGHTI AVGX( . J
W(V_VLEFT) D ,6Ji~$ tl".lme* COSI) simulated a schematic using
W(V_VRIGHT) 01)
O ~ubm:ut Nodes OBI)
ENYMAX(. 1
the Design Entry software.
ENYMINI. I
EXPIJ Open the ADD TRACES menu
GI )
IMGIJ (see Figure 5.12 ). Since our
LOGI)
14 varlOO!e:~:ted
LOG10{) text netlist kept the same
FullLi:1
Mi l
MAXI ) - component names and node
names, we see all of the
j rece EXple: :ionL ______
-- - .. -_.. i []D 1 ~c1 l lliJ
available trace s that we saw
"0
Figure 5.12 - ADD TR ACES window. when we ran the DC Sweep in

the simulation chapter.
Figure 5.13 is a screen capture of our netlist simulation with a voltage
trace measured from node 25 with respect to ground while VRIGHT is
sweeping. This plot shown below yields results that are identical to the plot
of this circuit from the previous chapter generated from a schematic capture.

cadence - ~ x
~
~ -~ YI
= ! ,!;2.. ~ !
-
~:i. eu
: ···•
~
I
e
2."
r-.;
--..........
. .. r---
= --------
-------
-1 .1lllJ
------- <..,
-- .
- 1 . etl
~
-Z .CII
-- ~
- ~ . CU
..a V( U } " 2. 3V
" 5.
U WAlGIJI
6.
" •• , , ..
!;)tcmc.El'_ . OCS\~1:.
H.\(~";'~ 3 F""' fllJ~J)Cs:....1E'~ I'dNd
_
. . __..... ._- ... . . ..
X=«J)Y,,>4MJ V ~'~ = 10
.
"
Figure 5.13 - Probe graph developed using the netlist file.
In Summation
This concludes the overview of the netlist. Between the material
represented in this section and Chapter 3, a user can begin to understand
how the layout of a schematic design and corresponding simulation profile
can be written in text form. An understanding of these concepts can only
better help you carry out routine simulation procedures using the OreAD
software and the PSpi ce user interface.
5·10 Chapter 5
Chapter 6
The PSpice
Probe Tool
The two main goals of the previous chapter were to familiarize the
user with the Cadence user interface and present four basic exampl es
incorporating different circuits and simulation types. In this chapter, we
will explore some of the capabilities of the Cadence Allegro AMS Simulator
or PSpi ce ND utilizing the PROBE tool in the Cadence Allegro Design Entry
or OrCAD Capture software.
Adding Measurement Markers to a Schematic Design

To begin, the circuit shown in Figure 6.1 is constructed within the
Design Entry software. This circuit uses the same component values for the
L1
C1
r--------'~I 1mH .2533uF
V1
VOFF =OV
VAMPL = 5V "-'
FREQ = 10kHz > R1
AC= 1V 30
Figure 6.1 - RLe tank circuit schematic.
The PSpice ProbeTool 6-1

capacitor and inductor as the RLC tank example from Chapter 3; however,
this circuit maintains a series configuration.
A Transient Anal ysis will be performed on the circuit, plotting a
sinusoidal output in the AMS Simulator. To achieve the desired output so
that we have more than two completed cycle s of the output waveforms, a
runtime of 300 !!S is declared. The plot will begin at the time of 0 s, and to
provide an adequate resolution to the output plots, a step size of 300 ns has
been selected. The simulation settings are shown in Figure 6.2.
After running the simulation, the Allegro AMS Simulator will
automatically open. After the simulation is complete, you can bring the
Design Entry window to the front and display the original schematic design .
In Figure 6.3, PROBE tools have been highlighted in the toolbar that spans
the top of the screen . These probes designate the output traces that will be
plotted in the AMS Simulator window.
The first probe to be placed on the schematic design will be a single -
voltage measurement probe. Select the PROBE tool to the far left in the bank
Simulation Sottings- Fim Example
Bun la tme: <econ<l> ITSTOPj
~Iafl .avi-lg dataoller. -0- - <econ<l>

~:
I,.."ienl options
rl MorteomN/ont e- Hamun ,lep a:e: ~ ,econd,
~ I'a1ornelric Sweep
~ T~ (Sweep)
~ S- 8M Por'll
rlload 8M Por'll IO\ljl<.tfie Oplq ",.. I
O S- Oled< PoilU
E:]ReotlldSI1dotion
OK 'I Coned I C~ [ ~ =,I
Figure 6.2 - SIMUL ATION SETTINGS window,Transient Analysis.
OrCA!) CaptureCIS- lIte· (I· (SCHEMATlO : PAGEl ))

~ file fdit y,... Iools fl a", Macro PSpice Accessories
Figure 6.3- Measurement markers.
6-2 Chapter 6
of probes . Hovering the cursor over this PROBE icon will display its name ,
VOLTAGE/LEVEL MARKER. This voltage probe is placed on the node in the
circuit labeled as net alias" 1" (see Figure 6.4). When a single voltage probe
is placed into a schematic design in this manner, a voltage measurement
will be taken from this point with respect to ground. The placement of this
voltage probe will plot the source voltage.
Once the voltage probe has been placed, the trace will appear in the
AMS Simulator window. Bring the AMS Simulator window to the front and
observe the presence of the new source voltage trace, which will be named
"V(l)". In Figure 6.5, a IV pk waveform is now visible.
L1
C1
1 • ~r-,,-3_---,
~~~ ~L==o~v
=
FREQ 10kHz
A C = 1V
P
<:
~
V1
1mH .2533ti'
R1
30
Figure 6.4 - Schematic diagram with voltage marker placed at node 1.
cadence - II x
~ • .eli ~ a ll • .1"'''''.....11'' ';••....;;;/11 - :"0
f C 0. A ~ .. .... YI ... Iii .!!. ~ rn~ ~ 1iI.J1. ~. ... ~. --.. .) _
...
... _.
, 'M 1DGus 12 0tls 1ltOus l U LlS 1tDIIs 2Gc.Js 21 D.I5" 2' '''s: :llflUS
Figure 6.5 - PSpice PROBE window displaying transient plot of trace V(1).
The PSpice Probe Tool 6-3

After moving back to the Design Entry window, hover the cursor over the
next probe . This probe tool can be referred to as the VOLTAGE DIF FERENT IAL
MARKER( S). Select this probe, which allows you to place two probe s into the
schematic diagram. The output trace that will be plotted as a result of this
probe placement will be a measure of the voltage present between the two
markers. Note that there is both a positive and negative marker. A voltage trace
will be plotted in the AMS Simulator window based on a voltage measurement
taken from the node placement of the positive marker with respect to the node
placement of negati ve marker. One could compare the placement of these
voltage probe s to the placement of voltmeter probe s. This set of differential
markers has been placed around the inductor, L1, as shown in Figure 6.6.
L1
C1
-+----1 1---,,-
3 -----,
" - v: 2533lF
VOF F = OV R1
VAM PL = 5V 30
F REQ = 10kHz
AC = 1V
-=- 0
Figure 6.6 - Voltage differential markerplaced across

component L1.
[.1'10
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.
~ncr·li
,
!) ~
lQ q _~Eil.
y-
--
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..l..~...~ .. ..':'..~ .. ...~ •.:••.i••• ..:..':'..:.....:...l.. ~ ... ..:...:. .. .. ...:. ..:..... ..l..i...;.. ...:. ..:..~... ••1•• ':". · : •• ...:...:.. ... .. : ...,:. ..: ..
..· . .~
::i::t::t::::t::i::~::: ::i::t::t:: ::t::r::~::: :: i::t::~ :: ::t::l::~:: : ::l::t: :~ :: ::~::i): :: .+.+,+. ::t:: i::~::: : :i::t::~:: :::~::r: :~::: ::i::t::~::
· · v · . :· . ~ ~ ~ ~
) ::t::t:: ::t:l::j:::
· :C. IU
... .. .... ...,
..f'.-:-.. ..
11(1)
~
,
1I{ 1. 2)
..:..-:-": .. "-: " !" i' " ..;..-: .. .. · , t · ' j " ~" · " j" f " f " , · t · ': · ,~· " " !".;-" :" ·'t " !" i"· ::F:r :f:: " f " :" i'" "!"-:- '.=.. "-:": "i'" " i'''r'':''
lIu~
~
lO OU s u ....s 1.11" s
TIM
1611
US , I lv s; 210Us 220.s: 211"'s 26tu 2U"s ~n"s
...... _ j
Figure 6.7 - Trace V(1,2) has beenaddedto the transient plot.
6·4 Chapter 6
With both the voltage and differential probes in place, two traces are
now visible in the AMS Simulator window. The original I V pk waveform
remains, and the new trace that has been added to the plot is that of the
voltage across the inductor. Refer to the bottom left corner of the screen
and note the name of the trace as V(1,2) (see Figure 6.7) .
One last set of differential markers has been placed into the schematic
design to add one last trace to the plot. This set of markers will lie on nodes
2 and 3, respectively, and provide a trace that plots the voltage acro ss the
capacitor (see Figure 6.8) .
The two previous traces remain and this third and final trace has been
VOFF = ov R1
VAMPL = 5\1 30
FRE Q = 10kHz
AC = 1V
Figure 6.8 - Differential marker placed across component C1.
II' SOQ4I'ro·fWd~·~" ....t1Rc · (lWdb:!""'f'lc )1 ~

il fO< 1M _ _ !J><. tI" r... l ! ( - ~" l!l tide nce - ~ x
- - -'0
- 12 11
Is 211I5
U( 1) . u (1 .Z )
lIIus
1.1( 2 . 3:)
Uus ."',
1""'_ _ ___. _ __. _
C:\OtOOot.CAO,w;JJ![\lOOlS\C »ttMtr\£l\ OuIllK ' .PStOt... ~1JC1v.nt &.Ime!tVirst~(Kti\S
Figure 6.9 - Trace V(2,3) has been added to the transient plot.
The PSpice ProbeTool 6·5

added to the plot. This trace plots the voltage across the capacitor. Refer to
the bottom left corner of the screen and note the name of the trace as V(2 ,3)
(see Figure 6.9).
Adding Labels
The AMS Simulator is user-friendly in the sense that it lets you
manipulate the plot in certain ways that allow the information and data to
be presented more neatly. The plot shown in Figure 6.9 could be considered
cluttered and illegible . At first glance, it may be difficult to decipher which
plot is which . We will begin by providing labels to each of the traces on the
plot. In the, PLOT drop-down menu, find the TEXT option under LABEL. The
user will be presented with the window shown in Figure 6.10.
Enter an alphanumeric combination into the text box to generate a label
that can be placed onto the plot. After
Add/Modify Label Text clicking OK or pressing enter, the
designated label will be attached to the
Enter Text mouse cursor and can be placed anywhere
the user desires . In Figure 6.11, three
( Change Font I(
OK ....."J ,. _ Cancel
--...J labels have been added to the plot. Each
trace has been labeled with a description
Figure 6.10 - ADDIMODIFY LABEL TEXT window. in addition to the trace name.
GiIIl1ii":lliiiia
cadence - ~ x
-iVI ! -_.~---
I I
-12UL~---._.L.--~,-.
!
- - -I- l - - -+--- - ! -- -J
I
I -
II:> 2 r.us 1I1l\!S 61ltlS 12UO!>
. U( 1 ) olJ (1 ,2 ) . U( 2 . :l )
Tin\'
Figure 6.11 - All three traces have been labeled .
6-6 Chapter 6
The three labels read as follows:
"Source Voltage, Trace V(l )"
"Inductor Voltage, Trace V(l ,2)"
"Capacitor Voltage, Trace V(2,3)"
Notic e that arrows have been inserted to designate which trace
corresponds to which label. To insert an arrow, open the PLOT drop-down
menu and find ARROW under LABEL (see Figure 6.12). Using the mouse
-'·' \'- '-;+ '; -';-' - ~'"'-- ;- _·;I-;-\-H · ·:· ,r, ' +-' · ·i · --;··Ir \ ; - · ;- --f- - i - · " · · i\ j· · - ' · · i f - ;- \I · · '· --I-;< - · ·I
- 12 U o~. 2 11u'S ~~lJ5 6 Uus 8 t us 11lUU!> 120u s 1-'10U5: 16t1u!> 180Us :ZOOU5 220\1 s 2Jlll u 'i 2 U lIS llllltl s aDDu..
U(1) U(1 , 2) UO' . 3)
•
Figure 6.12 - Insert Arrow option.
U '2'
0
1
l~ / 1'\ V\ I
··,•
t Ind C'lOfVoltllg• • UI:;. V(I.2)
il \ ., \ I
IU
Y \ --J
S4uru Vol: \I' , Trice ¥( )
k
,-
\ .--...... ~ \
J~ >( 1\ \ )1 / V 1\ \/ V V 1\ 'v
k
-""
\ \ A / 11\ \ j\ / 1\ \ !' /
"'-- ~ / \ V \ I \ II \
/ "--
-IU
<:> -,!/ I
C" p.tCr!Of VO. J~.T'lc ,V1 .3)
\..J ~
- 12U
"
• U( 1)
21."
• U(1 .2 ) • U(2,:1)
...., ...., ...., 1""'5 12Dus 1' 11I5 ueus 11lu s 21lus 2Z1us. ZUus 2""'5 ZU IIS lIlus
Ti_
Figure 6.13 - Plot copied to clipboard in grayscale.

cursor, select the de sired start and end points on the plot to draw the arrow
in place.
Now the axes are labeled and the plot has been output in grayscale.
This finished product can be seen in Figure 6.13.
Adding a Second Plot to the AMS Simulator Window

Thi s first example uses a transient response simulation to plot the output
voltage across the capacitor and inductor with a plot of the source voltage
visible simultaneously. The frequency of the source voltage is 10 kHz. This
also happens to be the resonant frequency of the RLC circuit, so when plotting
the output, you might find it benefic ial to isolate the induc tor and capacitor
volt ages fro m the source voltage using separate plots ; this lets you clearly
obs erve the phase relationship between the inductor and capacitor when the
RLC circ uit is at reso nance . As prev iously stated, the AMS Simulator can allow
the user to display the output data and plots in a variety of different ways.
In the next example, the same circuit and traces will be employed in
generating output data in the AMS Simulator, but this time the traces will be
contained within two plots in the same window.
To accomplish this, it is not necessary to run the simulation again;
rather you w ill be manipulating the data present after the initial run of
the Transient Analysis. T he first step is to delete the traces from the AMS
IF.;! rm~·rntu-.,N ·PSpic fNOLAf· ;r'"'[....,..,.l.fct~)1

.
1. E'~ ~:H ~.- ~1I".x:n l rac., fIot T~11 JYondow ljrfp ~ cadence _ ~ x
;u · e if-~ ! . j F. :t E><=p/eFr:t E""""* 0

:0. ~ ~~
.;., ,...
,. ~s : he;;
---
;
.... . .. . .. ..
~
: SED>
es ',,", IIll us 6 0U5 BDus 100uo; 1 20 U5 1 i10u s 160tJ s 1 80U 5 2 0 CUs 22 0Us 2IJOUs: 2Uu s 2 11lus 3 Dllu s
Tine
.fnI~
f«Helc.>.Ilf~F1 Tomr- JOO,OE..(l6 100%
Figure 6.14- A second plot has beenaddedto the AMS Simulator window.
6-8 Chapter 6
Simulator window. This can be done in one of two ways. One method is to
click the individual trace name s at the bottom left of the screen and press the
DELETE key; the other method is to select the option DELETE ALL TRACES
under the TRACE drop-down menu. After doing so, the user will see a blank
plot with an undefined Y axis and an X axis ranging from 0 s to 300 us.
By selecting the option ADD PLOT TO WINDOW under the PLOT drop-down
menu , a second plot will appear in the workspace, as shown in Figure 6.14,
with each plot taking up approximately half the active window.
The axis labels and grid lines can be adjusted accordingly for each
independent plot. This means that the plot in the top half of Figure 6.14 can
have a unique gridline arrangement and Y axis title while the bottom plot can
have its own configuration. The method in which these parameters can be
altered remains the same. Again, to change an axis title or modify the gridlines,
simply double-click on either Y axis to open the AXIS SETIINGS menu.
Now with two plots to work with, the traces can be reinserted. First
we will input the capacitor and inductor trace s into the bottom plot. In Fig-
ure 6.14, take note of the SEL» indicator, next to the Y axis of the top plot.
Any trace s added in the AMS Simulator will be to the plot associated with
the SEL» indicator. In the case of Figure 6.14, traces would be added to
the top plot. Select the bottom plot by click ing the blank region to the left
of the lower Y axis, then add traces V(1,2) and V(2,3), as in Figure 6.15 . In
this figure , gridlines and label s have been put in place. After moving the
jtJ', SCJ4MAfJ:1-fwW~· "",," NOl",, · _ ~ I

~~
i. f- ( M :t:_ ~tllOft 1_" fIot TIClb Ytondow I:itlp~ cidenc e - "
x
~~ . O ~
1:< Q ~ ~
. ---"
.!!iii -;"~ VI
... ..
l'
Iff ~ ! ~ ;;;
-
. •. •1
. ISriEMATIC1 .FiI_ E~'-
.. -_ .. .. . ... . ._- - - -
I-
I:
I~
SED)
u
,OU
e
I
.,t
•
~ v....
r", y ~. V r~ /
~
~ -: ~
r~ /
·, '" ---' ----.. . . .- V" -: r-.;V
::..~ ~ <. I--------'
k
,
<, -----..-V i~
"-"'a
..
k
.,
-
· , ou
2D,,, ,,, , ..s ...s 118u s 12 lu s l /1UUs 16 tl1J'i lIDus 210Us 2211I5 z"UUs 26Dus 21llus 31lkl5
a U( 1 . 2 ) . U( 2. 3 )
...
F« . . .. JJtet fl
U"'"
X: l 54~-<lOS Yd1.1 TwnuJJO.oE-06i "..

Figure 6.15- Traces V(1,2) and V(2,3) havebeenaddedto the bottom plot.

SEL» indicator to the top plot, the source voltage trace, V(1), can be plotted.
In Figure 6.16, all traces have been plotted and labeled. Each Y axis
is labeled and both plots have the appropriate gridlines.
Finally, the grayscale plot has been generated in Figure 6.17. With the
capac itor and inductor voltages isolated in the bottom plot , it is very easy
to see the phase relationship between these two waveforms. As previously
~ SCHlMAt1CI -'_~'~.AIO.~.,a~~~
;. £_ t lW Y..... ~ 1(1(<< floc J~ »:"~ t::tttP cadence - if x
lu ' I ~ ~: ·S(H£iiJ,l 1C1.f. ll f .... 1O
~ I"''''' _til. VI ". C':l ! ~~ L~ l

--- J
·
u
,.OU
<, -. ~
:·
1
I 1\'-' V
"V('r
I ~
I~
t C«• • Tr.M:1f
ou
~ 1\
•• \ \ '\
••
SED)
- S:. IU
,OU • V( 1 )
1"-, V I"'-. V r. V
·
U
1 ..... lOI' VoII• • ac."V(ur

··,• I------- r--,
~ -: 1..---.... 1/
t
•
ou -- <,
- r---....
I'---V'.. . .....~.- . - //
.>: ~ ....
-.
,/
I'-------
V '
-,
/
-, .............. /
.. ~
r------- '"
V '" " ' "",-
p (;,apldOfV lagt:, f ran 12.3r
•
-' Ill
.. "..
• U{1 ,1) • lJ( 2 .3 )
0"', ... , ...., 1'lus i l lus 10\" 5
Ti M
""" 1t tus 2flu s 22tv 5 2...lu s 2'''5 2I lu s tllu s
'. ""e-
Figure 6.16 - Top and bottom plots have been compl eted adding all trace s and axis labels.
.:I fN
-. \ S.
lu Vo11 olga , f;, t~
/ -.
\ !/ ~
\
\ \
\
V 1/
p
/
k
p
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, au
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-. -. -.
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u
-.[7
1
·• y -. V- ~ / ~
I~
t IndulOfVOll1lge, r" e Vll .2)
~
e <, ~ /
au
•
k
-
<,
r-------- l/ " t'>-- L/ ""-" ~
i/' <; r~ -- -'~/
/
r--..---- ~
•• ap:acltor Vo: ge. T'<I' 9 V .3)
-, au
" II U{ 1 . 2 }
21'. "11(' 2 . 3 ) 0"', ... , I"" ileu s i 2 0u s 1o\lu5 16 8us 18 01.15 2Ulu s 2Uus ZIJtu:;; 260115 21tu s 3tOUs
TIM
6-10 Chapter 6
stated , the RLC circuit is running at its approximate resonant frequency of
10kHz. At resonance, the reactances for both the capacitor and inductor
are identical, so the voltage acro ss each component will be of the same
magnitude. It is important to remember that although the magnitudes of
the V(1 ,2) (inductor) trace and the V(2 ,3) (capacitor) trace are similar, these
waveforms are 180 0 out of phase with each other.
This will lead to a cancellation between the capacitor and inductor
waveform s, leaving a purel y resistive circuit. This phase shift can easily be
seen in the bottom plot of Figure 6.17 . With this modified layout , one could
argue that it is much easier to interpret output data when looking at Figure
6.17 rather than Figure 6.13, where all three traces were on top of each other.
Adding Traces Manually Using Analog Operators

and Functions
The marker tools that have been used thus far and that have been placed
in the Design Entry software have allowed the user to measure units of
voltage. While these probe tools may seem rather simple, used in conjunction
with ANA LOG OPE RATORS AN D FUNC TIONS in the ADD TRACE window, the
user can plot almo st any characteristic or function imaginable. Using this
second circuit, a new RLC resonant one, we will create another multi-plot
window showcasing both the impedance and phase angle of a tank circuit
with respect to change in frequ ency. The circuit to be con structed in the
Design Entry software is shown in Figure 6.18. Thi s circuit is identic al to
the resonant tank circuit from the previous chapter.
Figure 6. 18 has been drawn in a slightly different manner. Note the
R1
1 2
1k
>
J
L1
> 1mH
V1
.>
AC = 1V ""'- C1
.2533uF
3
RL
• 3
-l-
-=-0
Figure 6.18 - RLe resonant tank circuit.

schematic symbol of our ac source voltage, V1. The VSIN component will have
associated parameters of amplitude, frequency and offset voltage as well.
For this particular example, we will be performing an AC Sweep. The only
relevant parameter for this simulation type and example is the one shown,
AC=lV. A value of 0 V has been entered for a dc offset, and miscellaneous
values are input for the remaining parameters of amplitude and frequency
since they will not impact the results of the AC Sweep . To neatly present
this schematic, the only value that has been labeled is the aforement ioned
AC=lV. After the schematic is drawn, the simulation parameters are entered
for the AC Sweep (see Figure 6.19).
After entering the simulation parameters, run the simulation. As in
the previous example, the AMS Simu lator will open with a blank plot.
Begin by adding a second plot to the window . Select the top plot and
open the ADD TRACE menu. In the text box at the bottom of the window,
manually add the trace name, "V(2)/I(Vl)". Taking the voltage across the
LC parallel branches, V(2) , and dividing by the total current in the circuit,
I(V1), will calculate the impedance of the tank circuit. As the frequency
sweep is occurring, the inductive reactance and capacitive reactance will
change . These constant change s in inductive reactance and capacitance will
Simulation Settings - Second Example
GenenlIl
~Iype;
l;c ~~ _
hIaly$is I.~ Res 1.()ptionsJ ~lI Co1edion
·1
ACSweep Type
~
I Probe Wndow l
~lerl Frequency. 5kH z

-
~: @ L29llIithmic ~nd Fr~ncy. 15kHz
~~..e- I D~ ·1 PoinlslQ~e: 100J
Perlmetric Sweep
Noise~
lj T~1.te (Sweep)
IrJ SlIve Bias Pan EJ Enabled OJJlpul VohlllW [ I
E]Load Bias Pan I/y SOU/ce
I I
!nlelvlll
I I
OutputFile0 pljons
l!JIfll<lde delMed !liM point ilIOIrMlion fot nonIinellr
controled$OUIces <lnd seri:onduclOls I.OP)
II
I OK
Figure 6.19 - SI MULATION SETTINGS window, AC Sweep.

Cancel II twt
" He/p I
6-12 Chapter 6
im-pact the impedance of the circuit and will be reflected in the output
plot. The resonant frequency of this non-ideal tank circuit is approximately
10kHz. At resonance, the inductive and capacitive branches will be seen as
having an impedance of (Z) = 00 , with an equivalent parallel resistance of
1.318 kG . This is shown in the top plot of Figure 6.20.
Next, the bottom plot will be added to the AMS Simulator window.
l "-saou na ·,""",,, _ · !'P.<- ~" "' · """": """"

i.folof" _ _ _ I'~ !loO t ..... _ tlo'o .r&.
...
_ 8 X
cadn ce
te - ~ ~ - 5 I - I'" . i So4E""'JICJS--.d E.. oft -
I ~ Q, ~,,~ ..... yt ... ~I.lf" ~ s = h ii .iF' ~IP""

..
'.
= ~""
---- ~
... .. .
.
I~
r
"
k
1• •
I1
\
' .SIC
......* oITri l ~.~$ _F~y
/ \
-~ ~
l1j.
U l»
• • U( Z)/ 1 ( ',11)
5•• • 2 1."::
I
UkNzl
r--=--r., . . - - f r-~q ut n c: y
Figure 6.20 - Plot of tank impedance with respect to frequency.
ModifyT,.,.
SiDoJaIion O ~ '1_. IAnoIog OPO!..... aM FtolCliont · 1
Figure 6.21 - Addi ng a
trace using the phase
operator.
IICl )
UI
IICl:l ) I
1(1.1 ) @
1(1.1 :1) ASSI)
l(Al) ARCTANI)
~~IJl
1(A1:1)
1(Al) [J
I{RL:l) AVGX(. )
IiVll COSO
IN!:>] DO
VlO) OBI)
VII ) EN\iMAX( . J
V(2) ElNMltl(.)
V(3) EXPO
V(Cl :1J GO
V(C1:2) IMGI J
V(L1:1) LOGO
V(l1:2) LOGI c.: )
VlRl:11 1010
VlRl:2) WX(J
VlRL:1) MINO
VlRL:2) PI)
V(Vb ) f'WR(.)
F.. LisI
Iraoo E"Illeosion: ioWO Mr >iii. . . .

This will be a plot of the phase angle of the tank circuit with respect to
frequency . Select the bottom plot and open the ADD TRA CE window. The
right column of this window is titled ANA LOG OPE RATORS AND FUNCTIONS
(see Figure 6.21).
Scroll down and find the operator PO. This operator will plot the phase
angle of the trace entered within the parentheses. Click on this term or
manuall y enter the characters "PO" into the trace text box at the bottom .
Between the parenthe ses, enter the trace name "V(2)". From this first term,
"P(V(2))", subtract "P(I(R l ))". The full trace name becomes "P(V(2))-
P(I(RI )" and is nothing more than the phase of the circuit current subtracted
from the phase of the tank circuit voltage. The plot of this trace will illustrate
the change in phase shift as the frequency sweep occurs. This final plot is
The final plot has been generated in grayscale in Figure 6.23. With the
two plots adjacent to each other, it seems easier to interpret the relationship
between these two plots. In the top plot, the labeled peak magnitude of
the tank impedance occur s at the resonant frequenc y of the RLC circuit
(10 kHz). At resonance, there will be no phase shift between the circuit
current and the voltage of the tank circuit, so we can note that at this same
frequency in the lower plot the phase angle measures 0°. At this point we
know that the circuit is purely resistive. At any frequency below resonance,
the RLC circuit is capacitive; therefore, it is indicative in the lower plot
i .fk {6C r- ~ I 'K' fkt T$Ok WiMow ~ fliil (aden" _ " x
i ll ' C ~ ~.l .I SQiEw, nCl-lf - ... .0

IQ Q ~ ~ ~ • "l VI " . lOf31 \':: 8 't: ~ ii.1r- _- _._.
~-+ - .- _.- -- . . --
loJ Z 1 . 51
'~ ·
T
"III: 1 . M I \ 1I-'U'19Q
~
' .51C
. . . . . . clTMk ~ . yt;.F~
/ \ <.;
= .---/
, ,,.• • U(2) /1(1I1)
•
·
s
e
SOd
~
\ 11-... ..."
·
n
9
,.
F'tNtH oI T" ~l'I .~
/
·
1
-s" 1\
-,,.
U L»
"'--
-:::-I'
5 .IUz
• r {U( 2 » - p ( l( a l »
... 'n.u~.
l lkM ~
-
=:J
Figure 6.22 - Trace of phase angle added to bott om plot.
6-14 Chapter 6
Z t SK
·
T
~ 1 ()(
/ 1\(9999K.'.3175K)
O.5K
Mawnilu a of Tank Impld ..nCl VI F ~qu . nc )'
/ \
~ ~
r
... 0
o Y(2';'lV'lJ
·· ,..
h
s
~
\
C3999K••2 5541)
· ..
n
9
Pha" of T~nk Imped~llce YS f ~ que ncJ
/
·-,..
1
\
-...
SEl »
S • • Hz
a P(U( 2 » -P(1( 11»
1 .Mz
"'--- 15 KHz
Fr .qurn cy
that the phase angle begins to climb in the positive direction. Likewise, at
frequencies above resonance, the trace in the lower plot begins to climb
increasingly in the negative direction when the circuit is inductive.
Transient Analysis Results in the AMS Simulator Window

The next example will be that of a simple series RC circuit with a de
voltage applied. After constructing a schematic, a Transient Analysis will
be completed to plot voltage across the individual components of a circuit
as the capacitor charges . Again, we will employ two separate plots in the
same window, one of which will be used for the voltages previously alluded
to and the other for power and current. To begin , the
R schematic design was constructed in the Design Entry
1 2
l
---m~--l software as shown in Figure 6.24. After drawing the
schematic design, double-cl ick on the capacitor to open
10V ._ V1 ,...
C
the parameters for the component. Find the parameter
r-'
1uF Ie (Initial Charge) and input a value of "0" . This assures
that the simulation will begin with an uncharged
capacito r.
Next a simulation profile is created entering the
simulation settings shown in Figure 6.25. The profile
is set to run a Transient Analysis with a runtime of 50
ms beginning at time, t = Os.
Figure 6.24 - RC circuit schematic. After running the simulation, the AMS Simulator

will open. Just as was done in the previous examples, add a second plot to
the window. Select the top plot and, using either the VOLTAGE DIFFERENTIAL
MARKER probe tools in the Design Entry window or by entering the traces
manually, plot the resistor voltage and the capacitor voltage . The bottom
plot will contain two traces. One will be the current in the series path and
the other will be a measure of power across the capacitor. To reiterate, either
method can be used to plot each trace. The probe tools can be placed in the
Design Entry software, or the trace names can be input in the ADD T RACE
window. Now a total of four traces can be seen within the two plots (see
Figure 6.26).
In Figure 6.26, the top plot shows the capacitor voltage, trace V(2), and
the resistor voltage, trace V(1 ,2). In the bottom plot, the circuit current, trace
I(C) is accompanied by the trace of the power dissipated in the capacitor,
W(C). Notice, in the bottom plot, there is no unit labeled on the Y axis, merely
a prefix for milli . The axis has been simply titled "Magnitude" because
there are two traces based on different fundamental units . Therefore, it is
understood that when interpreting the current trace, measurements will be
taken in the unit of milliamperes, and when interpreting the power trace, the
unit will be expressed in terms of milliwatts. Finally, the plot is generated
in grayscale in Figure 6.27.
Simulation ~in9s - ThirdExa mple .~

GenenlIl ~ I~ Fies I ~J OataCoIedion I Probe Wndow I
~type :
Bun to time: 5CIrn$ seconds (TSTOPj
ITme Domain (Tl1lIlSIerj) ... 1
Qptions:
.stallSllVing dala after. 0 seconds
;J - . Iransient opliom
ICl Marte CarloIWOfSt Case Maximum step size: SOu seconds
IEIplIrMlelric Sweep
E1 T~ (Sweep) ILJ ~kip the iriiaIlIansienl bias poi1lcaIcWlion (SKJPB PJ
IC.I Save Bas Pon
[Jl.oad IliasPon
EJ Save Check Pons
IE]Bun inr=me mode I O~ Eie o~·· 1
lEI Restart SinUation
[ OK II Cancel II twY II ~ I
Figure 6.25- SIMUL ATION SETTINGS window,Transient Analysis.
6-16 Chapter 6
The bottom plot is rather self-explanatory. It contains two trace s, one
of circuit current and one of power delivered to the capacitor with respect to
time. The top plot allows the user to see the relation ship betwe en capacitor
voltage and resistor voltage. As the capacitor continues to charge and store
potential, the voltage drop across the resistor will continue to decrease.
ciden ce - " x
• t::l Go ~ "Sol ~ .. ,. .1""'" \1(""",,"';,, ·.0 ... I
q ~ 6l. /1;' ."~-
VI'" EO !
-
~ EO = h ii , I"" .::l~ .!"'
-- --_. _ ~ _ ..- --
-= liil ~..Ii;i'
- --,--
... J
Voltage "". TIme
• U( 1 .2) • V(2 )
" •·..,.-----__r----r---___,----.----r------r---~--__r---._--___, I I
···••
~ 2·1IIl,+---,L- t- --+--"".......::-1--- -+-- - - t - - - - + - - -+-- - - t ---+------i 11
·'·" -----rL-
IT
. ........·1
•
Is
• wet) • He )
. .. .... 2_
"
u ..
.. .... .- .... .-
Figure 6.26 - AMSSimulatorwindow with graphs of voltage,current and power.
."l'~
: ~J--
: ~ ......... capaeitorvoI:,.
Voftage vs , irne
~~
~
1/
'Sol V
J-----~ ,.
eN
• V(1;) o V(l)
··•
" 2 . ....
-.....
I
t 2 ....
.: --../"'"
<,
D-INtu d To Capac Of
/
--.-
"d
· 1."
f ap.c itOl'Cu ani ~~
1;--..~ -----
.- .. .-
t--
sn,»
• Is .
• w<e) • I( C)
1_ .... 2_ 2'"
11..
.... ..
Figure 6.27- Plot copied to clipboard in grayscale.

Transient Analysis and Fast Fourier Transform
Our fourth example is another Transient Analysis that plots the cycles
of a square wave. The circuit for this is a single voltage source connected
to a load resistor (see Figure 6.28). The type of voltage source used is the
component labeled VPULSE . It is crucial to modify the parameters of the
pulse source in order for the output voltage to resemble that of a square
waveform. To do so, a quick rise time and fall time of 1 ns have been
designated. The pulse width is 0.5 ms, which is half of the period of the
waveform, and the amplitude of this waveform has been defined as 1 V, the
difference on V1 and V2.
Figure 6.28-
Schematic of pulse
voltage source across
single-load resistor.
V 1 = QV V1
V2 1V= R1
10 =05 1k
TR = 1ns
IF = 1ns
PW = .5m s
PER =1ms
-=-0
SimulationSettings- Fourth Example

~ Figure 6.29-
SIMULATION SETTINGS
window,Transient
~ ~ I~ ResJ ~ I OaIll Coledion . I Probe WndowJ Analysis.
~type :
Buntoline: 25m seconds (TSTOPj
ITIne Oomai'l (Tl'llrlSieri) ...1
.s.lal ~~alllter. 0 seconds
~:
- -. - IrMSienl options
Ir:JMorte CMolWcnt Case M~ stepfize: ~ . J seconds
IE]PllRlIIletric Sweep
I~ T~lJ'e (Sweep) It:!,S,kip theinitiaI lIansienlbias point calculalion (SKlPBPJ
IClSave Bas Port
I ~ l.oad Bas Port El Buni'l resune mode !OulpUfie Oplions..·1
EJ Save 01eck Ports
IE] Restart SlrWaticn
l OK II C510el II JW:t II ~ I
6-18 Chapter 6
Figure 6.29 shows the SIMULATION SETTINGS window. The simulation
profile is set to perform a Transient Analysis with a runtime of 25 ms starting
at time, t = Os. The output plot will display 25 cycles.
Because of the simplicity of this output waveform, the next screenshot
is the generated grayscale plot (see Figure 6.30). The plot consists of the
plotted load voltage with respect to time.
The fact that this last example utilizes a square waveform allows us to
explore one of the other features of the AMS Simulator, the Fourier Analysis
Function. A Fourier Analysis determines the harmonic content of a complex
waveform. In the SIMULATOR window, the plot of a 1 kHz square waveform
is visible. A square wave is composed of a sine wave accompanied with
multiple odd harmonics of that fundamental frequency. By carrying out
a Fourier Analysis of the plotted square wave, one would expect to see a
I kHz fundamental followed by the presence of a 3 kHz harmonic waveform,
a 5 kHz harmonic waveform, 7 kHz harmonic waveform, etc . To carry out
a Fourier Analysis, click the button highlighted in Figure 6.31 in the active
window with the plotted square wave .
1.51,1
··•
l
·
v
1
·•• 1."
t
I.SU
. l- I- '- '- '- '--
- 1. 5 1,1
'"
• 1,1(1)
... ... ... e.. " .. 12M
liM
10 "" 16 ""
" .. .- .. "" ,."" . ""
Figure 6.30 - Plot copied to clipboard in grayscale .
Figure 6.31 - FOURIER

ANALYSIS button.

cadence - (J x
r
"""'."'" _. ._ .. -
L"'"
··• (1.000CK.636.775m)
·
u
1 61 ..,
··•
t
""""
t;:::::;;;J- liiI
,!",... .., .01........ - - - - - --- - - --- - -_. 100%- -&= _
rOt ......prmn
Figure 6.32 - Fourier Analysis, harmonic content of VPULSE square wave.
l lliIMII
··•
L
IllllXJl<,636n5m )
·
u
1
··•
t
U """
' .1oU
(3lllXJ1< ~1 2 mm)
.....
..• z
\I U( 1 )
11Hz ZIeHz 31Hz OK"
~
U Hz 61 1z
~
71Hz IIlfz ' K.z
A
1_ . z
FrlfquMCJJ
6-20 Chapter 6
After clicking the FOURIER ANALYSIS button, you will be presented
with the plot shown in Figure 6.32. The fundamental frequency and all of
the associated harmonic frequencies, as well as their associated amplitudes,
are plotted within the user-defined range of the X axis (Frequency Range).
The output is displayed just as was predicted. Finally, the output plot
has been generated in a more legible grayscale plot in Figure 6.33.
In Summation
With the information from this chapter and the overview of the four
basic simulation types from Chapter 4, you will be able to create basic
designs using the Cadence software and present the data in the Allegro
AMS Simulator window. In the next chapter, you will be introduced to
semiconductor models that can be incorporated into more complex designs
than those discussed thus far.

Chapter 7
Semiconductors
In previous chapters of this book, you were introduced to the basic

schematic design process, passive components, and the fundamental
simulation types that can be utilized within the OreAD/ PSpic e environment.
In this section we will expand upon all of these concepts while introducing
you to another family of components featured in the PSpice library -
semiconductors. In addition to the resistors, capacitors and inductors that
you have already used to draw and run simulations, the PSpice library
features a wide variety of diodes and transi stors.
The Diode Model

Let us begin by drawing the circuit shown in Figure 7.1. The circuit
consists of a single resistor, a de voltage source and a lN4002 diode .
The I N4002 diode is a relatively common rectifier diode. The default
PSpice component libraries contain many different diodes ranging from a
common variet y to more obscure component models. An excellent feature
of the PSpice software is that virtually every
R real component from every manufacturer ha s a
1 2 PSpice model. They may not initially appear in
1k the default PSpice component libraries, but they
are available for download from most component
v manufacturers' websites or the Cadence/PSpice
10V website. Each different diode model has its own
D characteristics and specifications that are indicated
D1N4002 on the real components spec sheet.
To explore the behavior of these nonlinear
components, the PSpice software can be used
--=-0 to plot their characteristic curves. To do so, one
must perform a DC Sweep Analysis of the circuit.
Figure 7.1 - Diode circuit using the model D1N4002. Varying the source voltage and plotting the current
Semiconductors 7-1
in the circuit will provide a characteristic curve for this diode.
First, we need to decla re the simulation parameters. Figure 7.2 shows
the SIMULATION SETIINGS window and defines the range of the DC Sweep
starting at a value of - 103 V and ending at +2 V with data points being
plotted at 0.25 V interval s. After running the DC Sweep, you will generate
a plot similar to the one shown in Figure 7.3.
Using this declared range for the DC Sweep provides a visual repre-
sentatio n of the three modes of operation of this particu lar diode . Starting at
the right of the plot, it is apparent that
Simulation Settings - Chot
- --- ..... , the diode is forward biased with a for-
ward voltage of approxim ately 0.4 V.
Continuing along the X axis, the trace
Sweep valiable
Ii; Volt ~ eocece v
of the characteri stic curve extends past
locs-> Name:
o C...rent source
L ~I
o V in the negative direction . This in-
e Globalparameter dicates that the diode is operating in
~ Model parameter
E1SecoodafySweep
o MorieCario,wool Case tV Temperature reverse bias. As we cont inue farther
E1plII1IITIdric Sweep
E1 T~ (Sweep) Sweep type
in the negative direction of the X axis,
IElSave Bas Poirt
~) Linear
Start value: ·103V the de voltage source value eventually
E1 lDac1 aasPoirt
e LogarU'IInic r;::;::::.:-:l
~
Endvalue: sweeps beyond the peak inverse volt-
Increment .2'3'1
age (PIV), and an increa se of current
e:>Valuelid '--- ----'
flow in the negative direction can be
noted as the diode is now operating in
a state of breakdown. This seems to
OK Ii ~ Ii "cl"Jy II ~
occ ur when the value of the voltage
Figure 7.2 - Simulation settings for single DC Sweep. source V exceeds -100 V.
1 .S ... .---- -- - -- - - - - - - - - - - - - - - - - - - - - - - - - - -- ----,
1._
)<:11 700.-92957U)
.
-1."
-z...
-I . .....
- a.s.. .L-..__--~-- ~ - --..__--~-- ~-- - ~-- ~ - -~ -- - ~ - - ~

- 111U - l Oll '100 - ' 00 -600 -'00 -zoo - 1 00 00
_ I ( D)
"_"
Figure 7.3 - Characteristic cu rve for D1N4002 diode.
7-2 Chapter 7
Another simulation technique allows the user to provide a more
accurate characteristic curve of a particular diode model by changing the
axis variable of the X axis to the diode voltage. This will generate an output
plot that more closely represents the characteristic curve of a diode as it may
be seen on a spec sheet.
To accomplish this, open the AXI S SETTINGS menu from the Cadence
Allegro AMS Simulator or PSpice AID window that has the IN4002
characteristic curve and select the X AX IS tab (see Figure 7.4 ). In thi s
window, click the AXIS VARIABLE button to open the X AXIS VARIABLE menu.
The X axis variab le has been chosen as V(D:1), the voltage at the ano de of
the diode (see Figure 7.5).
Apply these changes and it will produce a plot representative of diode
voltage versus diode current, as opposed to source voltage versus diode
current. This is shown in Figure 7.6.
To further illustrate the difference between the two characteristic curves ,
the range of the DC Sweep has been extended in the positive direction to 10 V,
and the X axis range of the diode voltage versus diode curren t plot has been
defined from a minimum of - 0.5 V to a maximum of I V. This will present
the forward bias characteristics of the IN4002 diode (see Figure 7.7).
~- -~
-- ----
Data Range Use Data

(0, Auto Range ~1 Fuft
o User Defined 10Restricled (analog)
Scale Pmce ssng Options
o Foufler
EIPerformance Analysis
Axis TKle
IAm Variable... I IUse1 Defuled TlUe -r
OK II II
Cancel ] [Save As Default ReselDefd , l[ Help
Figure 7.4 - AXI S SETTINGS menu.
Semiconductors 7-3
X Axis Van ble
~ - ----~- - - - - - - - - - - - - - -- -- - - - - - -
Simulation Oulpul Variables Functions or Macros -
IAnalogOpecalOlSand Functions y I
•
1(0:1)
I(RJ
()
n
1(R:1 ]
I[V) ~ Vollages
I[V:+) I
VIOl @
~ Currenls
V(0:1) A8S( )
, V(0:2) ARCTAN( )
~ Power
V(NOOO81) ATAN()
V(N00087) D Noi:e [V'/Hz) AVG( )
V{R:1) AVGX( ,)
V(R:2) ~ Alias Names COS( )
V[V:+) O( )
V[V:-) D Subcircu' Nodes OB( )
V1(0) ENVMAX( , )
V1(R) ENVMIN( ,)
V1[V) EXP( )
V2(0) G()
V2(R) IMG( )
V2[V) LOG( )
V V 25 variableslisled LOG1 0( )
WiD) M( ]
W(R) MAX()
Full List
Trace Expression:I V(0:1j
Figure 7.5- x AXIS VARIABLE window,
• z._
··
i
d
C J
u
r
•
··
r
· z.... . . . . . r . . . .
--.. -1 11U
_ I { D)
-s.. ...
- -, .. -d" -s ..
U{O : 1 )
...
- ...
- -2" .
-, .. ..
,
Figure7.6- Characteristiccurve of 1N4002 diode, full range.
7-4 Chapter 7
,'-
··
1
•
·,,
"
C
t
s..
· ..
-s..
+ + + + + + + + +
..'. +
+
+
- ' . 5U
.. I(El)
-I.'" -t .3 U - 1.2 U -' . 1U -t.'" D. 1U t .2 U ' . 3U I.IIU 1 .5 U '.6\1 O.7 U 1 . 1'" O.9U 1."
U(D :1)
Figure 7.7 - Characteristic curve of 1N4002 diode, forward bias.
Bipolar Junction Transistors

We can build upon the concept of the basic DC Sweep simulation type
when using the PSpice software to plot the characteristic curves for other
types of semiconductors, specifically the transi stor. Next we will look at
both BJTs: the NPN and the PNP. To plot the characteristic curves of these
three terminal semiconductors, we will be implementing two separate de
sources and performing two simultaneous DC Sweeps.
The first of the two BlTs to be studied will be the NPN. For this particular
simulation, we will be using the 2N3904 model from the PSpice library.
The construction of the circuit to be simulated is shown in Figure 7.8. A de
current source is connected to the base of the transistor. Sweeping this current
source varies the base current and will have a direct impact on the value of
r-t-r- -,2
01 C
VCC
B 15V :-L
-
Q2N3904
E
100uA
Figure 7.8 - NPN BJT test circuit schematic using the model Q2N3904.
Semiconductors 7-5
the collector current due to the gain constant (~) of the transistor. Sweeping
the voltage source will vary the voltage drop across the transistor. To plot the
characteris tic curves of this transistor, a current marker is placed on node C,
the collector of the transistor.
Again, we must define the parameters of our simulation profile . For
this type of simulation it is necessary to sweep two parameters of the circuit
instead of one , as we are accustomed to from prior examples. Select the DC
SWEEP analysis type, and inside the option section of the window ensure
that the boxes are checked for both PRI MARY SWEEP and SECON DARY
SWE EP. By default, PRIMARY SWEE P should already be checked. Using the
mouse cursor, click/highlight PRIMARY SWEEP to display the primary sweep
parameters. The primary sweep parameters will define the X axis of the
output plot. In the case of the transistor characteristic curve, it is desirable
to plot transistor current with respect to the change in VCE (voltage across
the transistor). Therefore, our de voltage source, VCC, will be the source for
the primary sweep. These parameters have been defined in Figure 7.9 . The
primary sweep parameters will remain the same for the rest of the examples
in this chapter. The de supply voltage connected across each transistor
circuit will sweep from 0 V to 15 V, plotting data in 0.015 V increments.
Simulation Settings - Characteristic Curve
Analysis type: 5weep variable -

[DCSweep .1 @ Voltage source Name: VCC
() Current source
Options: Model type:
C) Global pararneter
~ PrvnilfY Sweep e> Model parameter Model name:
~ Secondary Sweep
[[] Monte CarloIWorsl Case
o Ternpereture Parameter name:
'--- - - - ,
[[] Parametric Sweep
[] Temperalure (Sweep) .' Sweep type
[J Save Bias Poiri @ Linear
Start value:
[ ] Load Bias Point
o Logarithmic [ Decade ... j End value: 15V
Increment O.15V
e> Value list
OK I[ Cancel I[ IwIY II HeP
Figure7.9 - Simulation settings for primary DCSweep.
7-6 Chapter 7
Now select SECONDARY SWEEP to declare the simulation parameters
for our de current source. For this simulation, the de current source IBASE
will vary from 0 A to 100!-tAin incremental step s of20 !-tAoTherefore, there
will be separate traces on the generated output plot for each incremental step
of IBASE (see Figure 7.10).
After press ing OK and running the simulation, a plot will be displayed
similar to the one shown in F i gu r e 7.11 . The Y axis has been titled "Collector
Simulation Settings - Characteristic Curve
Analysis twe: Sweep variable
loc Sweep ·1 @ Voltage source Name: IBASE

() Currenl source
Options: Model type:
() Global parameler
~ m ary Sweep Model name:
() Model parameter
o Secondary Sweep
EJ Motte CarloIWOlSt Case e) Temperalure Perarneter name: '--_----.J
I
EJ Parametric Sweep
E! TelJ1)efOltre (Sweep) Sweep type
D Save Bias Port @ Linear
Slarl value:
EJ Load Bias Poirt
o Logarithmic IDecade ..j End value: 100u6.
Increment: 20u6.
<CJ Value lisl I

'--------------~
OK ) I Cancel II PwIY II Heil
Figu re 7.10 - Simulati on sett ings for secondary DC Sweep.
'w
·
c
'8 s.Curr.nt~ oo.A
1
·
1
c IS.CUff.rot 00uA
·
t
ne Curr. nl
r
C
'W ""'"
u U e Cllltent <lOuA .
r
·
r
~u t .curren( :>JuA
"t
.
Bu e Cvfr. rt 0uA
•
.a IC( Q1)
, 2. •• .. su 6U 7•
U_UCC
I. ,. ,. 11. tau tau ,.. ".
Figure 7.11 - Characteristic curves for Q2N3904.
Se miconductors 7-7
Current" and each current trace has been labeled with its associated base
current. This is a typical output plot for an NPN BJT. The a ftA trace at the
bottom of the plot indicates that the transistor is in cutoff. With IBASE =
a ftA, there is no base current to forward bias the base-to-emitter junction,
therefore there is no collector current since the collector-emitter junction has
an enormous internal resistance at this time. As the base current increases,
an increase in collec tor current can be observed. This relationship will
be maintained until the maximum base current and supply voltage have
been reached, at which time the transistor is in
2
saturation.
Next, the same simulation will be performed
on the PNP BJT. This transistor relies on the
same principles of operation as the NPN , the
Q2N 3906 vee
15V -=- only difference being the physical makeup. The
IBASE
01 e
configuration of the N-type and P-type materials
100 uA ~ are inverted in the two transistor models, hence
the names NPN and PNP. To compensate for this
difference in their composition, our schematic
design will vary slightly from the last exercise.
-0- 0
Note that in comparison to the previous design,
the transistor used in the design of the circuit in
Figure 7.12- PNPBJT test circuit schematic using
the model Q2N3906. Figure 7.12, a 2N3906 (PNP) has been inverted
Simulation Sett ings . Characteristic Curve PNP
L~ion Rl~ I ~ala CoIection I Probe Wlndow [

Sweep variable
[OCSweep ... 1 (~ Vo ltage source Name: vee
CJ Current sourc e
Options:
ll.J PrimalySweep
--- - - -- o Global pererneter
G Model parameter
lil SecondaJY Sweep
[ ] Monte CariolWorstCase
o Temper ature Peremeter n ame
D ParameiricSweep
!'JTel11Perah...., (Sweep) Sweep t~ p e
[ ]Save Bias Point Start value: [].I
(~; Linear
[J wad Bias Point ( ~--- --~ End value: 15\1
o Logarithmic '-- ,
Increment: _015\1
G Value list
OK II Cancel II fwly II ~
Figure 7.13- Simulation settings for primary DC Sweep.
7-8 Chapter7
with respect to vee to ensure that the emitter now has a greater positive
potential than the collector. Also, our current source, IBASE, has been
reversed in order to forward bias the base-to-emitter junction. The BJT
in this design shows a small gap in the path at the emitter terminal. There
is a compl ete path at each at this node, but it doesn't happen to be shown
with this particul ar OreAD schematic symbol. Rarel y, you will notice
discrepancies like this with certain component s in the PSpice library.
As can be seen in both Figure 7.13 and Figure 7.14, the same
simulation parameters have been used in this example that were used with
the NPN model. Note that you could have kept the same schematic layout
from the previous example and used it in this example with the 2N3906
and achieved the desired result. You would, however, need to modify the
simulation paramete rs by defining them with negative magnitudes in the
SIMULATION SETIINGS window, so instead of sweeping from 0 V to 15 V
you would be sweeping from 0 V to - 15 V.
Thi s simulation produ ces almost an ident ical output plot (see Fig-
ure 7.15) to the one shown in Figure 7.11. The plot of the emitter current
curves seen in Figure 7 .15 are typical of a BIT. As the magnitude of the base
current increases, the collector/emitter current will increase.
Simulation Setting s - Characteristic Curve PNP

.,- "I """ 1,
",,-. . :~ .
~ ffialysis ICoriigl.raIion Files I Options I Data CoIeclion I Probe Wnd ow I

ffiaIysi. type : Sweep variable
l oc Sweep
"1 o@ Vollage source Name: IBASE
Options:
Current source
e Global parameter Model lype: I ,.1
IWl Primary Sweep o Model parameler Model name: I I
-.
lEi Monte CarlolWorst Case o Temperalure F'ar.9meter name:
~~
LJ Parametric Sweep --
Ll T~ (Sweep) Sweep lype
EJ Save Bias Pori @ Linear
Slarl value: IlI\
EJ load Bias Point
e Logarilhmic IDecade . ] End value: 100uA
Increment 20uo:\, I
<:) Value lisl I I
I OK JI Cancel II ftwIy II Help I

Figure 7.14 - Simulation settings for secondary DC Sweep.
Semiconductors 7-9
,-
·
E
·, .-
t
t
~ S. Curt.nt ,ro..o.
H. Currerl'l llOuA
C
"r-
, r-:- .., Corr,nt 600A '
·
"t
,-
,n e Culrent 2!l<>'
. .
ai. cun-,nt OUA'
.
OIl
JE(Q 1}
1U
'" ' U 50 ' U 'U
u_uee
' U 9U 'OIl 11U 1fU 13U t .. 15U
Figure 7.15- Characteristic curves for Q2N3906.
Junction Field Effect Transistors

This same multiple-sweep procedure can be used to plot the characteristic
curves for other types of transistors. Next we will look at another type of
transistor - the junction gate field effect trans istor (JFET). Curves will be
simulated for both the N-Channel JFET and P-Channel JFET.
Figure 7.16 features a 2N5486 N-Channel JFET and two dc voltage
sources. As in the previous example, this JFET shows small gaps in the path
at both the drain and source terminals. There is a complete path at each of
these nodes .
One de source is the supply voltage to the drain, VDD, and the other will
be swept to vary the gate voltage, VGG . As the gate voltage of a JFET varies,
a change in current can be observed across the channel of the transistor
2
Figure 7.16 - N-Channel
JFETtest circuit
schematic using the
model 2N54861PLP.
VDD
J1
.:.L
2N5486IPLP~
15V _
1- 7' 0
7-10 Chapter 7
that exists between the source and drain terminals. The gate voltage will be
adjus ted in incremental steps similar to the way that the base current was
modified in the case of the BJT. The voltage across the transistor will sweep
at the same time to produce the set of characteristic curves for the JFET.
As previously stated, the supply voltage will be our primary sweep, and
will range from 0 V to 15 V, with data points plotted in 0.015 V incremental
steps (see Figure 7.17).
The secondary sweep of this simulation profile will be that of the gate
voltage (see Figure 7.18) . The voltage at the gate of the transistor will vary
from -4 V to 0 V in 1 V increments. This is an N-Channel JFET, meaning
that the voltage source VGG is connected to a P-type material. Applying a
negative potential to the gate will widen the depletion region between this
P-type gate, and the N-type channel, thus restricting current flow across the
channe l of the transistor.
After running the simulation, a plot will be generated similar to the one
shown in Figure 7.19. Each of the drain current traces have been labeled
with their associated value of gate voltage. As projected, when the gate
voltage is 0 V, current through the channel is unre stricted. As the gate
voltage increa ses in the negative direction, the channel current decrea ses.
Simulation Sett ing s - Characteristic Curve N Chan
Jlnalysis type :
locsweep Name: VDD
Current source
Wions: Model type:
~ Global parameter
~ .. ~ Model parameter
Model name: II
~ Secondary Sweep ~=::=::::;
lEI Monte CariolWorst Case t) Temperature Parameter name: L -_ _- '
I' ,
D P~ Sweep
D TefIll8l'lltre (Sweep) Sweep type
[J Save Elas Port @ Linear
Start value:
[J load Bias Point 15V
~ Logarithmic IDecade ...1 End value:
0,015V
Increment:
t) Value list
OK ) I Cancel II PWt II ~
Figure 7.17 - Simulatio n settings for primary DC Sweep.
Semiconductors 7-11
The current decreases as a direct result of the enlarging depletion region
until it completely closes off the channe l. The voltage across the gate that
will yield no current flow across the channel is referred to as the pinch-off
voltage . Looking at the plot below, the trace for VGG = -4 V either is or
exceeds the pinch-off voltage . It is apparent with this trace that the channel
has been closed completely since the drain current is constant at 0 amperes .
Next we will plot the characteristic curve for a Jl75 P-Channel JFET.
Figure 7.20 is very similar to the layout of Figure 7. 16 but varies slightly in
Jlna/ysis t;pe: Sweep variable --

[OCSweep ~I @ Voltage source Name: VGG
e') Current source
Options: h,j odeI type:
e') Globalparameter
~ PJimary Sweep Model name:
6 Model parameter
~ Secondary Sweep e Temperature Pa remeter name : L-- ---.J
EJ Monte CariolWor.>t Case
II] Parametric Sweep
.- Sweep type
[J T~ (Sweep)
!EJ Save Bias Point @ Linear
Start value: -4V - jI
I
IDecade ~ I End value:
[J Load Bias Port rN
6 Logarithmic
Increment: lV
<D Value list
OK ) I Cancel I[ ~ II ~
Figure 7.18- Simulation settin gs for secondary DCSweep.
I
"
··• ,... _. G.tI! Volt.~ eN.
c ,- .
7 .
··· ... /
" . . .
. .
G~le Voll ",g. = ~1V
n ~.
t /"
.. I~
. .
V K;aleVattag• •2\1.
a,t,Yo!t:ll9 t -~ .
.. ID( J1 )
,- 2_ >U
.- su
.- 1_
.. _
eu ,- ,. 11_ '2_ ,,- , .. 15_
Figure 7.19- Characteristic curves for 2N5486.

-
7-12 Chapter 7
2
0
VDD
1 Jd ~[ 15V ..:..--.!::-
4V L J175JPlP -T
Is
-T VGG
I
1-=- 0
Figure 7.20 - P-Channel JFET test circuit schematic using the

I
model J175/PLP.
. Simulat ion Settings - Characteristic Curve P
Analysis type : Sweep variable

@ Voltage source Name: VDD
(() Current source
Options:
a Global parameter
~ Prvnary Sweep 5 Model parameler
Model name:
~ Secondary Sweep
[[] Mort e CarlolWorsl Case
<:) Temperature Parameter name: L- .JI f
[J Parametric Sweep
D Temperature (Sweep) Sweep type
rJ Save Bias Poirt @) Linear
Start value:
e Logarithmic [ Decade I End value:

~ load Bas Poirt
T 15V
Increment: O.015V
a Value list
OK II CiY1cel II PcPiY I[ ~
Figure 7.21 - Simulation settings for primary DC Sweep.
Semiconductors 7-13
the same manner that the circuit was modified from the example of the NPN
BJT to the PNP BJT. The modifications to the circuit shown in Figure 7.20
are to compensate for the physical construction of this particular transistor
model. This is a P-Channel JFET. That means that the voltage source VGG
is connected to an N-type material. Applying a positive potential to the gate
will widen the depletion region between this N-type gate and the P-type
channel, thus restricting current flow across the channel of the transistor.
The orientation of voltage source VDD has been changed from the
N-Channel design to accommodate the P-Channel transistor model, so
again, we will be sweeping from 0 V to + 15 V, with data points marked in
0.015 V intervals (see Figure 7.21).
Figure 7.22 illustrates the simulation parameters of VGG, the voltage
source applied to the gate. VGG will sweep from 0 V to 4 V in 1 V incremental
steps. This will provide an output plot consisting of five channel currents,
one for each gate voltage.
With a current marker placed at the source terminal it is evident that
this P-Channel JFET exhibits similar behavior to the N-Channel JFET.
According to the output plot generated in Figure 7.23, with a potential of
o V applied to the gate the channel current is unrestricted. As the potential
at the gate increases, the channel is eventually pinched off.
Simulation Settings - Characteristic Curve P '~'-'

..~ .. "",- . _-:a:.' ~ .• "'...,.
Ma~'Sis type: Sweep variable

[OC Sweep ... 1 @ Voltage source Name: VGG
Options:
o Current source Model type:
C) Global parameter
~ Pnmary Sweep o Model parameter Mod~1 name:
~ Secondary Sweep
() Temperature Parameter name
D Monte Cano/Wors! Case
EJ Parametric Sweep
[J Temperature (Sweepl Sweep type
[J Save Bias Point Start value: rN
o Load Bias Point @ Linear
0-- - '--- - -, End value: 4V
() Logarithmic '--~•., J Increment: -, V - - -
('J Value list
OK )1 Cancel 1L~~LJ [ Help
7-14 Chapter 7
s . ...
·
"
r
·, PM'VoIt.
e fN
....----
~
,
·,...
"t
JlIlIIII
/
v Gat. VoltIV' - IV
~
V
,... /
j
ltI. VOll:ag. 1'1
. 011
,_ ZU ,. . M•
SO
.
a"Vclagt lV
6_ 7U I- 9U 1011 11_ m ,,- .

, 15U
• 1S (.J 1 )
U_UDD
Figure 7.23 - Characteristic curves for J175.
M etal-Oxide-Semiconductor Field-Effect Transistors

The last type of transistor that will be covered is the metal -oxide-
semico nductor field-effect transistor, or MOSFET. For this last example,
we will use a relatively common N-Channel 2N7000 low-power switching
MOSFET. This is an enhancement MOSFET, which will be tested using
the schematic design shown in Figure 7.24. These enhancement MOSFETs
differ in constru ction from a traditional JFET due to the configuration of
the gate and the presence of an inversion layer comprised of Si0 2 . With
the N-Channel MOSFET, both the drain and the source connect to two
isolated N-type materials that are separated by a larger quantit y of a P-type
Figure 7.24
-N-Channel
r- ---, 2 enhancement
MOSFET
test circuit
schematic
using the model
2N7000.
1
lV
LVGS 15V~~
VD D
J
Semiconductors 7-15
material. The gate connects to the Si0 2 layer instead of either of the doped
semiconductor mater ials. With an N-Channel MOSFET, as positive potential
builds at the gate, it repel s the net positive charge of the P-type material,
creating a channe l between the two previously isolated N-type materials and
allowi ng for current flow between the drain and the source.
As with all the previous examples, the supply voltage VDD will be
the primary sweep and will range from 0 V to 15 V, marking data points in
0.015 V interval s (see Figure 7.25).
The parameters of the secondary sweep define the behavior and the
range of voltage source VGS, the voltage applied to the gate. This voltage
source will start at 0 V and adjust toward +5 V in 1 V increments. These
parameters are shown in Figure 7.26 .
The characteristic curves for this MOSFET are shown in Figure 7.27 .
Referri ng to the bottom traces in the plot for VGS = 2 V, 1 V, & 0 V, the potential
at the gate was not sufficient enough to create a depletion region in the P-type
material and allow current to flow between the N-type terminals. When VGS
was increased to 3 V,the potential was significant enough to create a channel
for current flow, and that channel only grew as VGS increased, as evident in
traces VGS = 4V and VGS = 5V.
Sweep variable
(~, Voltage source Name: VDD
Options:
o Current source
C) Global parameter
D Secondary Sweep
o Model parameter
o Monte CarlolWorst Case () Temperature
o Parametric Sweep
o Temperature (Sweep) Sweep t~p e
o Save Bias Point @ Linear
Start value: IJI/
LJ Load Bias Point r~ · ·· · _· ··_~ End value: 15\1
() Logarithmic L.... _ _ ••. .J
Increment .015\1
o Value list
OK ) I Cancel Help
Figu re 7.25 - Simulat ion settings for primary DC Sweep.
7·16 Chapter 7
Analysis type: Sweep variable
loc Sweep ~I I~J Voltage source Name: VGS
~) Current source
Options: Mc,dl;'l type:
<:) Global parameter
[l] Primal)' Sweep Model name:
<:) Model parameter
o
El
Secondary Sweep
Monte CarlolWorst Case
o Temperature Parameter nome:
ElParametric Sweep
[J Temperature (Sweep) Sweep type
[J Save Bias Point @ Linear
Start value:
EJ Load Bias Point
Cl Logarithmic [ Decade
~ I End value:
Increment: 1V
V Value list
OK II Cance II Ppply II Help
...-
0
r
i
~S~ 5V
"
~ ..
-, .>
.
r- V
V
r
"t i'Gs ~,v

2._
V
. Ii
III
II 1( " 1: d )
lV 2V 3V .V 5V
f1;s~;'
k;S a 2V,1
6V
.a ov
1V
U_UDD
.v ,V 1 11I " V , 2V 1 3V
". 15.
Figure 7.27 - Character istic curves for 2N7000.
Semiconductors 7-17
Design Problem
For the last example in this chapter, the transistor can be demonstrated
in a practical circuit while we build further upon the concept of the DC
Sweep simulation profile in a design application. Assume that we are trying
to design an audio amplifier represented in the schematic design of Fig-
ure 7.28. This circuit utilizes the 2N3904 NPN BJT seen in the second
example in this chapter in a common emitter configuration. The potential
established between the voltage divider of R1 and R2 will be used to bias
this basic transistor amplifier circuit. Without the capabilities of this kind
of software, you would have to sit down with spec sheets and scratch paper
and carry out numerous calculations to determine how to properly bias this
amplifier or one like it.
The Cadence software allows a user to sweep not only the values of
a voltage or current source, but individual component values as well. This
can be especially helpful in the instance of trying to bias an amplifier such
as the one in Figure 7.28.
One can begin by constructing the schematic design shown using the
DreAD software. Instead of entering a value for R2, the bottom resistor of
our voltage divider, enter "{RVAL}". Next, search the Component library
for the component PARAM and place it anywhere on the schematic page .
.:.LVCC
20V~
R1 RC
40k
~ .7k
C2
l VOUT
,~
C1 01
i
1 1fO
-U-----''+--- -10
-B
' -l E0 2N:;04 PARAME T ERS:
RVAL = 2k
V IN
<:
VOFF =O R2 < 47k
VAMPL = 250mV RE RLOAD
FREO = 1k {RVAL} 470
AC = 1V
Figure 7.28 - BJTamplifier circuit with sweepable R2.
7·18 Chapter 7
cadence .. " .1
I - ....tl!i
' I fill
- ro Maw J
-
"..
..... _
....... fL1
.
-. - ......
. ....
~
.... ._--- ....

l. _y .c..-., ~
I,•
;~
...
:~ - -
.... ,_ --
...............
"""'.......
~C; .
-r'
$CC.IMTlCt; "'C;U
'" Nl)O[S(fl/SPfOl.l
II , I ..
1otOC£S(1:1$,,£Qfrr4
I ~~
_. -
a
.
Figure 7.29 - PROPERTY EDITOR for PARAMETERS component, RVAL column has been selected to be modified.
Simu lation Settings · bias ~

1- - - ---
~ Malys;s I~ Res I ()ptiom I DataCoIedion I Probe Wndow I
tfI a1ysis type: Sweep variable .-- -.. _._- - _._ ._- -- - ----- - - -
[OCSweep ·1 <:)~ oltage source
CO ];;urrent source
tjame: I I I
I
Model t!ipe I "I i
Qplions :
~. , ... @ Jalobal parameler
l!5 Model parameter Mo d~1 name: I I :i;
IE! Secoodery Sweep ~ Iempera lure Earameler name: RVAL
ElMonte CarlolWor.;t Case
IE] Parametric Sweep - -- - - - - ---I
--- --- .-_.. - -
[E] Temper<lhre (Sweep) - Sweep type -_._--- - - -------------.

[E] Save Bias Point Starl value: 1k
@ !,inear .- ..
EI Load Bias Pori
End v,glue: 33k
e Logarilbmic [ Decade "1
Increment: ~_:::J
t) Value li£l I I
---- --_.- - - -- -- - _.-
I OK J[ Cancel 1[ !lPr*f I[ ~ I
Figure 7.30 - Sweep characteristics for the RVAL parameter.
Double-click on the newly placed parameter component to display its

properties.
Next search the Component library for the component PARAM and
place it anywhere on the schematic page . Double-click on the newly placed
PARAMETERS: component to display its properties, as seen in Figure 7.29.
Create a new column titled "RVAL", the value you declared for R2. For this
property, you can insert any value of resistance that you desire, and if you
were to run a Transient Analysis, this is the value that you would use. For
Semiconductors 7-19
j:~ ~:~ :1$ty~E!IiTiIilEEr r:if :l::i1r rEi f
.. ~ f~~T r E ··. jTfEl E!EjlEF Ei Ei.·••••••iFrr
,
[]] .. U(C.E) [l]
SIC
. I C( Q1 )
1. 1511: 2 011: 2SK 3. 35K
RUAl
Figure 7.31 - PSpice output display ing effects of the sweep on the BJT amplifier.
the purpose of the DC Sweep this value will not be considered. For now a
value of 2 kQ has been entered.
For the purpose of this example, a value of R2 needs to be established to
properly bias the amplifier. This can be determined by measuring the collector
current and collector-emitter voltage while sweeping the value of R2. To
accomplish this, create a DC Sweep simulation profile (see Figure 7.30) . In
the SWEEP VARIABL E portion of this windo w, select GLOBAL PARAMETER,
and for a parameter name enter "RVAL", the same value that you declared
for the component R2. This GLOBA L PARAM ETER sweep function refers to the
PARAMETE RS: component placed on the schematic page . Remember that the
PARAM component is associated with component R2 using the declared value
"RVAL" and will sweep the value of this resistor based on the limits declared
in the bottom portion of this window. According to these constraints, R2 will
sweep from I kQ to 33 kQ in 100 Q increments.
After running the simulation, plots resembling Figure 7.31 are generated
as a result of the voltage and current markers in the schematic design. They
have, of course, been manipulated slightly in the PSp ice PROBE window to
make them more legible. A BJT can be thought of conceptually as a voltage-
controlled resistor. The top plot illustrates this point as a trace expression
and has been entered as "V(C,E)/Ic(Q l )" to plot the internal resistance of
the transistor. As the value of R2 increases, the base voltage increases and the
resistance of the transistor drops. As this change occurs, observe the bottom
plot. The bottom plot consists of trace s plotting both collector current and
collector emitter voltage with respect to the value of R2. As the resistance of
7-20 Chapter 7
3 4
l vcc
'JfN ~
Rl RC
40k
4.71<
C C2
YOUr
VlN
Cl
2
Q1
BY'
lOU
I' .v
<~~
10U PARAMET ERS :
"' Q2N3904
E RVAl - 3.5k
VOFF =O R2 471<
VAMPL = 250mV RE RlOAD
FREQ = 1k (RVAL) 470
AC = 1V
-l- ~O
Figure 7.32 - BJT amplifier schematic with new R2 value.
·, ,...
U
' .IU
1 ~ ~ ~ ~
··
t
II I .
IU
I/ \ . .
I \ I \ / \
- 2 . 1U
1\ · .
\ ......... 1 :\ j
. .
........
1\ ......... /
1/ :\ j .
. .
I'-'
. .
-3. au
Is
o U( UI " }
O. oUJs
• U( 1I0UT)
' .IM 1.2,.5 1.6n5 ,.-
" ..
2 .lins 2.IM 3 .2M 3 . 611III5
..-
Figure 7.33 - Transient Analysis with R2 set at 3.5 kO.
the transistor drops, the collector current increases.

At the beginning of the sweep, and soon after R2 begins to change,
the transistor is in cutoff. Looking at the plot it is easy to find a value of
resistance that is right in the middle, in a linear mode of operation, between
a state of cutoff and saturation. That value is a 3.5 kQ .
With this newly obtained value of resistance, you can refer back to the
original design (see Figure 7.32). Inside the paramete r component on the
schematic page, change the value of resistance to 3.5 kQ and create a new
simulation profile for a Transient Analy sis. Place voltage markers at the
input and output of the circuit and run the simulation.
Figure 7.33 plots the output voltage alongside the input voltage and
Semiconductors 7-21
demonstrates the proper bias of this transistor circuit using a value of 3.5 kQ
for R2. This choice for a resistor value yields a clean output with the proper
headroom. This was done without any additional freehand computation and
further showcases the comprehensiveness of the OrCAD/PSpice software.
In Summation
Now that you have an introduction to semiconductor components, you
can start to take better advantage of what the OrCAD/PSpice software has
to offer by designing and simulating circuits with practical applications.
These types of circuits are discussed further in Chapter 11.
7-22 Chapter 7
Chapter 8
Miscellaneous
Components
Up to this point, we've touched upon the most basic passive components
and some of the semicond uctor models available in the PSp ice software.
Before moving into sample circui ts and other advanced operations of
the software, let's discuss some of the other component models that are
available . The components to be discussed in this chapter will be switches,
op-amps, and transformers. We'll begin with switc hes.
Switches
There are two types of switches are available in the PSpice library -
Sw_tClose and Sw_tOpen. The letters "Sw " denote that the component
being used is a switch. These switch components can be used only with
the Transient Analysis simulation type. Their operation depends on a value of
time that is declared by the user for when they will either open or close. The
component Sw_tClose is a switch that
is initially open, but will close at a
TCLOSE= 1m
time that is declared by the user. This
type of switch is utilized in the sche-
~2
2
matic design shown in Figure 8.1.
Figure 8.1 is a simple series
lV1 circuit with a 10 V source connected
10V - ~ RLOAD
> 1k to a 1 kn load resistor. A Sw_tClose
switch component has been placed
in the series path between nodes 1
and 2. As stated, this switch is open
and will close depending on the user-
defined parameter of time. Referring
again to the schematic of Figure 8.1,
Figure 8.1 - Schematic design wit h closin g switch.
this parameter is titled TCLOSE and
Miscellaneous Components 8-1

has been set at 1 ms. A Transient Analysis simulation profile has also been
set up to run for a total of 2 ms starting at a s with a step size of 2 us (see
Figure 8.2).
The load voltage has been measured during this Transient Analy sis
simulation and plotted in the probe graph shown in Figure 8.3. This is a
result of placing a voltage marker on node 2 of the schematic design. From
a to I ms there is no load voltage present. The switch is initially open, so
there is no current flow through the series path. At 1 ms, the switch closes,
Simulation Settings - SWClOSE
~stype :
ITme Domain (fransiert ) ~ I flun to lime: 2ms . seconds (TSTOPJ
lilarl savingdata aller: 0 seconds

Qptions :
Iransienl oplions
D Morte CariolWorstCase Ma"imumslep size: ~ _J seconds
ICl Parametric Sweep
D T~ (Sweep)
ICllikip the iniliallransienl bias poinl calculalion (SKIPBPj
[] Save Bas Poirt
[] lo ad Bias Poirt
L!Save 01eck Port.
EJ flun in resume mode IOulput f ile Options... I
ICI Restart SinUation
OK II CwlceI II f:9i*t I[ ~
Figure 8.2- SIMULATION SETIINGS window,Transient Analysis.
11. 1U
·• ....
l
. . . . · · · ·
·,
u
1
··• .... . . . . · · · r-
. · · · ·
IS 1.2M , • .lIlK 1 . 6M I . IM 1._ 1 .211$ 1._ 1. 6as 1 . 11IlS 2.-
o U( 2 }
n ..
Figure 8.3- AMS Simulator window measuringload voltageas the switch closes.
8-2 Chapter 8
and from I ms to 2 ms the 10 V dc source voltage drops across the load
resistor.
Conversely, the component Sw_tOpen is a switch that is initially closed.
It will open at a time that is declared by the user. This timing parameter
is called TOPE N. To illustrate how these switches can modify the behavior
of the most basic circuits, both Sw_tOpen and Sw_tClose will be used in the
TOPEN =10m TCLOSE =20m

~0~0 2
3
~v
~VDC
12V -=-
1 ~.r C
S: R
1k
-T 47u
I
o
Figure 8.4 - Schematic design using both opening and closing switches.
SimulationSettings - SWBOTH
Run to time: 30ms seconds [TSTOP)
Startsaving data after: 0 seconds
- ..
Option.:
'-; Trensient options
EJ Monte CarioIWorslCase Maximum step size: 150us seconds
LlParametric Sweep
EJ T~Lre (Sweep) D Skip the initial transientbias point calculation (SKIPBPJ
o Save Bias Poin!
EJ LDad Ilia. Port EJ Run in resume mode IOutputFileOptions.., )
[] Save 01eck Points
o Restart Simulation
OK II Cancel II ~ )I ~
Figu re 8.5 - SIMULATION SETTINGS window,Transient Analysis.

v
I·, 12.50\'
. w,.,12V . . . . . . . .. . . . . ..
·· . "' / .
~
I
.. .. .. . .
.. . . · . . . ... . . .
.. ..
/
,
l ' .15V + +
~c h :OO 0P:tns a1:1£ln'\$ :
• + ;-
· . . 4-
.. + . +
... +
- : · . . . . . . .
Svdchoc Cion! ac 2OIns . · . . ... . . . .
SEl» · . . ... .. . .
10.00"1
• Val
·
u
1
. SwitdflJC Closn at 2Oms'
··• ::] . .
"I.- ....
t
+ . .. .. .. .. .. ..
.
Is
U(3)
,
."" ..,. ,... .... ,_, "0$ "0$
TI..
,... .
" ...
. .,"" ...I. :
21 ...
.-1
Figure 8.6 - AMS Simulator window measuring node voltages as the switches open and close .
simple parallel RC circuit shown in Figure 8.4. The switch that is initially
closed lies between nodes 1 and 2 and will open at 10 ms, while the switch
that is initially open lies between nodes 2 and 3 and will close at 20 ms.
A Transient Analy sis will be carried out on this schematic input file. It
will start at 0 s and run for a duration of 30 ms with a defined step size of
150 us. These simulation parameters have been defined in the SIMULATIO N
SETT INGS window shown in Figure 8.5.
The top plot of Figure 8.6 is a measure of the voltage from node 2 with
respect to ground. The bottom plot depicts the change in voltage measured
from node 3 with respect to ground as this Transient Analysis takes place.
Let' s refer to the schematic design shown in Figure 8.4. The switch
UC, Sw_tClose is initially open for the first 20 ms of the simulation, and the
switch UO, Sw_tOpen is closed for the first 10 ms of the simulation. For the
first 10 ms of the simulation, the 12 V de source is connected only across
the 47 ~F capacitor. The capacitor charge s almo st instantaneously, and after
10 ms, the switch UO opens. At this time, the source VDC is no longer
connected and the switch UC has not yet closed, so the capacitor remains
charged until 20 ms. At 20 ms, the switch UC closes, and the capacitor begins
a steady discharge acros s the I kQ resistor that will last a period of 5 r
(235 ms) that exceeds the range of the Transient Analysi s.
Operational Amplifiers
As you can see, switches can provide great versatility to the operation
and functionality of a circuit. They can aid its operation by either turning
a circuit on and off, or they can add additional branches that will modify a
circuit's behavior during a Transient Analy sis.
Figure 8.7 features a model of the common uA741 operational
amplifier. Even in the OrCAD/PSpice software environment, the schematic
8-4 Chapter 8
3
>
RI 1t>---=--- - - 1>--- - - -----,..V,OUT
2 v
VIN
uA741
1k
VSIN RLOAD
1k
"-' RF
VOFF =O
=
VAMPL 250mV
FREQ= 1kHz VDC+ VDC-
AC =OV 3k <;> <;>
I v+ v-
~1 5V 1-
_ 15V
-=-0
1 I
Figure 8.7 - Op-amp schematic using an inverting configuration.
• • • • • • • • • • • •• • • c~a~d2e~n~ct;!e~f;~~. i;!lx
1fl~1 symbol maintains the typical pinout for a
uA741 package. Pins 1 and 5 are the offset
null pins, pins 2 and 3 are the inverting
and non -inverting inputs, respectively,
pins 4 and 7 are used for power, and
pin 6 is the output. For the purpose of
this example, the usage of the uA 741
will be demonstrated with an inverting
configuration. The circuit has an input of
250 mV at 1 kHz .
This schematic design uses power
terminals to connect de voltages to
pins 4 and 7. These terminals come in
especially handy when working with
O ll etG(04) POM:f
tJ ShowUcNom<d N"G,,,,,,
complex designs or circuits that use
multiple voltages. Placing a voltage
Figure 8.8 - PLACE POWER butto n high lig hted and PLACE POWER
source schematic symbol numerous times
window active displaying vcc terminal component. in a schematic design or placing a voltage
source schematic in a confined space can
make your design appear messy. In the toolbar to the right side of the DreAD
interface, click on the highlighted icon to display the PLACE POWE R window.
This is shown alongside an active PLACE POWER window in Figure 8.8 .

The VCC component can be used as a reference terminal for power in the
schematic design . In terms of the schematic design shown in Figure 8.7, it
has been used a total of four times. Because of the feedb ack loop from pin
6 to pin 2, it would have been too cluttered to place a VDC component and
ground symbol in that small space . A VCC terminal was placed on pin 4 and
was renamed VDC-. A second VCC terminal was placed in an open space
in the schematic design and given the same name of VDC- . This floating
(not connected) VDC- terminal was then connected to the negative side of
a 15 V de source. The positive side of the voltage source was grounded.
This creates an indirect schematic path between pin 4, the negative voltage
source, and ground . The same proce ss was repeated with the second pair of
VCC terminals using a reference name VDC+, indirectl y attaching a positive
15 V de source to pin 7 of the operational amplifier. Assuming that we are
working with a larger circuit consisting of multiple op-amp s, these terminal s
VDC+ and VDC- can be used repeatedly, anytime these positive or negative
15 V potentials are required .
A Transient Analysi s is performed on the circuit of Figure 8.7. These
simulation parameters are shown in Figure 8.9. The simulation will start at
o s and end at 2 ms with a step size of 2 I!S.
The feedback resistor, RF, in the inverting op-amp circuit is 3 kn and
ffialy$. type:
ITille Oomail (fr.wieft) ... 1 Run to time: 2ms ' seconds IT STO PI
Start saving data after: 0 ; seconds

Options :
Transient options - - - '- - "'--'
EJ Marte CarioIWOlSl Case Maximumstep size: ~ lseconds
IEjPir<lII1etric Sweep
ID T~ (Sweep)
, EJ Skip the initial lransient bias pointcalculation ISKIPBPJ
IDSave Bia . Point
ID Load Bias Port
IDSa ve Oleck Pcirt.
EJ Run in resume mode IOutput Fie Option.... I
~ Re.tart Sirnjalion
OK II Ca1cel II ;wy II ~
Figure 8.9 - SIMULATION SETII NGS window,Transient Analysis.
8-6 Chapter 8
......
......
...
-.._+---~-=--~---~---,----~--~-=--~---~---,-----H
's ' . 2J1lS as •.,,,s 1. _
a U( UOUT) • U(U IH )
I .•
Ti ne
1 . 2 J1lS
Figure 8.10 - AMSSimulator window measuring both output and input voltage of op-amp circu it.
1.6M
.. -
the input resistor, RI, is 1 kQ . Therefore, a calculated gain is expected to
be -3. With the 250 mV input ac voltage, this will yield an output waveform
with an amplitude of750 mV that is 1800 out of phase with the input signal.
Looking back at the input schematic file (Figure 8.7), voltage markers have
been placed near the ac source at net alias VIN and across the load resistor at
the net alias VOUT . The plot in Figure 8.10 shows a measurement of voltage
at net aliases VIN and VOUT. The relationship between the input and output
voltage is exactly as expected in terms of phase relationship and amplitude.
Transformers
The last topic of discussion in this chapter is the transformer. PSpice
features many different transformer models, both linear and nonlinear, with
multiple primaries, multiple secondaries, center taps, and with different
core materials. For the purpose of this example, we will use a basic linear
transformer with a single primary and single secondary (see Figure 8.11) .
.001
RLOAD
100k
~o
Figure 8.11 - Linear transformer circuit schematic .

The primary is connected to a I V ac source and the secon dary is connected
across a load. The frequency of the ac source is 60 Hz.
To explore the parameters of the transforme r that can be modified,
double-click on the component TX 1 to ope n its PROPERTY ED ITOR (see
Figure 8.12) . For the basic linear transformer, the main parameters are
COUPLING, L1_VA LUE , and L2_VALUE .
The numer ical value in the COUPLI NG column ofthe PROPERTY EDITOR
is representative of the coupling coefficie nt of a transformer. The coupling
coefficient ranges from 0 to I and is essentially a ratio of how much of the
magnetic flux from the primary reaches the secondary. In regard to a physical
S"" IP""" b GA3.oc>J· l~ PAGE,' I SOl£HAlL'j
Location X-COOf'<finate Location Y-CoonIiNlte Source Part

100 320 XFRJ.CUfJEAR ~I
Figure 8.12 - PROPERTY EDITOR window XFRM_L1NEAR component.
Figure 8.13 -
SIMUL ATION
SETTINGS window,
Transient Analysis.
[Tone Dam.... (Tr<mieri ) T I Run to time: 32ms seconds (TSTOPJ
Startsaving data after: 0 seconds

Options:
";/ Transient options
EJ Morte CartolWetSl Case Maximumstep size: 32us seconds
EJ PilI1ln1eIric Sweep
EJ T~ (Sweep) [] 5kip the initial transient bias point calculation [5KIPBPJ
EJ Save Bas Pori
E] Load Bias Pori
[] Save 01eck Poris
EJ Run in resume mode IOutputFie Options... I
[J R.e.tart SirTUation
OK II CmceI II fwIy II ~
8-8 Chapter 8
transformer, a transformer is tightly coupled if the primary and secondary
coils are in close proximity to each other and a majority of the flux from
the primary reaches the secondary. Transformers have loose coupling if the
coils are distant and little of the flux from the primary reaches through the
secondary. Tightly coupled transformers have a coupling coefficient that is
close to 1. In this example, we are dealing with an ideal transformer, so the
coupling coefficient has been declared as 1.
L1_VALUE and L2_VALUE are the inductive properties of what are
the primary and secondary windings in this circuit. For this example, the
inductance of both the primary winding and secondary winding have been
set at 10 !tH.
A Transient Analysis will be carried out on this circuit that will start at
a s and end at 32 ms with a step size of 32 us as shown in the SIMULATION
SETTING S window in Figure 8.13. This run time has been selected to
display an output plot that executes just under two complete cycles of the
output waveform.
With the voltage marker placed at node 3, the output plot (see Fig-
ure 8.14) displays the output voltage that is measured across the 100 kO
resistor connected to the secondary winding of the transformer. Since this
transformer is an ideal linear transformer with a coupling coefficient of 1,
the amplitude of the voltage across the secondary is equal to the primary/
source voltage .
Lastly, we can use an AC Sweep simulation profile to measure the
frequency response of the transformer. Since we are working with a linear
transformer, it can be expected that a rather consistent output will be
measured throughout the frequency spectrum. Figure 8.15 displays the
simulation parameters for the AC Sweep. The logarithmic sweep will begin
at 10Hz and end at 1 MHz with 100 data points per decade.
·· vn 11\'
·•
1
t
s
1."
D.SU
,
:1 xn ~
. Y' ~ '\:
N:\( vi f\: ,:
:J/f'
:
- • •su : ,
~:
Yf
~ l .CIU
.
Is
U( 3)
2..
- 0.. ... 1_ 12 .. 1""5 16 .. 5
U ..
Figure 8.14 - AMS Simulator window plotting load voltage with respect to time.
" .. 2_ 22. . ,. .. 20"" " .. 3_ 32..

Again, the voltage marker has been placed at node 3 to measure the
secondary voltage in the probe graph shown in Figure 8.16. The output is
characteristic of a linear transformer and features a flat frequency response
throughout the range of the sweep .
Malysis type : AC Sweep Type

- ---
1/lC Sweep/Noise ·1 e> Linear Start Frequency: 10
Options: ~l Logarithmic End Frequency: lMeg
Genera! Settrlg1 IDecade · 1 Points/D ecade: 100

[iJ Monte CaI1olWom Case
EJ ParametIic Sweep NoiseAnalysis .
[J T~ (Sweep)
[J Save Bias Poirt LJ Enabled OutputVoltage' [ =-::J
tJ Load Bias Point IN Source: r---l
Interval: [~
Output File 0 ptions

EJ Include detailed bias point information for nonlinear
controlled sources and semiconductors I.OP)
( OK II Cancel I[ IwI:'I I[ ~
Figure 8.15 - SIMULATION SETTINGS window, AC Sweep.
·•
1 .1U
··•
t
1."
1.9 U
1. 111
1.1U
1 .6U
1.5 U
"'" • U( 3)
3M' "": 2 01Hz 1. OKHz 2 . 1KHz 1 0KHz 3 1KHz 11.Hz 31t1CH z 1 . DHHz
Fn quf'fl c,
Figure 8.16 - AMS Simulator window plotting load voltage wit h respect to frequency.
8-10 Chapter 8
In Summation
The se components can only further enhance the capabilities of the basic
design s discussed thus far. Chapter 11 will provide an in-depth examination
of circuit s with practical appl ication s and will showcase many different
types of sample circuits using them .

Chapter 9
Transmission
Lines
If you are using PSpice, the basic transmission line element is actually
considered to be lossless. This is quite reasonable for a circuit analysis
program with integrated circuit emphasis, since transmission lines used
within an integrated circuit (likely to be stripline or microstrip) are going
to be very short, both physically and electrically. The loss in a short
transmission line is normally quite small (a fraction of a dB) and, therefore,
negligible for most purposes.
If you wish to add loss to a PSpice transmission line, you can do so by
using lumped (as opposed to distributed) resistive elements. The dominant
loss mechanism in most practical transmission lines is the conductor loss due
to skin effect , not the dielectric loss. You can simulate a long and lossy line
by breaking it up into shorter sections and adding a small resistance in series
with each short section to represent the distributed conductor loss . Although
it is tempting to use extremely short sections (each with a very small series R
for loss), there is a tradeoff involved with this. In Transient Analysis, PSpice
will make the timestep (or internal computing interval) less than or equal to
one-half the minimum transmission delay of the shortest transmission line .
This can make a PSpice Transient Analysis take a very long time if short
transmission lines are used . Another problem is that transmission line loss
increases with frequency. It is not possible to specify a frequency-dependent
resistor, so line loss simulated by lumped resistors will be valid at only one
frequency. The PSpice limitation that transmission lines are lossless is not
a serious one. In the examples that follow, you will see that PSpice can be
used to solve an assortment of transmission line problems, which would be
all but impossible to solve in a reasonable time without a computer.
Transmission Lines 9-1

Transmission Line Length
Since there are two methods for telling PSpice the length of a
transmission line, it may be helpful to look at how each method works and
how to convert from one method to the other.
In general, we can say that the transmission delay, TD, of a transmission
line can be found from:
TD = Physical LengthNelocity
where Velocity is the phase velocity in the line, given by :
Velocity = (Velocity Factor) x (Free -Space Velocity)
The Velocity Factor is less than or equal to 1.00.
Also , the normalized electrical length, NL, is:
NL = Physical LengthlWavelength
where Wavelength is the wavelength in the line, determined by :
Wavelength = Velocity/Frequency
Normalized electrical length can then be expressed as:
NL = (Phys ical Length x Frequency)Nelocity
Since Physical Length =TD x Velocity =(NL xVelocity)/Frequency, then:
TD = NL/Frequency
and
NL= Freq uency x TD
Let's apply this information to a practical example. Say we have a
transmission line that has a characteristic impedance of 50 Q, is 12 meters
long, and has a velocity factor of 0.66. Now let's ask:
A) What is the transmission delay ?
B) What is the normalized electrical length?
We know that:
A) Velocity =Velocity Factor x (c), and c =3 X 108 mis, so Velocity =
0.66 x (3 x 108 mls) = 2 X 108 mls . TD = LengthNelocity = 12 mI(2 x 108
mls) = 60 ns.
B) Before the normalized electrical length can be determined, a
frequency must be specified. Let's use 30 MHz . NL =(Frequency x Length)!
Velocity = [(30 x 106) xI2]/2 X 108 , so NL = 1.8 wavelengths.
Each of these characteristics of a transmission line can be
modified using the PROPERTY EDITOR in the Cadence A llegro
Design Entryl DrCAD Cap ture schematic capture window. Each
characteristic of a transmission line is abbreviated in the PROPERTY
EDITOR as shown below:
Figure 9.1 - Transmission line • Design Frequency, F
schematic symbol (T/ANALOG in • Normalized Electrical Length, NL
the library).
• Transmission Delay, TD
9-2 Chapter 9
Opbc ns Window Help
il L seeree P~rt
t Hi SCHfUATlC1 : PA -/;" I T ,..;:x:N!
Figure 9.2 - PROPERTY EDITOR window for transm issio n line component.
These parameters will be adjusted in the example problems later in this

chapter to manipulate the behavior of each transmission line circuit. Figure
9.1 is the schematic symbol for transmission line in the schematic capture
software (T/ANALOG in the library) .
To modify each of these parame ters, double-cl ick on the transmission
line schematic symbol to display the PROPERTY EDITOR. In the PROPERTY
EDITOR , each of these characteristics can be modified to accommodate a
particular design (see Figure 9.2).
As with all the components discussed in previous chapters, a
transmission line component has a correspond ing element line in a circuit's
netlist. It is strongly recommended that users generate netlists of their own
transmission line designs in an effort to develop a stronger understanding
of the composition and purpose of a netlist.
Matched Load
This problem will show how PSp ice can be used in the time domain
to look at a single short pulse at the sending end and the receiving end of a
physically short transmission line.
Figure 9.3 shows a pulse voltage source , with 50 n output impedance,
V1 = OV
V2 = 10V
TO = 1n
TR = 1p
TF = 1p
PW = 3n
PER = 6n
7"0
Figure 9.3 - Transmission line circuit schemati c with matched load.

connected to a 50 n transmission line, which is terminated in a 50 n matched
load. The characteristics of the pulse are defined in the schematic design .
The initial voltage will be av and will rise to 10 V after a I ns delay. The
pulse will have a width of 3 ns and will have both a I ps rise time and fall
time . More information can be gathered from the schematic design shown
in Figure 9.3.
Transmission line T1 has a TD of 2 ns. We should, therefore, expect
[Tille Domai1 (Tramie1I ) ~ I Run 10lime: 7n . seconds (TSTOP)
Start saving data after: 0 seconds

0JXi0ns:
Transient options
[] Morte Or1oJWorst Case Maximum step size: ~ seconds
o Par.onetricSweep [] SkipIhe iniliallran,ienlbiespoinlcalculation (SKIPBP)
EJ T~ (Sweep )
[]Sa ve lias Poirt
[]load Bia. Poirt EJ Run in resume mode [ OlJ4lut Fie Option.... ]
o Sa ve Qleck Pon s
o RestartsmJation
OK II <:anca II tWiY II ~
Figure 9.4 - SIMULATION SEITINGS window, Transient Analysis.
5!P1
V
0
r
··
t
'.eN
, PULSE ATINPUTTOTR..A,NSMISSION lINE
2JN
eN
• val
• 5.SU
·, ....
1
··
t
PULSE ATlO.4DEr.o Of TR.A1'lSMfSSION UNE
2."
.
Sf D )
Is
D U(3)
I.Sns 1 . ltns 1 .S ns 2.ln s 2 .5n s :I .lns 3.5n5 11. 01\5 IJ. 5ns 5 . ens 5.5ns 6. lns 6.5ft5 7 . ln s
T1..
Figure 9.5 - AMS Simulator window plotting time delay between input end and load end of circuit.
9-4 Chapter 9
that whatever voltage changes appear at the input to the transmission line
(node 2) should occur 2 ns later at the output (node 3).
The PSpice SIMULATION SETIINGS window (see Figure 9.4) specifie s
that a Tran sient Anal ysis will run from 0 ns to 7 ns with a step size of
7 I-ts. The results of the PSpice Transient Analysis, displayed by PROBE,
are shown in Figure 9.5. Voltage V(2) is shown in the upper plot, and the
lower plot shows V(3).
The inpu t voltage, V(2) , rises from 0 V to 5 V at 1 ns and remains
5 V for 3 ns. The output voltage, V(3) , doe s the same as V(2) except that it
is dela yed by 2 ns. Since the transmission line is termin ated in a match ed
load, no reflections are seen. If the load is not matched, a reflection will
occur at the mismatch, and the input voltage will change at a time equal to
twice the transmission delay of the line. Thi s is the basi s of time -dom ain
reflectometry, which is used at the input side to examine tran smission lines
for defects . PSpice can be used to predict what a time-domain reflectometry
display should be for a cert ain transmission line circuit.
The last example in this chapter demon strates time-domain reflectometry
with mismatches between both generator/transmission line and transmission
line/load.
Balun Connected to a Voltage Source

PSpice will be used to determine the power bandwidth of a transmission
line balanced-unbalanced (balun) transform er. Balun s are used to connect
coaxial transmission lines to balanced tran smission lines or antennas,
and utilize a Vz wavelength section of transmission line to accomplish the
impedance transformation.
It is a very simple task to anal yze how baluns work at the design
frequency, where the line is indeed Vz wavelength long. However, it is not
at all simpl e to analyze how the balun will perform at frequencies above
or below the design frequ ency. PSpi ce can be used to great advantage to
perform a frequen cy sweep of the input voltage and to plot the output voltage
NL = 1 NL = .5
ZO = 75 ZO = 75
F = 100Meg F = 100Meg
R IN
~ '}i)VAC
-=- 0
Figure 9.6 - Transmissi on line balun circuit schemati c with voltage source .
Transmission Lines 9·5

versus freque ncy. We can tell the power bandwidth of the balun circuit by
observing when the output voltage magnitude drops to 0.707 of its value (a
drop of 3 dB) at the design frequency.
Look at the circuit shown in Figure 9.6. The 75 n coaxial transmission
line impedance is converted by the balun to the 300 n impedance of the
AC 5weep Type
IftC SweeplNoise ~l @:f Linear 5larl Frequency: 20MegHz
Options: 6 Logarithmic End Frequency: 180MegHz
EJ Monte CarlolWor.;l Case

~3 Total Points: /40Q _]
EJ Parametric Sweep NoiseAnaly sis

LJ Temperature (Sweep)
EJ Save Sias Point o Enabled Output 'folrage
[J Load Sias Pen I/'/ SOI.Hce:
Inrerval
oulpul File0 plions

L] Include detailedbias point informalion for nonlinear
controlled sources and semiconductors (.OP)
OK II Cancel II !wit II ~
Figure 9.7 - SIMULATION SETTINGS wind ow, AC Analysis.
o
1 2'"
··•
t
~ 52 336M.!""O)
«I7533M.14 1.40)
"V
12V
3dB BANOVIIOTH
IV
'V
",' +--~--~---'-~-~--~-~~-~--~-~--~-~~-~--"-!--~--~----I
2_z 3 ....% ~ettlz 5 tlHHz 6 _2 7Dtlfz lottHz 9tlHHz 11lDtltz 11 1lttHz 121lttMz 13 0HHz lII Dt11z 1StHH z 16_2 17 IHH z 11 ,""2
• U(31. U) . 1.IJ. 1_
rrfOqu Pncy
Figure 9.8 - AMS Simula tor window plott ing voltage across RL.
9-6 Chapter 9
load. The design frequency of the balun is 100 MHz, so transmission line T2
is Y2 wavelength long at 100 MHz. Figure 9.7 shows the simulation profile
to be used on this schematic design, an AC Analysis in which the frequency
sweeps linearly from 20 MHz to 180 MHz.
The PROBE display of the PSpice analysis output data (Figure 9.8)
shows the graph of the voltage magnitude across the load resistor, trace
V(30,40), to be a maximum of 20 Vat 100 MHz. Using the 0.707 criterion,
the cursors in PROBE show that the voltage falls to 0.707 x 20 V, or
14.14 V, at approximately 47 .6 MHz and 152.4 MHz.
Thus, PSpice has directly provided the information to determine the
power bandwidth to be about 152.4 MHz - 47.6 MHz, or 104.8 MHz.
The power bandwidth is not necessarily the same as the usable bandwidth,
since the voltage standing wave ratio (VSWR) may be acceptable only over
a much narrower bandwidth. The higher the VSWR, the more power is
reflected by the load back to the source. The next problem will show how
to make PSpice provide information that can be used to calculate VSWR
at each frequency.
A very simple modification can be made to a circuit to make PSpice
calculate the input impedance of a circuit. In this next example, we will
slightly change the circuit of the previous problem to allow PROBE to graph
the input impedance of the balun circuit at each frequency. From this input
impedance data, the VSWR at each frequency can easily be calculated, and
a VSWR-based bandwidth can be determined.
Balun Connected to a Voltage Source

If an ac current source of I A magnitude and 0° phase is connected to
the input of a circuit, the phasor voltage at the input is the product of current
and impedance, as we see below:
V= I x Z = 1.0 x Z = Z
Thus, by replacing the ac voltage source and 75 n resistor in the
previous problem with a 1 A current source, PSpice will generate input
impedance data directly. Refer to the modified schematic diagram in
Figure 9.9, which shows current source 11. Since the phase is not specified
in the 11 current source, the default value of 0° will apply.
Figure 9.10 shows the simulation parameters for this circuit. A linear
AC Sweep will occur from 60 MHz to 140 MHz with a total of 400 data
points.
The PROBE output graph shown in Figure 9.11 has two plots that show
the complex input impedance in polar form - V(20), the magnitude of the
voltage at node 20, and P(V(20)), the phase of the voltage at node 20. These

are the magnitude and phase, respectively, of VIN.
The input impedance data, when converted into VSWR data, indicates
that the VSWR at 60 MHz and 140 MHz exceeds 3. The conversion method
can be found in many texts on elect ronic communications with a chapter on
transmission lines. While the data at 48 MH z and 152 MHz was done in this
analysis, the VSWR at those frequencies is 5.66. A VSWR that high would
be unacceptable for most applications.
NL = 1 NL = .5
ZO =75 ZO = 75
F = 100Meg F = 100Meg
~'
1Aa c
OAdc
r-:.
-
-=-0 300
Figure 9.9 - Transmission line balun circuit schematic with current source .
AC Sweep Type
IPC. Sweep!Noise ~I Linear Slarl Frequency: 60MegHz
Options : iE) Logarithmic End Frequency: 140MegHz
General SettIl1!lS Total Points: 400

EJ Monte CarloIWO<Sl Case
[CJ Pa<iOITlelric Sweep
NoiseAnalysis
[J T~ (Sweep)
C] Save Bias Pan EJ Enabled OutputVoltage:
tJ Load Bias Pan Ilv'SOI.JfCe
~~
Interval.
OutputFile 0 plions
[] Includedetailedbias point information for nonlinear
controlled sources and semiconductors (.0 P)
I Cancel I[ IWt II ~
Figure 9.10 - SIMULATION SETTINGS window, AC Analysis.
9-8 Chapter9
v
o
I l50V
··•
t
100'/
5OVL : -_ _~ _--====:=::::=-__--':' '=:::=:=::::=-- ~ ~ -l1

'_r·...:-V(lIl)
==------ - - - -- -- - - - -- -- - - - - - - - - - - - - -- - - -....,r
DESIGNFREQUENCY 100MEGHl
.. +----":O"":::::---------::=_~==-"__====_--==------------"""_<;;:---___! I
SEl»
- lI.. +-----.-----r--
----,----~,.__--- ~-- -~----_._----q
,-, .. ' ( U(ZI»
11 at11z , ...lHN z
Figure 9.11 - AMS Simulator window plotting both output voltage and phase angle.
Qu arter-Wavelength Transformer
One method of matching a load to a transmi tter is to use a 14 wavelength
sectio n of transmissio n line to transform the impedance at its load side to the
characterist ic impedance of the system . Refer to Figu re 9.12 .
The purpo se of T3 (a 50 n line) is to transfor m the very low resistance
of the load, S n, to 500 n at node 4. Transmission line T2 (not a 50 n line)
is 14 wavelength long and transform s the impedance of 500 n at node 4 to
50 n at node 3, thus crea ting a perfect match at the design frequency.
141.42VAC
NL
F
=2
=50Meg
~~ -=
- 0
NL
F
=.25
=50Meg
-=
- 0
NL
F
=.25
=50Me g
-=- 0
Figure 9.12 - auarter wavelength transformer circuit schematic .

Figure 9.13 details the simulation settings for this circuit and calls for
an AC Analysis. A linear AC Sweep will occur from 10 MHz to 90 MHz
with a total of 400 data point s. The results of the AC Analysis will be plotted
in the PSpice PROBE window shown in Figure 9.14.
AC 5weep Type
IJlC SweeplNoise @ Linear Start Frequency: 10Meg
Options: C) Logarithmic End Frequency: SOM eg
General Selti1gs [D~~ Talai Points: 400

ElMonte CarlolWor.;tCase
rJ Parametric Sweep Noise Analysis
[iJ Temperalure (Sweep)
EJ Save Bias Point El Enabled outpul \/ 0It,9ge: I I
[J load Bias Point ll\"-Source: [._~
Interval: I I
OutputFileOptions - ---- ---
[] Include detailed bias pointinformation for nonlinear
controlled sources and semiconductors (,OP)
OK II Cancel 1[ Ivt*f I[ ~
Figure 9.13 - SIMULATION SETTINGS window, AC Analysis.
• 2• .-----------------_,_~~--_,_----------------.....,
• (SS032fol)HID)
n BANDIMOTH
"
SEl;t'L_ _ -.:.::::=======- ...L ...L -=======:: : : :== -.J
J zsur·"::'
··:":(:u.,:
(s:.,:):...
) - - - - - - - - - - - - - -, -- - - - , -- -- - - - - - - - - - - - - - ---,
,
.
l
, .OU
I
e
""
...
S"l.
a U( 5)
, ....
, ,. . .:. . . . .:. .==:=;::====:::;::=~......:....
, ....
. . .:.....z
._._......:...~......:.........:...~......:...-:..l.
SlIll z ....
. . .:. .......:...~......:....
, . . .:. ..:.==:;:=====:===.
r ..., , ....
. . .:. ..:...z
.J
Frl'quftlcy
Figure 9.14 - AMS Simulator window plotting output voltage and dB with respect to frequency.
9-10 Chapter 9
The voltage magnitude across the load, V(5), is plotted two ways in
Figure 9.14. The lower plot is the magnitude of node 5 voltage, while the
upper plot shows 20 log (node 5 voltage). The decibel data in the upper
plot makes it easy to evaluate the half power, or -3 dB, bandwidth of this
matching circuit. Using the cursors in the PSpice window, the -3 dB points
have been indicated and designate the bandwidth.
The DB(V(5)) graph (upper plot) shows that load voltage is a maximum
of 27 dBV at the design frequency of 50 MHz and falls off on either side.
The 3 dB bandwidth is the range of frequencies over which the magnitude is
within 3 dB of27 dBY. The cursors in PROBE easily show that the bandwidth
is from approximately 45 MHz to 55 MHz, a 10 MHz range.
Time-Domain Reflectometer
An excellent way to understand how pulses behave on transmission
lines is to use a time-domain reflectometer (TDR), which sends a train
of voltage steps into the sending end of a transmission line and displays
the reflections when they arrive back at the sending end. By observing the
sending-end voltage, with a knowledge of voltage reflection coefficients,
you can quickly determine both the length of the transmission line and the
nature of the load impedance. A similar process is used by bats (in air) and
by porpoises (in water); it is called SONAR.
Ord inarily, the TDR is matched to the transmission line (that is, a 50 n
TDR is used on 50 n lines). This is desirable because the reflected pulses
arrive at the sending end, are absorbed by the generator impedance, and do
not get reflected back toward the load again . An excellent way to realize how
little you really know about pulses on transmission lines is to use a TDR
that is not matched to the line. In practice this is avoided, as the backward-
traveling pulse reflected from the load and forward-traveling pulse reflected
l - - - - - ,4
V1 =QV
V2=2V
=
TD 1n RLOAD
TR = 1p 1E-6
TF= 1p
PW=.1n
-=-0
Figure 9.15 - Transmission line schematic with VPULSE input.
Transmission Lines 9·11

from the generator coincide at the input and make interpretation of the
display quite difficult.
Thi s last example illu strates a pulsed TDR, with a 200 n output
imped ance , connected to a 50 n line. As if that' s not bad enough, the load
on the line is a short circuit. When the voltage at the input is observed,
confu sion reigns. In order to make what is happening understandable, we
can use PSpi ce to peek at the voltage in the middle of the transmission line.
Figure 9.15 shows the pulse generator with 200 n output impedance
connected to two 50 n transmi ssion lines in series. The characteristics of the
input pulse are defined in the schematic design. The pulse voltage source,
VIN, will start at 0 V and rise to 2 V after a 1 ns delay. The rise time and
fall time will both occur in I ps. The width of the pulse will be 0.1 ns. Each
line has a time delay of 0.25 ns, so the total one-way transmission time is
0.5 ns. Using two lines in series allows us to view the voltage at the midpoint ,
where the forward -traveling and reverse -traveling pulse s do not coincide.
In the schematic design, the load resistor is listed with a lE-6 n value
(0.000001 n), as PSpice does not allow 0 n resistors.
In order to observe the reflection of the input pulse, a Transient Analysis
will be carried out on the schematic design with a run time starting at 0 ns
Analysis type:
Run to time: 5.5n : seconds (T5TOP)
[TITle Oomail(Tr.meri) ... 1
5tart saving data after: 0 ; seconds
Options :
Transient options
'J - ...
EJ Monte CarioIWOfSI Case Maximum step size: 5.5u . seconds
EJ Parametric Sweep
[E] T~ure (Sweep) EJ 5kip the initial transient bias point calculation (5KIPBP)
[J Save Bias Point
lEI Load Bias Pori Ii] Run in resume mode [ Output F~e Options... I
EJ Save Oleck Points
EJ Restart 5mJI ation
Cancel II ~ ][ ~
Figure 9.16- SIMU LATION SETTINGS window,Transient Analysis.
9-12 Chapter 9
.. t-----~ ~ __;F+R
r _- - -- _: !- -;F+Rr - --'
F+R
-5'''''' .
• U(Z)
..+ - -- -- - - - ;
SU »
- Sl.... +---..,.--- -..,.----r-----r----r---..,.....--..,.....- -...,---~ -- ~ - - _ l
Is ' . Sns 1 . ... '1 1 . Snfi l .lns 2 . Sns 3 . ln s S .lns $ . S"S
0 "'(:' )
rio.
Figure 9.17 - AMS Simulator window plotting voltage from both node 2 and node 3 (F, R, and F+R labels have been
added to indicate direc ti on of pulse).
to 5.5 ns with a step size of 5.5 us to provide an adequate resolution to the

output plot in the PSpice PROBE window. Simulation parameters are shown
in Figure 9.16.
The PROBE display of analysis result s seen Figure 9.17 shows the
voltage at the generator, V(2), on the upper plot and the midpoint voltage,
V(3), on the lower plot. Label s have been added in the PSpice plot s to mark
each pulse with its direction of propagation - F (forward) or R (reverse).
On the upper plot, the first pulse, of 400 mV, is seen at I ns. The 400 mV is
easily explained as the voltage division of the 2 V generator pulse between
the 200 n generator resistance and the 50 n line impedance. However, at
2 ns a pulse is seen, whose amplitude of -640 mV may not be so obviou s;
this is the sum of the -400 mV pulse reflected back from the load and the
-240 mV pulse reflected back towards the load by the generator.
The voltage reflection coeffic ient of the load is -1.0, while the generator
has a voltage reflection coefficient of +0.6. Observing the lower plot of the
voltage at the transmission line midpoint, you can see much more clearly
what is happening. Every time a forward-traveling pulse (labeled F) is
reflected at the load , it comes back with the oppos ite polarity, multiplied
by -I ; every time a reverse -traveling pulse (labeled R) is reflected at the
generator, it comes back with the same polarity, but multiplied by +0 .6.
PSpice has been used here to give insight into the behavior of a
transmission line circuit, which would be difficult to glean in the laboratory.

In Summation
As you can see, PSpice is an excellent tool in the sense that it can
simulate and solve transmission line problems in a matter of seconds, whereas
carrying out manual calculations can be tedious and time consuming. But it
is important to note that PSpice recognizes only a lossless transmission line.
To compensate for this, if you wish to simulate a more realistic example, it
is possible to add distributed losses to a transmission line by breaking the
transmission line into a number of short lengths and inserting resistances
in series .
9-14 Chapter 9
Chapter 10
Subcircuits
Many circuits are made with basic electronic building blocks, such as
operational amplifiers (op-amps), logic gates and comparators. For example,
an active filter might contain six identical op-amps . One way to create an
input schematic for such an active filter to be analyzed using the PSpice
software would be to place the op-amp six times in the schematic capture
window. In additi on, resistors and capacitors certainly will be attached
to those op-amp s. This appro ach can be tedious and monotonous work ,
especially when you begin to work with larger and more complex schematic
designs. Fortun ately, PSpic e permit s us to define an often-used or redundant
circuit block in a single new comp onent model. This circuit block can then
be used many times, like a part, each time the circuit block is used in a
schematic design. PSpi ce calls such circuit blocks subcircuits.
Linear Dependent Sources

This chapter will demon strate how to create a subcircuit using the PSpic e
software. We will also take this opportunity to introduce linear dependent
source components. PSpice lets you use dependent (or controlled) voltage
sources and current sources in describing circuits. This can be helpful in
making simple models of semiconductor devices, such as BJTs, PETs, and
op-amps.
The four kinds of linear dependent sources are shown in Table 10.1.
Table 1 0 . 1 - - - - - - - - - - - - - - - - - - - - -
Linear Dependent Sources
Linear Dependent Source Abbreviation PSpice Component
Name (see Figure 10.1)
Voltage-controlled voltage source VCVS E
Current-controlled current source CCCS F
Voltage-controlled current source VCCS G
Current-controlled voltage source CCVS H
Subcircuits 10·1
E1 F1 G1 H1
~ ~~ ~ ~
E GAIN = 1 F GAIN = 1 G GAIN = 1 H GAIN =1
Figure 10.1 - Linear dependent source schematic symbols (see Table 10.1).
The schematic symbols for each of the four linear dependent sources are
shown in Figure 10.1. Each of these source components consists of four
terminals . Two terminal s are sensory terminals that detect an input voltage,
in the case of the VCVS or VCCS (volta ge-controlled voltage source or
voltage-controlled current source), or input current in the case of the CCCS
or CCVS (current-controlled current source or current-controlled voltage
source) . The input to the sensor terminals, in conjunction with a user-defined
gain constan t, will determine how much voltage or current will be present
at the output terminal s of the linear dependent source .
Using component E, the voltage-controlled voltage source, a circuit
will be constructed in the Cadenc e Allegro Design Entry/OrCAD Capture
schematic capture window to show how to create a subcircuit using the
OrCAD /PSpice software. After the subcircuit has been created, it will be
demonstrated that a VCVS exhibits similar behavior to a typical op-amp, in
the sense that it is possible for a user to create a certain amount of voltage
gain that can be seen between an input and output voltage.
Creating a Subcircuit Block

First, let's reduce this basic schematic design into a subcircuit block
(see Figure 10.2). In Figure 10.2 the VCVS component has been placed in
the OrCAD drawing space . The VCVS, as with any of the linear dependent
sources, features the sensor terminals on the left of the schematic component
Out
-=-0
Figure 10.2 - VCVS schematic design to simulate op-amp.
10-2 Chapter 10
and the output voltage or current to be present within the terminal s to the
right ofthe component. Thus, our input pins (which we will talk about injust
a moment) have been attached to these. Also, note the presence of R1. This
large I MQ resistance between the input terminals is characteristic of the
enormous input impedance of a typic al op-amp . A linear dependent source
exhibits almost ideal behavior, so R1 is there only to help mimic the input
termin als of an op-amp model. To the right of the terminals, the negative
output has been grounded, and the output has been designated at the positive
output pin of the VCVS component. With the negative pin grounded , all
the potential developed between the output pins will be seen at the positive
terminal/output pin, and again, will simulate a singular outpu t of an op-amp.
To summarize, the input pins (designated + and - ) at the left of the
schematic are similar to the input pins of an op-amp. An input poten tial
attached to these pins will be sensed and acted upon by the VCVS component
and produce an output based on a given value of gain. In the case of this
sample circuit, the gain has been specified as 50,000.
Now, to place and designate the input and output pins of a subcircuit,
select the button in the right toolbar titled PLACE PORT. You will be
presented with the window shown in Figure 10.3 . Scroll through the
Place Hierarc hical Po
Symbol
OK
PORT LEFT -L
Cancel
POR TBO TH -R /C,/l,PSYtv' ""
Add Librar}'...
PORTLEFT -L/ Design CcD ~P O RTl£ FT-L
PORTLEFT-R/ C,/l,PSYM [ Remove Libra!}' 1
PORTNO-L/C,/l,PSYM
Help
Libraries:
Name:
PO RTLEFT -L
o NetG roup Port ~I

lEJ ShowUnNamed NelGroup
Figure 10.3 - PLACE HIERARCHICAL PORT window.
Subcircuits 10-3
available ports and find ports PORTLEFT- L and PORTRIGHT-R . Placing the
port called PORTLE FT-L will create a terminal that will appear on the left
of the subcircuit block that you will create, and placing PORTRIGHT-R will
create a terminal that will appear on the right of your subcircuit block. Two
PORTLEFT-L pins have been placed on the input side of the design and have
been named simply + and - . The terminal - denotes the port that connects
directly to the negative sensory terminal of the VCVS, and the terminal +
connects directly to the positive sensory termi nal of the VCVS. The output
terminal of the VCVS component connects directly to a PORTRIGHT-R port
and has been named OUT . Thus a single output pin will appear on the soon -
to-be-created subc ircuit block named OUT .
Now we turn to the first step in creating the subc ircuit block based
on this design . After drawing the schematic to be reduced into subcirc uit
form , save the design and select the CREATE NETLIST option found in the
PSPICE menu, as shown in Figure 10.4. This will present you with a CREATE
NETLIST window. Click the PSPICE tab at the top of the window so that
the CREATE NETLI ST window looks similar to Figure 10.5. If this CREATE
NETLIST window does not open, you may need to use anot her metho d of
creating the netIist. There are subtle differences between some of the most
recent versions of the software, and whether or not you experience this
problem of not being able to open the CREATE NETLIST window depends on
1· .. . r . .. · 6 · .. . L ' . 1..' . . . • . . 9 . . L L.· . -1) .
(3 .30. 1.&1)
The fOlOft'lg 2 polflts have ~ tdentifJed as net conned Wit y (!'lange poIlts from the tast opera tion
(3 30 . 1.20)
(3.30 . 1 80)
CtUt~ , PSpc., Meld: 101IN- Kti\~ srmuIMtoot> pt"Cfk.
I
Figure 10.4 - Creatin g netli st of schemati c design .
10-4 Chapter 10
~ Creeee Netfist ,~ ~
PCB fdlor I EDIF 2 00 I INF I t.ayou I PSpice I SPICE I VOliog I VHOl I 001er !
Option:!
D u.ate ~ Format Nell:;t ISeImgs-1
~ Oeee SubGrt:ut Format NetI,.
.ji) Descend
Use TenJllote:
ate
:::J ii; X 1"
•
IPSpiceTenJll
1._~ DoUct Descend :_------------------- ---- ----_:
I
: {i] Place DRClMlk.,. for Eitm and W~
0 ~ Mode(1 62 and PriorReIeeseej
NetI,. Re : ~ \-Iew Ot.tpli
C:\S<bc:iro..ot\S<bc:iro..ot·PSpiceFles\SCHEMATIC1'.OphT1lSlbciro.Jit.L1B I &-owse ... I
I OK II ~ II ~ I
Figure 10.5 - CREATE NETLIST window.
the version of the OrCAD/PSpice software you are using. Another proce ss
that surely will work for creating the netlist is to select the project tab in the
OrCAD window. This will display the project folder and all associated files
in a hierarchal format. Select the schematic page that contains this design by
clicking on it, and then select the CR EAT E NETLIST button from the toolbar
at the top of the screen . For more information regarding this method, refer
to Chapter 3.
Once the CREATE NETLIST window has been opened and the PSPICE
tab has been selected, check the box to create a subc ircuit format netlist
with the DESCEND bubble chosen. This means that a netlist will be created
that describes the schematic to be contained within the subcircuit. The
fact that this subcircuit descends means that once the subcircuit has been
implemented in a new design, the subcircuit netlist will lie on a hierarchical
tier below the top schematic page of the design . The text box at the bottom
of the window designates the destination and the file name for the netlist
of the subcircuit block . The VIEW OUTPUT box has been checked in this
window, so after pressing OK, the completed subcircuit netlist file will be
opened in a new window.
Subcircuits 10-5
I!d Ope n l ibrary - ~
~ - - - -- - -_. ---
Lookin. SCHEMATIC 1
... -.:
Recent Places
Name i Date mod ified
~-Op-a-m-pS-ub-ci-rcu-it.-U-B-----~ 8113/20138:36AM
Type
PSpice M,
Desktop
l ibraries
Com puter
Nrlworl: ,1
1-_ -==== ========:::::'-
Re name:
III
I SDT ~Jb)
Figure 10.6 - Netlist for VCVS design.
Figure 10.6 show s that the netlist for the subcircuit block based on the
schematic design created earlier in the chapter has been saved under the file
name "OpampSubcircuit" .
Introduction to Model Editor

Open the Model Editor program included with the DrCAD/PSpice
software. Select OPEN in the FILE menu and find the netli st file for the
subcircuit block you created (see Figure 10.7). The file extension for the
netlist that you have created is .lib. This denotes a Model Editor library file.
Open the netlist and the MO DEL EDITOR window will resemble what is
shown in Figure 10.8 . You will see the same netli st text file that was shown
in the DrCAD window after you generated the netlist earlier. The name of
the subcircuit block will be SC HE MATIC 1. This is designated in the column
at the left side of the screen .
Under the FILE dropdown menu, select the option EXPORT TO CAPTURE
PART LIBRAR Y to open the window shown in Figure 10.9. This will create the
schematic symbol for the subcircuit block that will appear in the PSpice library.
The top text box is the destination for the library file that was just opened; the
bottom test box designate s the library name that will contain this subcircuit
block SCHEMATIC 1. This file extension is .olb, which stands for DrCAD
library. The DrCAD library name chosen for this example is OpampSubcircuit.
10-6 Chapter 10
eaeeace _ '" 1<1
so"r~
. :! " BCn"
E El
lO.-ll.l
.Ur03
.. ~:;),~ ): ll.<;::IT
:! ~..tI'..JJ f Cl "
oarO .. -$:lk
- O\o~
;
.. ~ '7 '
l-g:Z:·Si~;;~:*~~~:-----· 1
,~,. .•, ~
~.-: t-{ .:W~
(;iJ~U
_ _, t";;'Ci ,.... .
, ~
:IID
-~
,
::'~"
,- ~
.... S.-""POll
.
' r
i _-Il ~ . ..
.
..
I
1.""'-'1
Figure 10.7 - Opening the Model Editor library file.
SCHEMATI Cl + - Out
OUT 0 + - SOl<
Model Name Type Modified Date/Time
+ - !MEG TC= O, O
SCHEMATICl SUBCKT
Zoom in about center of plot NUM
Figure 10.8 - MODE L EDITOR window displaying imported VCVS design netlist.
Subcircuits 10-7
Create Parts for l ibrary
Enter Input Model Library:
• .1l;JjjM1.1il:IU'!4I1.U.1.IW IlO111.i4ii;ijil. 41:!J [ Browse... I

Enter Output Part Library:
:u it-PSpiceFiles\ SCH EMATIC1\0 pampSubcircuit.olb Browse... I
[ OK ] I Cancel I ['--'--"'-~'---'
Help
Figure 10.9 - CREATE PARTS FOR LIB RARY wi ndow.
Name: Date modifi ed Type

~...? ~ OPAMPSUB CIRC UlT.Ol B 6/6 / 20129:44 PM OLBFile
Recent Places
Desktop
Libraries
Computer
, ~ III
Network
Fieran< : I -::J ~
Filesdl)pe: § l.iJr"'Yf"'lll) ~I Cancel
Figure 10.10 - Li brary containing new VCVS subci rcuit.
Crea te a new project and open a blank schematic page in the OrCAD
schematic capture window. Next, add a new library in the PLACE PART
toolbar by clicking the ADD LIBRARY button pre viou sly mentioned in
Chapte r 2. Browse and find the name of the OrCAD library that was ju st
create d using the Model Ed itor program. In this case the library name chosen
is OpampS ubcirc uit.olb (see Figure 10.10). Open this library.
This library now is active in the schematic window along with an of
the other components that you have been using up to this point. There is
10-8 Chapter 10
only one component in this library, and it is shown in Figure 10.11.
=9~1 OUTf- lt is the subcircuit block SCHEMATICl, and it features three pins
that correspond with the ports placed in the schematic design in the
SCHEMAllC1 beginning of the chapter.
Figure 10.11 - Schematic

symbol for VCVS subcircuit. Schematic Design Incorporating the
Subcircuit Block
Figure 10.12 shows a schematic that was drawn utilizing this new
subcircuit model. A 100 ~ V, 1 kHz sinusoidal input has been applied to the
positive terminal of the reduced VCVS circuit while the negative terminal
has been grounded. A 1 kQ load resistor has been attached to the output
U1
VOFF =OV RlOAD

VAMPl = 100uV 1k
FREQ= 1kHz
AC =OV
Figure 10.12 - Schematic design featuring VCVS subcircuit.
Figure 10.13 - SIMULATION Simulation Settings - Trans

SETTINGS window, configuring
the subcircuit library.
lbaI)' Path
OK 11 Ca-1C<l I[ PWt II ~
Subcircuits 10-9
U 6 ._
....
2 .1lrII .
..
- 2.•
-'. IU
-•.IU Is+---~--~---~--~--~---~--~--~---~---;
1 . 1M 1 .2M 1. 61tS ' . 7M I .'M 1.'1115 1. ....
• U( 11O.D :2 )
e,-
TI ..
Figure 10.14 - AMS Simulator window plotting the load voltage with respect to time .
terminal. Recall that the VCVS component within this subcircuit has a gain
of 50,000, so it is expec ted that we will see an output of 5 V after simulating
this circuit.
Before simulating, it is essential to configure the new library. In the
SIMU LATION SETTINGS window, select the CONFIGURATION FILES tab.
Click LIBRARY and then browse to find the OpampSubcircuit.olb file (see
Figure 10.13). Click ADD TO DESIGN and apply the se changes after
opening the library file. This action allow s the PSpi ce software to attach the
underlying netlist data for the SCHEMATIC I component to the simulation
profile. Even though the subcircuit block is visible in the schematic design,
the netlist data is not associated with the schematic from a simulation
standpoint. If the user neglects to configure the library for the subcircuit
component, a simulation will yield errors. Most likely, the PSpice software
will inform the user that the component is undefined and that all of the
attached traces and components are floating.
A Transient Analysis was carried out on this circuit with a start time of
Os and an end time of 1 ms with a step size of 1 its. As predicted, the output
voltage measures exactly 5 V (see Figure 10.14).
In Summation
Being able to create a subcircuit can significantly reduce the complexity
of a design and can be especially helpful in an instance where a circuit might
feature redundant branches or networks. These subcircuits can be utilized
to simplify some of the sample circuits in the next chapter.
10-10 Chapter 10
Chapter 11
Sample Circuits
This chapter is devoted entirely to sample circuits. Analysis will be

carried out on various examples to effectively put into practice all the
concepts discussed in previous chapters. The early examples of this chapter
will carry out Bias Point Calculations on de circuits. This will be followed
by examples using sweepable dc parameters, then ac parameters, and finally,
examples using the Transient Analysis.
These examples were designed with the intention of expanding further
on the topics that were previously discussed and may delve even a little
deeper into some of the more advanced functions of the Cadence software.
Bias Point Examples

Figure 11.1 shows a dc circuit with one battery and nine resistors. The
problem is to find the de voltage across RG, the 600 n resistor. As done in
previous chapters, we will draw the schematic design and perform a small
signal analysis, which will cause the voltage at each node and the voltage
source current to be printed in the output file.
The outputs in Figures 11.2, 11.3 , and 11.4 contain the Small
Sign al Bias Solution calculations, giving measurements of voltage
RA RD RF
2k 4k 500
-;,J-
300 •
RI
200
7"0
Figure 11.3 - Bias Point results showing only currents.
RC RE
3 ~ M*M
l~
400
RA RD RG
....&IE
2
RB
5
300 200
Figure 11.4 - Bias Point results showing only wattages.
11-2 Chapter 11
with respect to ground, current and power, respectively. Since we want
to find the voltage across resistor RG, it will be necessary to subtract
manually the voltage at node 5 from the voltage at node 4, as follows:
V RG = V(4) - V(5) = 1.4474 - 0.8977 = 0.5497 V
While it is not necessary for this problem, the Small Signal Bias
Solution will also yield the branch currents, and the power dissipated within
each component is displayed in the outputs shown Figures 11.3 and 11.4.
The de circuit in Figure 11.5 contains a voltage source, a current source,
and three resistors. The voltage across the 40 Q resistor (R2) and the current
through the 30 Q resistor (R1) will be determined. Similar to the previous
example, these values can be found using the Small Signal Bias Solution.
Figure 11.6 displays the voltage at each node of the circuit with respect
to ground. The voltage measured from node 4 of the circuit is the voltage
drop across the 40 Q resistor. Referring to the output from Figure 11.6, this
potential is measured at -5.143 V de.
11
R1
r- ~'
2 4
30
500mA
6V
-T R2
40
R3
20
1
-=:1-
-=-0
Figure 11.5- A dc circuit with a voltagesource and a current source.
11
R1
2 4
30
500mA
V
6V
-T R2
40
R3
20
-=-0
Figure11.6- Bias Point results showing only voltages.
Sample Circuits 11-3

Notice in Figure 11.7 that the current values have been toggled visible
in the Cadence Allegro Design Entry/OrCAD Capture window. The current
has been measured in the branch connecting node 2 to node 4 as 371.4 rnA.
The next example will carry out a Bias Point Calculation for a circuit
featuring one of the linear dependent sources alluded to in Chapter 10.
The schematic diagram in Figure 11.8 is a de circuit with a linear voltage-
controlled current source, called G. The current through the voltage-
controlled current source G is equal to five times VRA' the voltage across
the 15 n resistor. The problem is to find the voltage across the 6 n resistor
(RD) and the current through the 25 n resistor (RB). In order to easily find
the voltage across the 6 n resistor, ground (node 0) has been placed at its
bottom terminal.
The input schematic drawing shown in Figure 11.8 is simulated
11
R1
2 4
30
v
6V
R2 R3
40 20
Figure 11.7 - Bias Point results showing only currents.
G1 2
~ RA I
15 I < RC
~ 25
1 I 3
> RB
GAIN =5 ;,. 25
RD
<
-- - 6
8V
~TV1 V2
4
JIt--4
12V -'--
-=- 0
Figure 11.8 - VCCS dc circuit schematic .
11-4 Chapter 11
using the Small Signal Bias Solution. With reference to the discussion in
Chapter 4, just as was seen in that first sample circuit, here the circuit
voltages, currents, and wattages can be toggled on and off in the schematic
capture window after the Small Signal Bias Solution is complete.
Figure 11.9 displays all the node voltages in the circuit. According to the
simulation results, the voltage drop across resistor RD is equal to 1.891 V.
Another element of the problem statement was to find the current
across the resistor RB. The circuit currents are displayed in Figure 11.10.
The Small Signal Bias Solution results indicate that the current across RB,
the 25 n resistor, is 318.2 rnA.
Figure 11.9 - Bias

Point results showing
only voltages.
RC
25
RB
25
RD
6
8V
TV1
-=-0
Figure 11.10 - Bias

point results showing
only currents.
RC
25
RB
25
RD
6
8V
T V1
4
Sample Circuits 11·5

DC Sweep Examples
Figure 11.11 illustrates a test circuit that can generate a volt-ampere
curve for a diode. This is a similar method , used previously in Chapter
7, except we will take the simulation further to illustrate other important
characteristics of the diode in question. Again, we will be using the IN4002
diode. A current measurement marker has been placed into the schematic
design to measure the current across the diode as the source voltage, VD,
sweeps.
The SIMULATION SETTINGS window is shown in Figure 11.12. The
diode voltage is stepped from 0.6 V to 0.81 V in increments of 2 mV.
10 20
D1N4002
VD
-T
840mV
-=- 0
Figure 11.11 - Diode test circ uit schematic.
Sweep variable
I~} Voltage source Name: VD
OJ:t;ons:
e> Current source
e Global parameter btodettcpe r ·1
~ .. C) Modelparameter Model nerne I -.J
EJ Seccodev Sweep C~
o Morte CarIolWoost Case ~ Temperature Peremeter name.
o Pa<amelric Sweep Sweep type

D TefTl'<'ill.... (Sweep)
EJ Save 80s Pan (l!' Linear Start value: 600mV
EJ Load 80s Pan _ . . r - - -'- l End value: 840mV
tl Loqerithrnic ~c_~d:'__~ J
Increment: 2mV
o Value list <-C _
OK II CMC<i I l~ FwIY 11 ~
Figure 11.12 - SIMULATION SETIINGS window, DC Sweep.
11·6 Chapter 11
Figure 11.13 shows the diode volt-amp characteristic s. Using the
cursor in PROBE , at 600 mV the diode current is 1.763 rnA, while at 810 mV
the current has risen to 163.763 rnA. If the Y axis is made logarithmic rather
than linear, a straight line graph results due to the relationship bet ween
voltage and current in a diode. Remember that the PSpice software has
ability to display a trace that plots a mathematical expression. This functi on
is used to the graph the diode 's static resistance , VD/ID, in Figure 11.14, and
e 20 ....
I j..j.::.~.:~.: j.j.'.:~.;'~.: ::rrr .

···········, ···
...~ .."; ...~...
: : Er:F::E·E.F
c . . ."JJ·:·F
.
~ 151M +--i-:--Cc---!-";'-+--+--+--:---i--i-t-:--C'-i- t-+--+--:--f--i--:--:-H--,.-+-+-+-...,--:-+--i--i-rl--,.-:--,...-+...,--:--i-t--:-",L-J
y
n
t
--+.+.+.....+.+..... ~
:::f:::f:::j::: :::[:::1:::1:::
"'r"T"r-' ··'to ··r·ot"
.... . . ... ..... "... 12...
""'" " ... " ... ...... .....
ea...
Figure 11.13 - AMS Simulator window, plot of D1N4002 transfer curve.
S Jill, :
!,..'t:LI..,...,...,.. 1:::~. .:: 1 """":I:rT:.·:::r:: . . ....< .. ~::: : -:: : rr: : : ::: :j.::FI.: ..:
.
f ' :••+ ..;....:.. ..,.. + : > t I: :i·: :t::!~~~ ~;· ·j ,·.. ! :· · f·..,··+- ..,.. + ··,..··: ,..·, : '..·'.. ·I· ..·,..··, 1:::{.:::: :r:
.l±l· it"' jj
", ±", <
t··'LU
"",,:rt ::r::j:±
:;::[:J :::;:::iJ=
:: 1·:: Lt
:::; :tt;::T:1JjjII::tt±±~~~~
6 0BnIJ
.."""
62(11,0
e V(IJ D: -)I I ( O)
610nU l Don U
""'" .... .
nenu lI OnU . .Gnu
Figure 11.14 - AMS Simulator window plotting the static resistance of the diode .

D OD
.
Y
"
"I
., ,, ,..,.. :~r ·LL : ::T:r::j::~~T:Y~L
. . . -_. -- --
. ..
.................... . . . ... . . .
. . , " . . , . . , : ". .. :
..- ..- ..- 10""11

" ....
UD
Figure 11.15 - AMS Simu lator window plotting the dynam ic resistance of the diode.
VDD
J
~".v RD
10k
10V
VDD
-
9
~VDD
OV. I V-BA
-T-T-E-R--'~'--J-2N4395-
~ AREA =8
o
Figure 11.16 - N-Channel JFET test circuit schematic.
11-8 Chapter 11
the diode 's dynamic resistance , d(VD)/d(ID) , in Figure 11.15. It is interesting
to note that at 640 mV, the static resistance is approximately 173 .0, while
the dynamic resistance is much lower, 14 .o.
Before moving into some real circuits with practical applications, we
will carry out the same proces s used for the 1N4002 diode using a JFET.
The proce ss will look very similar to example s carried out in Chapter 8,
except we will use other simulation and trace technique s to explore other
characteri stics of the transistor. The test circuit of Figure 11.16 uses an
N-channel JFET, J 1. A graph of drain voltage versus gate-source voltage
is desired. The gate-source voltage, VBATIERY, is stepped from -2.5 V to
0.5 V in steps of 20 mV.
Before creating a simulation profile and carrying out a simulation, we
will use the Property Editor to modify the physical characteristics of the
JFET. Double -click on the JFET to open the PROPERTY EDITOR window
(see Figure 11.17) . Under the AREA column, change the numerical value
to "8" . However, the element line for the JFET contains an area factor of
8. This means that the physical area of JFET Jl is 8 times larger than the
default JFET, and several of the JFET parameters will be affected.
The voltage source, VBATIERY, swee ps from - 2.5 V to 0.5 V in
increments of 0.2 V. For this particular simulation profile, VBATIERY is the
only component with parameters that will be swept. Sweeping the value
of this single source will yield a transfer cur ve for the transistor in the
PSpi ce OUTPUT PLOT window. The simulation parameters are defined in
the SIMULATION SETIINGS window as shown in Figure 11.18.
Figure 11.19 is a graph of drain voltag e, V(3), versus gate-source
voltage, VBATIERY. The drain voltage begin s to drop when VBATTERY
OreAD Capture as - lite - [pro Edit .

~~
------------~--- ~
~ File Design Edit Vif!Nol Too ls
o
SlNtPage JrEmDCSWEEPS..• ][~ PAGEl r SOtEHATL. 1
INew Propelty...JI Apply I IOisplay...] I Oelele Property] I Pivot I Filter by: I< Culfent properties >
AREA Colo r CO MPONENT Desig

+ SCHEI.1ATIC1 : PAGEl 8 Detaul
Figure 11.17 - Property Editor for JFET model.

h1a!ysis type: Sweepvariable
!OCSweep ·1 @ Voltage source
(f) Current source
Name: V8ATTERY
Options: Mod.I 'ype

(iJ Global parameter
~ . h10del name:
B Model parameter
ElSeconda<y Sweep
E] Morte CarioIWorslCase
iD Temperature Peremeternama:
E] Paramelric Sweep
EJ T~ (Sweep) Sweep type
ClSave Bias Poirt (~:J Linear
Start value: ·2.'SI
E] lo ad Bias POOl
End value: .'SI
e Logarithmic ~~
Increment .02\1
6 Valuefist I;
OK
Figure 11.18 - SIMULATIO N SETTINGS window, DC Sweep parameters.
u , au
o
.1
t
l· :~L[8r ~ir~h~ ~~:¢~:~ '.: , .:~',

: I U+-+-+-+-+--+--+--+-+ --+---+---+--+t+- r-r--+---+---+---+----j-;--;--;-f-r -t -t -t -+-+--+--+-+--+--+--+-+ --+---+---+-- +- r--+- r--+---+---+---+----j
.' ::. :. :,.': :.:.:.;.'::,:.:..' :. '. ' :. ... " '. ' ... i:.... , . ':,:. -:: : : : : ..
I...c....:.. ·:,.. .
. . ~
...: ~---~ ~ ~. -_.:. -- ~_. - -~ --': '-:- .--:-_.: .

·· ·f· · · ~- - · _~· · _ - "' 1---~- - - -~- - -- " '~"' i" ": _· · ~-- --r - : .. .. _ · _ -~---- 1--- !- -
~-_._~ _- ~ _
- 1. au -1.6U - 1 .2 U -LOU - 1• • tI - 1. 2U -.... . ' .2U
Figure 11.19 - AMS Simulator window plotting JFET transfer cur ve.
11-10 Chapter 11
reaches - 2 V, and the JFET is saturated whe n VBATIERY is above - 1.3 V.
The PROBE cursor could be used to get exact num erical data, if need ed.
Figure 11.20 is a schematic diagram of a transistor-transistor logic
(TTL) 7404 inverter. The output is connected to a 2 kQ pull -up resi stor. In
order to determine the tran sfer charac teri stic of this circuit, a de source, VIN,
will be swept. The range of the input voltage sweep will cause changes in the
output voltage characteristic of a logical 1 changing to a logical 0 at room
temperature. The sweep parameters will be discu ssed below.
To simulate the change in logic level from 1 to 0, the de voltage source
will be swept from 1.10 V to 1.60 V. In order to provide a high -resolution
output plot, the DC Sweep will occur in I mV incremental steps . These
simulation parameters have been outlined in Figure 11.21.
The graph of Figure 11.22 shows that the output voltage stay s at
nearly 5 V until the input voltage increases to about 1.28 V. As the input
voltage rises from 1.28 V to 1.38 V, the output monotonically decreases.
For input voltages above 1.38 V, the output is less than 30 mV, indicating
that transi stor Q4 is well into saturation.
One note of caution: In a circuit that is bi-stabl e or has hysteresis, such
as a Schmitt trigger (a TTL 7414 IC is one example) , the use of de analysis
can be problematic. In the de analysis, previous circuit values are not taken
VCC
4 j
RCQ3
130
RCQ2
-tl8J2
1.6K
RBOl
4k N2222
RPULLUP
5 2k
'\ 01
2 0 1N4148
1
05
3
~ Q2N2222 9
Vcc
Q2N2222
~ 04 9
~Vl
VIN
OV -...=-
-T REQ2
Q2N2222 5V -
lk 0 'T
I - -
-
7'
o
Figure 11.20 - TTL inverter schematic.

into consideration when calculating circuit co nditions for the next input
voltage. Since there are two possible stab le outp ut voltages for a given input
voltage (depending on whether the input voltage is rising or falling), PSpice
may fail to converge or may give incorrect results . A better way to analyze a
bi-stable circuit is to use a piecewise linear (PWL) source with a triangular
shape and perform a Tran sient Anal ysis. When a Transient Analysis is done,
PSpi ce does "remember" the previous circuit conditions when calculating at
the next time increment. Sample circuits will be used later in this chapter to
illustrate the usage and application of a piecewise linear source.
. _ x_
- - - -
hlaIysi. type : Sweep variable - - _._. _.

(~I Voltage source Narne: VIN
CJ Currentsource Mode!typer
e:J Global parameter
EJ Secoodar:y Sweep
o Model parameter Model name
EJ Merle CarioIWoot Case e Temperature Parameter name L.- ...J
['] Parametric Sweep

EJ T~(Sweep) Sweep type
IE]Save Bes Port Startvalue: 1.10'1
C!) Linear
EJ Load Bas Port ~ I End value: 1.60'1
e Logarithmic [ Decade
Increment: .OOW
6 Value i ,t
OK II Canc:eI II !Wf II HetJ
Figure 11.21 - SIMULATION SETIINGS window, DCSweep parameters.
0" ; ; : : : ; : : ; ; : ; ; ; ; : ; ; ; ; ; ; ; :
u
··_( -( -t ·( - .. _ . .".. ..- ...•...•........... .....-_ ....... ,----..... ...•...•...•...•... ..., ...,...,....... .
...•...•...,...•... ...•...•...,...•...
::Fj:::FF
~. _ .~ - _ . -.- _
p
t
... ..... ...... -.....- -_................. ...........•...•.... ... ..........., ... :::i:::t::j:::1:::.
···r··-.···,···.··-
~
~ ~
U ...•.......•....... ... ... .......... ... _ ................. _. .. ................... ...........•...•... .......•...•....... ...........•...•... ...... ............. ...................
t
~ . OU
:::;:::;::T::;::: ... ... ...+..+... "';"'["'1" ';'" ··N···· :· ·~···

U
...•..._........... ....................
0
••• h • • J • • • • ' •• ••' • • • •
FTi::~Jerte ·Tfa~$ric a!a~t~riSt~ ...•...•...•.......
··'r-·1···t·t·
1 ~ ~ :;~ ···1···1
···1"··1 ···· ...;... ...i'" i'" ...:... ..'i" ':'"
"'r"'i" 'j" 'j '" ....~..'1'..'j" .'j'... ·"r···r···t ·t···~~~ 1: ::1:..:::~:::: ::: ~ <'··T·"-·"-· ·::r:r~:!:~r~~ "']"']"'1"'1"" -- .~...'f...r'"!.. . · ~·· · t· r· t ·
~ . . '~" ':" " l-" ' l- ' " ~
t
a
s
• 2.OU ..., ..., ........... ................. ..,.... .......•........... ...................... ..., ............... ............. ........ ............. ..... ...
• ••• • • • p ••• • • • • •• • • •• • • •••• • • • • p • • • • • • •
1\1
1.I OU
...................
.U ( Q ~:c)
1 .1 SU 1.2 OU 1.2SU , .31\1 1. 3SU
tRr
................... ................ _... ................... ...................... ................... ......... ......... ...•...•...•....... ...............•.... ................... . ..........•.......
................... .................,.... ..................... ................... .............. ....... . .................. .................... . ..................
••• •••• J • •••~ ...... . .
1. ...OU 1. ...SU 1. SOU l. SSU '.I OU
U_U1H
Figure 11.22 - AMS Simula tor window plotting TIL inverter transfer curve.
11-12 Chapter 11
AC Sweep Examples
The RC circuit of Figure 11.23 is connected to a 1 V sinusoidal source.
It should have a half-power, or - 6 dB, frequency of 500 Hz . A PSpice AC
Analysis will be used to generate a Bode plot (a grap h of the magnitude
and phase of the output voltage versus frequency) of the circ uit respo nse .
The schematic design of Figure 11.23 calls for the source voltage ,
V1, to be stepped from 5 Hz to 0.5 MHz logarithmically, with 100 step s
per decade of frequ ency. The output voltage (at node 5) will be plotted in
decibels in the OUTPUT PLOT window. These simulation parameters are
3 ~5
1VK ~
OVdC~
'" ~ C
.159u
Figure 11.23- RC circuit schematic with Vac source.
ACSweep Type
t) Linear StartFrequency: 5Hz
Options: I~ Logarithmic EndFrequency: 500kHz
~jci§.:;(·~t,,;-+ • IDecade ~I Points/Decade: 100

o Morte Carlo/Wod Case
LJ P~ sweep
EJ T~ (Sweep)
EJ Save Bes Pori
EJ Load Ilia, Pori
Output File Options

f.J Includedetailed bias point information fornonlinear
controlled sources and semic onductors (.OPl
L OK I[ UnceI I[ !Wt II ~
Figure 11.24 - SIMULATION SETTINGS window, AC Sweep parameters.

Figure 11.25 shows a graph of VDB(5) that indicates that the output
voltage magnitude is essentially a dB at 5 Hz, fall s to - 3 dB at 500 Hz, and
then linearl y (on a logarithmic frequency axis) rolls off at 20 dB/decade . The
PROBE cursor shows that at 5 kHz the output is - 20.035 dB , and at 50 kHz
(one dec ade of frequency above 5 kHz) the output is - 39.992 dB.
The pha se of the output voltage starts at 00, is --450 at 500 Hz, and
asymptotically approaches - 90 0 as frequency increases above 1000 Hz.
The Wien bridge network is often used to determine the frequ enc y of
a low-frequ enc y RC oscillator. The Wien bridge, developed by Ma x Wien ,
is a kind of bridge circuit that comprises four resistors and two capacitors.
F igure 11.26 shows half of a Wien bridge, which is the interestin g and
mo re difficult to understand half (the other half is the resistor s in series) .
In order to see the response of the network with the output at node 6, the
input voltage will be swept logarithmically from 10Hz to 1000 Hz with 50
frequencies per decade. The schematic input file in Figure 11.26 sets the
source voltage magnitude to I V ac. Notice that the two resistors are the
same value, as are the two capacitors, although they are specified differently.
The screen capture in Figure 11.27 is subd ivided into two plot s. The
top plot is of the output voltage with respect to the change in frequency,
and the bottom plot displays a change in the phase angle with respect to the
change in frequ ency. As shown in Figure 11.27, the phase becomes 00 at
100 Hz. The phase angle becomes positive below and negati ve above that
100 Hz center frequency. The Wien circuit produces 00 of phase shift at only
one frequency, which is also the frequency where the output amplitude is
at its maximum value.
• -I
=---FS~K
I
Rolls 0 "AtZOdB Dec~::- ?:SK'

SEl)}
.~ ~ "'::.;:.
..-'--_--'-_ _--'-_ _-'--_ _ -'--_ _-'--_ _L.-_--'-_ _--'-_ _-'-_ _-'-_ _ L....:O~ _ _ '
08(U( 5 »
·•" -5lkS+---+---+--+--+--+-~.,__+_-_+--_+--+--+--+_--
·
1
" ..,+----1- - --1-

,... , - -+-- - -1-- -+-- - +-- --+- - --+- - -1-- - 1Ulltl
-1-- - 3 U_
+-----:
1 OM:
D UP( 5)
3: Ottz
"'IZ 180H z 3001 l Z 1 1K Hz Hz
:I DKHz Hz 1 0tIMl
2 0KHZ
Figure 11.25 - AMS Simula tor wi ndow plotting roll -off in dB and phase.
11-14 Chapter 11
8
RTOP
2k
V1 CTOP
1Vac <: .796 u
OVdc - 6
RBOT
2k CBOT
T .796u
Figure 11.26- HalfWien bridge circuit schematic.
""mV
,V
,I
..
,· :;:;-; ~:== ~~
· lOOmV
' 00 OJJ,m 333m) ~
.:::~ :~~
.. ..
..
, ... V1"<S}
·
1
·· ..
, ..
:~
~:
··, .. J_l~ ~ :' _l~_ ~.l.~~J. /.
~
·
1
.. .. .. ..
.. .. .. .. ~~::: ..
.. .. .. .. ..
»
S<l
-1 .Id,
,.." ,
U (
•
)
3
"" 1 ...,
F rpqurncy
3 ..., 1 ....
Figure11.27- AMs Simulator window plotting bothvoltage magnitude and phase at node6.
Sample Circuits 11 -15

Since at 100 Hz the input voltage is I Vat 0 0, and the output voltage
is 0.3338 V at 0°, the gain of the circuit is l/3, 0°. In order to make an
oscillator using this circuit, a non-inverting gain (angle 0°) of 3 (l/( l/3))
would have to be provided. This is true only if the resistors are equal and
the capacitors are equal.
The circuit in Figure 11.28 would be troublesome at best to analyze
L2 L3
C2
RIN
3
e 5
2 --j 4 "
50 '" , - v 2.9uH ",-~ l UH ROUT
" , - v 950p
0.3
VOFF =OV e L1 RP
VAMPL =2V C1 5.5uH C3 710 6
FREQ = 2MegHz 125p 184p
AC =2V
COUT
o BOp
7' 0
Figure 11.28 - Matching netwo rk circuit schematic.
Simulation Settings - AC
Config.rcrtion Fies
lVlalysis type : AC Sweep Type

[pc Sweep/No ise ,. ] ~ Linear Start Frequency: 1 99MEG
Options: (~, Logarithmic End Frequency: 2.01 MEG
rJ Genercll SeltJngs [ Decade ,. ] Points/Decade: 50

ICJ Monte CarioJWorstCase
ICJ Parametric Sweep Noise Analy sis
LJ Terroeratire (Sweep)
o Save Bias Point o Enabled OutputVoltage: I
LJ Load Bias Point I,V Source: I I
Interval: C=J
Output File0 ptions
LJ Include detailed bias point information for nonlinear
controlled sources and semiconductors [.0 Pj
OK I [ Cancel I[ ~ 11 ~
Figure 11.29 - SIMULATIO N SETIINGS window, AC Sweep parameters.
11-16 Chapter 11
by hand at a single frequency. It is a matching network that is to be used at
several frequencies. However, ROUT and GOUT, the resi stive and reactive
part s of the load imp edance, vary with frequency. For this rea son the anal ysis
will be at 2 MHz only.
T he inp ut file of Fig ure 11.28 calls for an AC Analysis at one freq uency,
with six voltages to be printed. The load resi stance, ROUT, is between nodes
5 and 6, and the voltage ac ro ss ROUT and GOUT is between node 6 and
ground. In order to find the magnitude of the ac voltages at each node of
the circuit at one specific frequency, an AC Sweep simulation profile will
be created with a relatively small range. These sim ulation parameters are
Note that since you need onl y to ob ser ve the behavior of the circuit at
2 MHz, the range of the frequency has been set to start at 1.99 MHz and
end at 2.0 1 MHz, with 50 data points per decade. This will provide you
with an output plot displaying only this miniscule portion of the frequency
spe ctrum, with traces centered around 2 MHz.
Voltage measurement markers were placed into the schematic diagram
shown in Figure 11.28 at each nod e of the circuit. The magnitude of each
trace has been labeled on the plot sho wn in Figure 11.30.
Obviously, this is not a high-efficiency matching network. Some of
the voltages, across reactances VM (4) and VM (6) for example, exceed the
input voltage ; this is indicative of some resonance effects occurring in the
matching network.
One of the limitations of PSpice is shown here, which is that a load
·,
U II .IU
··•
VC:ll:a9t NOdtS&.6·0CXXXI~"'.3~l
t
/ .
c::: VoIl;,ge NfJde 4 "(00''',3 0l32)
3."
cc.::....V OJl.a9t' NocI3 "' (2 OOXlM,2.6OO8)
/ VoI.lljj9Node 2 = alXOOM,2 00Xl)

2." I
1. . .
/ V~ age Node 1.= (20c00 M,51700 4rn)
.
1. 91 l1H1i1 z
a U(1 )
1. 9 9 D1t11;l 1 . 9921'4 % 1 ." II"" z
• Vel) .. U(3) ... Uell } • U(5) • U(6)
1. 99 6HHz 1 .9 91 tlHz 2 . 11I0 tIfz 2.GOZt1M z 2 .001l" "Z 2 . II06 HHz 2.IOl tllz 2 • • 1OtlHz 2. U12t14z
Fr l'q utoncIJ
Figure 11.30 - AMS Simulator window, plotti ng the voltage at node 1 thro ugh node 6.

that is freq uency-dependent cannot easily be described to PSpice . Antenna
impedances are one common example of this type of load . Since the load
impedance is a function of fre quency, the inp ut file must be edited (for
load impedance) and a PSpice ana lysis must be done separately at each
frequency.
It is sometimes useful to be able to compare graph ically the performance
of two circuits. In this example, the freq ue ncy response of two seri es
resonant circuits that are identical except for the loss resistance in eac h will
be compared. The Cadence Allegro AMS Simu latorll'Spice AID window
will be used to plot the results on one freq uency axis in orde r to make the
comparison easy.
Figure 11.31 illustrates the two circuits, which are connected in parallel
across a voltage source so a single plot of two response curves can be made.
LL LR
CL CR
"
1--=2'-----rv-YV"'I~-------<r ~----1 ~6
~ W~~
3 ----11- 1mH 63.33nF I
" ""' ' mH
RR
f ~~ OVdCY
3
Figure 11.31 - Parallel RLC circuit schematic.
l::....•..••.••.••• ••.•.. •..•.•••.••.•.•.•.• . .• .• .•.•.•.•.••. ••.• • .•. t/t:\ •• • • •.• • • •..• • • • • • ••••.• . •.• • • •• •. • • ••...•• ••
... .. ...... . ... .............. . . . . /7.Q7.V -/- /. . -\ \........ . ... . .
D" ::::: ::::' :::::'::::':::'::":':"'::'::':::::::::::::.::: ::··:::j ·::·::::r::::y:::::: ·:\;::::::·:·:::::: :·:::::::::::::::::::::.::: .::::.:::: .
. . "'~" " j :\ "~' . .
. ••••.•.•.•••.••.•.~,.•.••;i•• •. • • . • •. •~• ~.~~.•••••
'.2 -'- _~ ....... ::. ~~.::::: :.:::. . ~ .: :?
. +-- -- - - - - - - - - -- - - - - - - -- - - - -- - -- - -- -- ----1
15KHz 25kHz
U( 3) U( 6 ) . 111
Frp quft\ cy
Figure 11.32 - AMS Simulator window plott ing voltage measured from each RLC branch.
11-18 Chapter 11
A similar technique can be applied by placing the two circuits in series when
a current source is the input.
Each circuit is resonant at 20 kHz ; they differ in the series loss
resistance, which determines quality factor Q and bandwidth. The source,
v, will be swept linearly from IS kHz to 25 kHz, and the voltage across the
two load resistors will be plotted.
Figure 11.32 shows the graph of res istor voltage versus frequency
for the two circuits. The substantial difference in the bandwidth of the two
circuits is apparent - the left circuit, with a resistance of lOn, has a lower
Q and larger bandwidth than the right circuit, which has a resistance of
3 n. The PROBE cursors, on the V(3) trace, are located at the half-power
frequencies (19.207 kHz and 20.813 kHz), with the bandwidth computed
to be 1.5967 kHz.
The analysis of a circu it containing an RF transformer with a coefficient
of coupling less than 1 is somewhat tedious, even at a single frequency. To
get a freq uency response plot is not a task anyone would enjoy (or have
time to do) by hand. Figure 11.31 illustrates such a circuit, which is fed by
a current source.
One limitation of PSpice is apparent in this circuit - each node must
have a de path to groun d so that a Small Signal Bias Solution can be found .
This is true for any circu it, even if the Bias Solution is meaningless beca use
there are no de sources in the circuit. Resistor ROC PATH is added to the
circuit so that each node will have a de path to ground. As shown in the
schematic in Figure 11.33, ROCPATH has a value of I x 10 12 n, so its
effect on the circuit perfo rmance is neglig ible . Both primary and secondary
windings of the transformer are resonant at 2 MHz, and the coefficient of
coupling is greater than optimum coupling. This means that the transformer
is overcoupled and will have a very undesirable frequency response.
RPR IM RSEC
2
CRIM
RSO URCE 3l6.63pF CSEC
lOOk RL
T 1 316.6 3PF 30k
RDC PATH
-:-0
1T
Figure 11.33- RFtransformer circuit schematic.

Figure 11.34, the output plot, shows the classic double-peaked
response, where the output had peaks at two frequencies, neither of which
is the resonant frequency of 5 MHz. This is a good illustration of the concept
of reflected impedance, in which the reactance of the seco ndary is reflected
into the primary circuit and detunes the primary.
A circuit with two ac sources is shown in Figure 11.35. One is a voltage
source; the other is a current source. The phase voltage at node 5 is the
unknown , over the frequency range of 1 kHz to 2 kHz. The circuit requires
a dummy to provide a de path to ground for node 9. In the Small Signal
Bias Solution , the capacitor and the ac current source are both open circuits.
RDUMMY has a value of I Tn (l x 1012 n), which should have little effect
··
I
6 OIl
-- --
~~~~~/:
.( 1
-- --
--
--
··,
t
-- -- --
s OIl
R_'-070~':;<: _ --
• OIl
:fA: ..:..:.:.::.... ..
.-
-y- ::k
.... ...
......
- -
-~/ ----X
.. ..
.-
3 OIl
-- _.
.-
.. ..
-y~-
...... ..
-~>z-'
...- .......
_. .. .. -/ {
...... ...
.~\.
.... -.. ..
..
..
, OIl
.- ..
.. --/2(;-.-
..........
:~: :~: ·)SC
...... ...... ..
1 .. ....-. .. . -...... -.... . . . __.. . .. . -..... -.. --.

_.
. ~:
-- -. -- .. .~
.. ::::::::::...::::::"
.. .. .. .. ..
1
,....z , , ...t:
•( .3)
r r lP qu ~cy
Figure 11 .34- AMS Simulator window plotting the double-peaked response.
R CRIGHT
3 5
-I 9
6 10uF 20uF
CMID
Wac ~
V ~ 2Aa
OAdc v
" RDUMMY
1T
OVdc - ell L
1mH
-=-0
Figure 11 .35 - Circuit with two Vac sources.
11-20 Chapter 11
on circuit behavior. The simulation profile dictates that an analysi s occur at
101 frequencies linearly spaced between I kHz and 2 kHz . Results of the
AC Analysis will be plotted in the AMS Simulator window.
In this particular example, the default phase shift of the current source
will be -30°. To assign this default parameter, double-click on the current
source, I, to ope n the Property Editor (see Figure 11.36) . Under the phase
column, enter a value of - 30°.
Figure 11.37 is a graph of the phasor output voltage. The upper plot
indicates that the voltage at node 5 is at a minimum around 1.6 kHz, and that
the phase changes abruptly at the same frequency. PSpice always expresses
phase angles such that the magnitude of the phase angle is 180° or less.
Thus, what appears to be an abrupt change in phase angle may simply be
due to how it is expressed by PSpice.
ACMA G ACPKASl
2Aoc . JO
Figure 11.36 - Property Editor fo r Vac component.
lOY
V
0
........................ .......... .. . ........... ... . ... -_. .. _... _-- --_. ------_.. -------.. .. --_. .. . .. . _-_.. _._.-.. . .. .. .. . .. .. . _----.. . .. .. . .. . ------_._ .- . . _._-- _._---.. ......
_
I . _----- -_............. -_ .............. ......... _._.- ........... . . __............... - ............. . . . . ........... ............. ... ...............- . . ............_- ........... -_.. __........
,
I .. . _._-- . _--_........ ................... .......... . .. _. _. _._. ... -.. .. .
.
. . ... ... _- -----_ ... - .. . _--_ .- .. _
9 ....... . . _.-.......... .................. ................ :::::: :.::~::::::: : :: :: : :: ......... ...... ... .... ...... ..... .. .. ......... :~~ .
sv
. ~j~
".
OY
Viol")
•
,,
h
(I S9~K,~ 272)
·• ..
e
·
1
SEt»
- 2 0 Od
1 .CKHl 2 . 000Hz
VP(5 )
Fr ~ qlJ t'ncy
Figure 11.37 - AMS Simulator window plotting both voltage magnitude and phase measured from node 5.

R1A
15.92k
C1A
3
R2A RINA
15.9 2Meg
4
R3A -=- 0
-=-0
R4A L...../W,,------------J
10k 4.14k
-=-0 R18
15.92k
C18 C28
'---------1 f--_.1~2--j f-----~"-------___._____,
.01u .01u L--_-IT" ~+--_ _-.-J'1f\f\,...15
R2A2
15.92k 75
R38
R48 L...../\II!',, - ---J
10k 15k
-=-0
Figure 11.38 - Active filter circuit schematic.
Figure 11.38 shows two active filter circuits connected in parallel

across an ac voltage source. Each circuit is a second order high-pass filter;
the first has Butterworth response (Butterworth filters are signal processing
filters designed to have as flat a frequency response as possible in the
passband) and the second has Chebyshev response. (Chebyshev filters are
analog or digital filters having a steeper roll-off and more passband ripple,
type I, or stop-band ripple, type II, than Butterworth filters.) The response
is determined by the closed-loop gain of the op-amp . When constructing the
schematic design in the DreAD schematic capture window you may want to
create a VCVS subcircuit using the method discussed in the previous chapter
to give yourself extra practice and to help simplify the design . You may also
choose to simply redraw the circuit with the VCVS linear dependent source .
The input schematic design might have been somewhat simpler if the
subcircuit had been used, but it must be noted that you can obtain similar
11-22 Chapter 11
20
// ~
10
• C h~by~dll~Y R "P ('ll~

//
/ ~--
<>: ~-
v·"
- 10
/ BlJtl~h Re s pon~ e
->
- 20
- 30
-.. /
1 1 0HZ 30 Cflz 1. III Hz 3 . IKH z 1. MZ
.. D8 ( U( S)} • DB(U(1 S)
Fr l'qllf'ncy
Figure 11.39 - AMS Simulator window plotting the frequency response of each filter.
results if you create a similar design using one of the many op-arnp models in
the PSpice library. According to the simulation parameters ofthis particular
example, the frequency of the source is swept logarithmically from 100 Hz
to 10kHz, with 50 frequenc ies per decade.
The plot of the filters' output, Figure 11.39, indicates that the gain of
the Chebyshe v-response filter is higher than the Butterworth-response filter
in all frequencies, with a noticeable peak at 1.122 kHz. While quantitative
data could be obtained from this graph by using the CURSOR feature
of the AMS Simulator windo w, the graph is of great use in qualitatively
understandin g the difference between the se two filters .
A two-transistor BJT differenti al amplifier is shown in Figure 11.40. It
is fed by a voltage source at the base of Q I. This schematic design incl udes
two NPN BJTs. In order to perform an analysis, a simulation profile can
be set up so the frequency is swept logarithmically from 100 Hz to 1 GHz.
A voltage marker has been placed on node 6 of the schematic design to
produce a voltage trace in the output AMS Simulator window. This voltage
trace will be modified in the AMS Simu lator window so the output voltage
(which is the gain, since the input voltage magnitude is 1) will be plotted
in decibels.
Th is is a uniqu e sample circuit in the sense that it utilizes components
from the Breakout library that don 't necessaril y have defined characteristics
and can be modified. Notice the transistor models in the schematic design
are both the QBREAKN component from the Breakout library. The Breakout
library (search for this in the PSpice library) co ntains general tran sistor and

vee
~ 1
I
f
R4
5k
2
Q3
3
~Q breakn
VEE
VSig
I
I
Wa c ~
OVdc -
4
1- V3
R6
I• 12v
1
4.8k
Figure 11.40 - Differential amplifier design using BJTs from the Breakout library.
diode mode ls that are fully custom izable to a user 's specifications . This
model is of an NPN transistor. For this example, we desire a forward beta of
60 and significant junction capacitances representative of discrete devices,
not transistors on an integrated circ uit. In order to change the characteristics
of this transistor model, right-cl ick on either of the QBREAKN transistors
and select EDIT PSPICE MODEL. This will open the PSpice Model Editor
(see Figure 11.41).
Model Editor will indirectly amend the element line for the transistor in
the circuit's netlist by adding user-specified data. In the center of the MODEL
EDITOR window is a large textbox where you will first see a single line of
text that reads as follows:
.model Qbreakn NPN
Click inside the text box and modify the line so it reads, as shown in
Figure 11.42:
.model Qbreakn NPN (BF=60 CJC=16p CJE=30p)
We will discuss the contents of the parentheses in a moment.
The first portion of this line, .model Qbreak NPN, declares that the
transistor model that will be modified is the NPN, Qbreakn. When Mod el
11-24 Chapter 11
"""OfHori:ont.l!y
Mtml4'Vtftlcdy cadence
MinorBCllh
Roh lt
[6it P~._
EditPatt
............
S)tow fooc:print
linl<O",.e.-~P¥t Clrl..t
y_ DJUUw P¥t~ Ctrl-+D
rt':":t:"d l ' ~.··, ,,,,
'if"'<"" I'-.:# l :>
COflMdto IJIK
l~ '
,. I
;..;;;j
__oc_~" :. ~I
" 1' · · · , · · · ·· ·1 . t. . . .. • . . . ,.
IUFO(ORNET-11:56) PSpiCe neUistgenerabonc ~e :
Cfealinlj PSpke toletlisl ! ll ..........r. :/Ili f
It.jF O(ORt tET-104 1) Wrtlilg PSpiCe flat t.jf:t1l5tJ: \C ha~ I~ ~, : p I.Jf .
IUFO(ORt lET -1156 ): PSpice netlist geoerabon cQn1)Ie,ei
( IQCPlftlWQ4 PMlV....... QbrtHN ]
Figure 11.41 - Opening Model Editor.
File Ealt VIeW Model Plot Tools Window eadenee GTe]x
Model Name Type

Qbreakn BIT
Figure 11 .42 - MODEL EDITOR window featuring transistor model from the Breakoutlibrary.

Editor first opened, this was the only text associated with the component.
The dat a in the parentheses , that was just added, show the user-specified
transistor characteristics . BF stands for beta fact or and has been set at a
value of 60 for this example. Both CJC and CJE are junction capacitances
and have been declared as 16 pF and 30 pF, respectively. The se value s of
capacitance simulate the characteristics of a non-ideal transistor and help
dictate the frequ ency response, specifically rolloff, of the tran sistor amplifier
across the range of the AC Sweep .
There are num erou s other customi zabl e parameters for transistors and
diodes that ca n be alter ed in Model Editor; however, there are so many
more that it would requ ire a separate text to provide an adequate definition
of them all. For more informat ion regarding these parameters, a complete
list is available throu gh Cade nce PSpice.
Here 's one last note in regard to Model Edit or: If a user is to enter
enough parameters to take up more than one line of text in the MODEL
EDITOR window, a "+" character must be added at the beginning of each line
to include any data that may have wrapped to this next line . For example,
assume in this exa mple that the junction capacitances wrapped to the next
line. Then the MOD EL EDITOR window would read as shown belo w:
.model Qbreakn NPN (BF=60
+ CJC=16p CJ E=30p)
It is imp ort ant to understand that the AC Anal ysis use s small signal
models for all devices. The input voltage of I V is hardly a small-signal
input, and it causes a great deal more than a small-signal output. Take a
look at Figure 11.43, which shows an output voltage in the pas sband of
50
0
B
v
~~
»->:
(l5613K,4IJ 7)
25
(.t lOOlM, 939)
0
'------- ~ <,
- ""Mill
. · Ud
.
s
-2 Sd
------- <,
(,fl001M. '&5 2)
<,
_
s - SIkl
~
1
<,
- zse
SEt »
1 0 1Hz
o UP ( 6 )
'OOltz 1 . GKHz 3.C«Hz 1 0KHz 30K Hz 1001(112 30 01(H" 1 . GUHz 3 .atlHz 1 0tlHz
--- r--
3".lIz 1 00t llz 3D1I1Hl: 10 KH Z
Fr'l' qu l'lIcy
Figure 11.43 - AMS Simulator window measuring phase and dB at node 6 with respect to frequ ency.
11-26 Chapter 11
40.897 dBV, or 111 V. This is a ridiculous result and could not happen in
the actual circuit because the power supplies would limit the output to about
12 Vpp. However, it is convenient to use 1 Vas the input magnitude, since
the output voltage is then the same as the circuit gain.
If the input were specified as 1 kV, the output would simply be 111 kYo
Clearly, you must be careful when interpreting results of an AC Analysis to
be sure that the numbers are reasonable. If you wanted to see the effects of
nonlinearities, such as clipping of the output due to the transistors becoming
cut off and saturated, a Transient Analysis would have to be performed.
The Transient Analysis does not use a small-signal model as does the AC
Analysis.
The Bode plot shows the half-power frequency to be at 4.1 MHz, as
indicated by the 3 dB (2.958 dB is shown) drop in VDB(6) and the phase
angle of --45° near that frequency.
Transient Analysis Examples

In Figure 11.44, a capacitor and resistor in series are connected to a
triangle voltage source . The triangular waveform is made using the PWL
function and varies between 0 V and 1 V, with a period of 2 ms.
After the schematic design is drawn into the OreAD schematic capture
window, the characteristics of the piecewise function need to be defined.
To do this, double click on the VPWL voltage source, VIN, to open the
Property Editor for this component. If they are not already present, you
must create columns for each timing increment of the triangular waveform .
For a triangular waveform to run for a total of 6 ms, it will require seven
R
11<
VIN
C
2uF
Figure 11.44- RClow-passfilter with VPWL source.

increments of time, ranging from 0 ms to 6 ms. Simply click the NEW
COLUMN button and add column s as shown in Figure 11.45. In column T1
enter a time of 0 ms, and for each following column increment this value
of time by I ms.
Next, voltage magnitudes need to be defined at each increment of
11 n
0 _ _ • _L ~~ . 2'IlI , 5/11
_ _ -1- ~ ' . L
- -- - -- -- --
Figure 11.45 - Property Editor for VPWL displaying timing instances.
."'~ --
cadenc
II VI V2 V3 V' VS
.----.---.--. -- - -----..--- - . - .---.--- --- .-_ .-- ----- ---,--- - -------------,I
Figure 11.46 - Property Editor for VPWL displaying voltages associated with each timing instance.
.
U 1 . QU
.
1
t
: ' .IU
I I\Vlj I 1\ I 1\
0. 6u
1/
/ \ \ 1/
/ \ \ 1/
/ \ \
~
/ \ / /i / / \~
I . "U
\ ----------
/ .> \ /V /
] c pacitorV age \ 7 \
0.2 U
'"
I/~
"., U(5 )
O.S ns
_ U( 8 )
-: 1 . Gns 1 .5~
\ 1/a. .... 2.>"5 3 .Ons 3 . 5ns
\I It. Ons ".5"'1 5 .,,"s 5 .S ,"
\
......
Tl_
Figure 11.47 - AMS Simulator window plotting capacitor voltage in relation to the input triangular waveform with
respect to time.
11-28 Chapter 11
time. Create voltage columns for each of the seven voltages , similar to
what is shown in Figure 11.46. When the Transient Analysis runs, the PWL
waveform will be generated based on each pairing of voltage magnitude and
time; T1 will be associated with the magnitude of V1, T2 with V2, all the way
through T7 and V7.
Figure 11.47 features this triangle voltage from 0 ms to 6 ms only.
Note that there are seven time-voltage pairs in the PWL definition (see
Figures 11.45 and 11.46). A simulation profile will be created for a Transient
Analysis that ranges from 0 ms to 6 ms, using time steps of 0.01 ms.
An examination of the graph of the capacitor voltage in the output file,
shown in Figure 11.47, indicates that the capacitor voltage started at 0 V and
had nearly reached steady-state in 6 ms. The average value of the triangle
input voltage is 0.5 V.
For analyses that require many cycles of a periodic triangle waveform,
using a PWL source can become rather tedious. A better way to generate
a periodic triangle, pulse, saw tooth, etc . waveform is to use the PULSE
function (the VPULSE component in the PSpice library). When doing so,
it is important to use a tiny (compared to the period) but non-zero value of
pulse width. The rise time and fall time are set to equal half the period of
the triangle waveform.
The PWL source is a unique source as it gives the user the opportunity
to deliver any conceivable periodic or dynamic voltage/current to a circuit.
It is a broad concept, but might be better understood from the standpoint
of the component's element line within the netlist. An element line will lay
out all the instances of time and voltage/current in a single line of data . For
example, a periodic triangle waveform identical to the PWL triangle in this
example could be produced by the following element line:
VIN 5 0 PWL(O 0 1m 1 2m 0 3m 1 4m 0 5m 1 sm 0)
Outside of the parentheses, PWL designates that this is a PWL voltage
source . Inside the parentheses, the data can be broken up into pairs. The
first two values are both 0; the first value of the pair is time, and the second
is the magnitude of voltage. In a sense, this can be looked at as similar to
an ordered pair. What this means is at the time of 0 s, the source will output
o V. Moving on to the next pair, the values are 1m 1. This means that at
1 ms the source will output I V. The fact that this is a PWL source means
that between the times declared there will be a linear rise or fall between
the declared magnitudes of voltage . This example of a triangular waveform
is ideal for this type of source. Based on the values discussed in the first
two pairs, it is expected that we will see a linear rise from starting from
oV at 0 s to I V at 1 ms depicting the rising edge of a triangular waveform.
To demonstrate an alternative method of generating a triangular

waveform , a VPULSE source could also be used. Its element line would
look much different, as shown below.
V IN 5 0 PULSE(O 101m 1m 1n 2m)
Reading from left to right in the parentheses, we see the initial pulse
value is 0 V, the pulsed value is 1 V, the delay time is 0, the rise time is
I ms, the fall time is I ms, the pulse width is I ns (one millionth the rise
or fall time), and the period is 2 ms. After 1000 cycles or so, the I ns pulse
width, which should be 0, will start to introduce a slight error (a cumulativ e
lengthe ning of the period by 0.0001 % each cycle) . However, the error is so
slight that it doesn't much matter for any practical purpose.
Using either the VPWL or the VPULSE source, PSpi ce will produce
virtually the same output plot.
In Figure 11.48, an inductor and capacitor in parallel (tank circuit) are
connected to a pulse current force. The tank circuit has a resonant frequenc y
of 1007 Hz. This is a circuit that can be realized on paper only, as it is
completely lossless. The pulse is very short, with a magnitude of 1 A.
As in the previous example, the user must define the characteristics of the
current PWL component, IPWL, using the Propert y Editor. In this example,
the only difference is that each pair will be comprised of an increment
of time and a magnitude of current instead of voltage . Figure 11.49 lists
all important values of time, and Figure 11.50 lists the magn itudes of the
source current that will correspond with those times. Figure 11.51 depicts
an output plot measuring the current pulse from the PWL current source,
I-IN . Figure 11.52 plots a measurement of the tank voltage . The pulse starts
at I ms, and the tank voltage begins ringing at the same time. After the pulse
I-IN
• C
SOm
.SuF
L
-=-0
Figure 11.48- LC circuit with IPWLsource.
11-30 Chapter 11
O<CAD Capture CIS- Lik - [Property Editoij
~ Fife Place 51Analysis Macro
Start Page l[ij l'RAl'lSlei... X~ PAGEl SOtEHAlL. ]
[NewProperty...J ~ I D~pIaj>::L[@ile_~~~_C~ Fillerby. 1~<=Cu=r=ent=,=propef

===Iie="====== ==_-,
~ I~
T1 T2 T3
o 1m 1.1m
Figure 11.49 - Property Editor for IPWL displaying timing instances.
-------------------------------
- .~ -- - - -' - - - - - - -- ~ --~- ~ ----~._----
Figure 11.50 - Property Editor for VPWL displaying curren t magnitudes associated with each timing instance.
1. ..
C
u
.
,r-
n
t O.SA
so u~ urrent
1 . 6 11
~
I
g .~A
1.2.11
.. es
<I 1(I -fH)
'''-lans U.8ns 1 . 2M 10 6 m;. 2 . 011'> 2. l m s 2 . 8ns 3 .2n... 3 . 6~ 'l .U n s
Tint'
Figure 11.51 - AMSSimulator window plotting source current with respect to time.

ends at 1.3 ms, the tank voltage continues to ring with constan t amplitude.
This is due to the total abse nce of loss in the circuit; the tank will ring for
as long as you care to do the Transient Analysis.
A PWL source can be used to make any arbitrary waveform whatsoever,
providing you have the patience to put all the informati on on the element
line. This example contain s an electrocardiogram (EKG) voltage over a time
interval of 500 ms, with data point s every 5 ms.
The circuit shown in Figure 11.53 is a single-pole RC low-pa ss filter
connected to the EKG voltage. It has a breakpo int frequency of 10 Hz.
....
·•
1
··• ....
t
/\ .: I 1\
. -I \ 1/ 1\ 1 \
Tank ottage ____
-211M.'
\1 \ / \ / \
~
-IiIQU
D .~"s '. 6ns
V
2 . 0ns 2 .~ "s 2 . ' n~
~IJ 3. 6ns ~ .on s
".. U( 1)
1 .8 M ' . 2RS
TiM'
3 .2 " "
Figure 11.52 - AMS Simulator window plotting tank voltage with respect to time.
R
2
10k
V1
C
1.6uF
-=-0
Figure 11.53 - RC low-pass circuit with VPWL (EKG) source.
11-32 Chapter 11
After ente ring the low-pass filter circuit into the OreAD schematic capture
workspace, one must enter the timing and voltage pairs of the PWL voltage
source, V1. Using the same method as shown in the two previous examples,
adding new columns into the Property Editor, the voltage and timing pairs
are incorporated into the schematic design to replicate a beating heart. You
may recall how tedious it was when entering the timing/magnitude pairs in
the previous examples, and a waveform as complex as this can be rather
monotonous and time con suming, but it can be done (see Figure 11.54).
However, there is a much easier method.
With the PWL element line discussed earlier in this chapter, it is possible
to simulate a circuit using onl y a netlist text file. To refresh yourself on this
process, refer to the second netlis t discussion (Chapter 5). Using a VPWL
source named "VGEN", a netlist was created in a Text Editor as shown in
R
1 2
f~
10k
1"-
C
1.6uF
T1 = 0 '11 =-1 T21 = 100m '121 =-9 141 = 200m '141 = 34 T61 = 300m '151 = 1 T81 = 400m '181 = 28
T2 = 5m '12 = 2 T22 = 105m 'In =-7 T42 = 205m '142 = 12 T52 = 305m '162 = 3 T82 = 405m '182 = 32
T3 = 10m '13 = 2 T23 =11 Om '123 =-8 143 = 210m '143 = -10 T63 = 310m '163 = 2 T83 = 410m '183 = 33
T4= 15m '14 = 2 T24=11 5m '124 =-9 T44 = 215m '144 =-25 T64 = 315m '164 = 2 T84 = 415m '184 = 35
T5= 20m '15 =4 T25 = 120m '125 = -7 14 5 = 220m '145 =-30 T65 = 320m '165 =4 T85 = 420m '185 = 38
T6 = 25m '15 = 5 T26 = 125m '125 = -7 T45 = 225m '14 5 = -30 T65 = 325m '155 = 5 T65 = 425m '185 = 38
T7 = 30m '17 = 4 T27 = 130m '127 =-8 T47 = 230m '147 =-26 T57 = 330m '167 = 3 TB? = 430m '187 = 37
T8 = 35m '18 = 8 T28 = 135m '128 = -6 T48 = 235m '148 =-20 r ea = 335m '158 = 6 T65 = 435m '188 = 39
T9 = 40m '19 = 8 T29 = 140m '129 = -7 T49 = 240m '149 = -14 T69 = 340m '169 = 7 T89 = 440m '189 = 36
T10 = 45m '110 = 7 T30 = 145m '130 = -9 T5 0 = 245m '150 =-10 T70 = 345m '170 = 7 TOO = 445m '190 = 34
T11 = 50m '111 = 8 13 1 = 150m '131 =-9 T51 = 250m '151 = -5 T71 = 350m '171 = 9 T91 = 450m '191 = 31
T12 = 55m '112 = 8 132 = 155m '132 =-8 T52 = 255m '15 2 =-2 T72 = 355m '172 = 11 T92 = 4 55m '192 = 26
T13 = 60m '113 = 6 133 = 160m '133 = -10 T53 = 260m '153 =-3 T73 = 360m '173 = 11 T93 = 4 60m '193 = 22
T14 = 65m '114 = 4 13 4 = 165m '134 =-9 T54 = 265m '154 = -3 T74 = 365m '174 = 12 T94 = 465m '194 = 19
T15 = 70m '115 = 3 T35 = 17 0m '135 = -2 T55 = 270m 'I SS =-1 T7S = 370m '175 = 15 T95 = 470m '195 = 14
T16 = 75m '116 = -1 136 = 175m '136 = 9 T56 = 275m '156 = -1 T75 = 375m '176 = 18 T96 = 4 75m '196 = 10
T17 = 80m '117 = -4 T37 = 180m '137 = 25 T57 = 280m '157 = -2 m = 380m 'In = 18 T87 = 480m '197 = 7
T18 = 85m '118 = -4 138 = 180m '138 = 4 4 T58 = 285m '158 = 0 T78 = 385m '178 = 23 T98 = 485m '198 = 5
T19 = 90m '119 = -6 139 = 190m '139 = 54 T59 = 290m '159 = 1 T79 = 390m '179 = 25 T99 = 490m '199 = 2
T20 = 95m '120 =-9 T40 = 195m '140 = 49 T60 = 295m '160 = 0 TOO = 395m '180 = 25 T100 = 495m '1100 = 1
T101 = 800m '1101 = 1
Figure11.54- Schematic file with timing and voltage properties displayed(Schematic Capturemethod).

Figure 11.55. Instead of undergoing the long process creating and naming
new column s for timing and voltage in the Property Editor, all of the data
was simply typed into the text file and simulated using the AMS Simulator.
Either way you choose to run this simulation, the software will yield
the same output as shown in Figure 11.56. Referring to Figure 11.55, the
PWL independent source element "line" actually requires 16 lines, using the
EKG- LP . CIR ELECTRO-CARDI OGRAM VOLTAGE INTO LOU- PASS F ILTER

VGEN 1 0 PUL ( O - 1 5M 2 101{ 1 15M 2 10 tl .j 25M 5 30M .
3 511 a 40U 8 -ISH ? SOH 8 SSM B 60M 6 6 5M <1 70 U 3 7 5M - 1
+ 80M. - ~ 8511 - 4 Si OM: - 6 '35.l! - 9 100 M - 9 10 5M - 7 110 M - ;;:
+ 11 5M - 9 12 0M - : 12Stl - 7 DOli - 8 135M - 6 140 H - 7
+ USH - 9 150M - 9 15SK - 8 HOH - 10 16S!! - 9 1 70U - 2
175M '9 1 80H 2S l8SH H 190M S. 195M 49 200M 3 4. 205H 12
210K - 10 215M - 25 2~O M - 30 '::25M - 30 230 M -::~ 6 235 M - 20
240M - 14 24 5M - 10 250 M - S 2SS}1 - 2 260M - 3 ~65 }{ - 3
+ 270M - 1 275M - 1 280 M - 2 285 M 0 2~O M 1 ~ 9 5 H 0 300 M 1
+ 30SM ::I 31011 .:! 31511 :: no}! 4 32SM 5 330M J 335M 6
H OM 7 3 ~ S H 7 35 014 9 3S ;;'H 11 3~O l! 11 36 5M 1 ;; 370 M 1S
315M 18 ::aOH 18 385M 23 390 M 25 ~%M 25 400H 2G
+ <OSM 32 H OM 33 415M 35 .20M 36 ' 25M 36 130H 37
43 SH 39 HOM 36 US" 34 4S0U 31 455H 2b -t60M 22
46 SH 19 470M 1.( 475M 10 430H 7 4:?- SM 5 "90 M 2
. S5M 1 500 M 1 )
1 ::: H!Y.
:: 0 1. 6U
. TRJ.U 1M soot! 0 111
. PROBE
. EnD
Figure 11.55 - AMSSimulator window with an active netlist depicting the schematic design (Netlist method) .
...
·•
u
f\
1
··• ...
E G Unfiltered Source Volt
-. I/ r ~,
..
gel
' ou \\ EKG Filte ed LPF r:
. ~ ~", ~// \/ ~ ~
-, .
~':: '"
,.d/
\v7
V
-.ou Is
II U(1) • U( 2 )
s_ ,,- .. - 2'_ ,,-
liM'
3.- os_
..- ..- s._
Figure 11.56 - AMs Simulator window plotting pure EKG (Input) and filtered EKG (Output) .
11-34 Chapter 11
+ symbol in the first column to indi cate a continuation of the previous line.
An interesting circuit to study with Transient Analysis is a half-wave
rectifier with a capacitor filter. The inrus h current at the time of turn- on is
not easily measured in the labo ratory without some kind of storage device
(analog or digital storage oscill oscop e). With PSpice Tran sient Ana lysis
this phenomenon can be easily exa mined in great detail, and insight can be
gained into power supply operation. Figure 11.57 is the schematic diagram
of the rectifier circuit. A Tran sient Analysis will be carried out for this circuit
that will run from 0 ms to 40 ms with a step size of 40 us.
Figure 11.58 plots the load voltage on the top and the diode current on
01 R1
10 15
-{)t-
1
01N3940 1
VOFF=OV
. VAC CFILTER
RLOAD
1k
VAMPL= 100V "-' 40uF
FREQ = 50Hz
AC=1V
~
-=- 0
Figure 11.57 - Rectifier circuit schematic.
;- ...jZ:==~~~ . ·~ =t:=s t:::=FC ~

~"JN
~ lf""'-
9
'
.i:.:
ov,.lL-_ _ --!. - ' -_ _ ----L ...J......_ _ ----L ...J......_ _----L ...J......_ _---'_ _- J
, " ,T·_
V{:....
'5:....
1_ -, -,-_ _ -,. ...,-- _ _ -,. ...,-- _ _ -,. , -_ _ --;_ _ ---,
r:;;:: . : . . . . . (2~ ~?<';;:~~ji . : . . .. "':.

c " . .::~ •• .... ~ .. .. .•
,
~ s:,~ . . \: . ..:. :\~/ ..
lk lNts a llIS 12 ns 16M 2 ,," 5 211M 21 M 3 2M 2 6l111" ItCMs
0 1( 0 1)
Figure 11.58 - AMs Simulator window plotting output voltage and diode current with respect to time.

the bottom. The load voltage rises from 0 V, peaks at nearly 100 V, and has
the quasi-sawtooth shape characteristic of a poorly filtered power supply.
The ripple voltage is about 33 Vpp' Using the cursor, we can see that the
diode current during the first positive half cycle (enrich current) peaks at
about 1.26 A, while during the second positive half cycle the maximum is
1 A. This is because the inrush current must charge the capacitor, which is
initially at 0 V, and raise its voltage to 100 V. On subsequent positive half
cycles, the capacitor voltage is never less than 62 V, so less current is needed
to raise its voltage back to 100 V.
A complementary metal-oxide semiconductor (CMOS) FET inverter
NAND circuit is connected to two square wave voltage sources in the next
example, and the output is determined as a function of time . The two square
waves will provide all possible logic input conditions (11, 01,10,00 binary)
to the NAND gate. The logic NAND gate is made with four enhancement
MOSFETs; two are N-channel and two are P-channel.
Figure 11.59 shows the circuit, in which the NAND gate output is
VDD
«
I VDD
10V.:b-
V1 = 0 V1
V2= 10
TD=1U
TR=5N
TF =5N
PW =5U
PER = 10U -=- 0
V1 =0
V2= 10
TD =1U
TR =5N
TF =5N
Figure 11.59 - CMOS two input NAND gate schematic design.
11 -36 Chapter 11
loaded resistively and capaciti vely. The circuit consists of four enhancement-
type MOSFETs and two VPULSE sources that output square waveforms
that make up a binary input to the NAND circuit. For enhancement-mode
MOSFETs, VTO is positive for N-channel devices and negative for
P-channel devices. The starting time of the pulses is delayed by I us, and
the rise and fall times (5 ns) are quite small compared to the pulse widths
(5 us and 10 us). A simulation profile is set up to run from 0 ms to 24 f.ls
with a step size of 24 ns.
The analysi s results are shown in Figure 11.60. The upper plot contains
the two input voltages and the lower plot is the NAND output voltage by
itself. It can be seen that the NAND gate output is low only when both
inputs are high , and the rise and fall times of the output are significant. If
desired , the cursor in PROBE could be used to measure rise time and fall
time of the output.
A 7404 TTL inverter logic gate is shown in Figure 11.61 . It is fed by a
TIL-compatible square wave (well, nearly square). The output is connected
to a pull -up resistor of 2 ill. Thi s design uses a configuration of four NPN
BJTs connected to a VPULSE input, V2.
Again, this design will use the NPN transistor from the PSpice Breakout
library. In order to run the simulation, parameters need to be declared in
Model Editor. Open Model Editor as shown in Figure 11.62. The parameters
for the four transi stors are shown in the MODEL EDITOR window (see Figure
11.63). Save these changes and run a Transient Analysis on the circuit with
a start time of 0 ns and an end time of 105 ns with a step size of 105 ps.
!1IU
,su
D .
.. Is
• Uel)
.. ,.. ,..
-~,--~---+--------- -~------I------~-~--j
:U'I , " us 18.,'1 'Iu,
22u5
Yio,
,..., ' Iu,
,
...,I
..., ,. ,
tJ
10,.. 12us 16u5 181$5 'Iu, 22'1'5
~y
,
u su
..
.. Is
. U(IJ )
-_--~-- ---~-~--~--~--_--~-~--'--~-__l
2.5 ... , hs 'u, 'Iu, 1 211'1
,
11111'1 1 6115 1 1115 ..., ,
22:11'1 2 o\Us
Figure 11.60 - AMS Simulator window plotting the inputs and outputs of the NAND circuit with respect to time.

VCC
RC03
VCC 130
<? RCQ2
~V1 1.6K
03
7
5V
-T RB0 1
4k
~ RPULLUP
2k
-=- 0 5
2 Dl
Q2 D1N4002
1 3
'.V 01
Obreakn
Ob akN
6
V1 =0 V2
V2 = 4
TO = 10n REQ2
TR=2n lk 0
TF =2n
PW=20n
PER = 48n
-=- 0
Figure 11.61 - TIL inverter schematic.
'!'iJiiiiII" i
cadence _ It
6M-
Glot..-lRep..clt_
A~ P. rt :~} To ~ovp
~~ PMt'sl F Il~." G fC ~
~~.2~
"1· ' ' · 2· .. .~ ··t· ... t · ..... . ' "L. ~
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J
Cfeating pspce Hensl
INFO(ORrlET-I 041 ). Wrrt.ng PSpIce Flat t~t!isIJ \CHAPTER 12\PSPtC E Fll ES'F igUre 12.5!\fgu re 12-58-PSplc e Fite5\SCHElIAOC1 \SCHEf.tATlCt ~!
IUFO(ORr./ET-1156): PSpice netltsl geoerabon com~ .._ _ . . __
Figure 11.62 - Opening Model Ed/tor tor the breakout component.
11·38 Chapter 11
The input file, Figure 11.6 1, describes the input pulse as going from
o V to 4 V after a IOns delay, with a 2 ns rise time and fall time , a pulse
width of 20 ns and a period of 48 ns. Th e transistor model QBREAKN
includes a substantial number of parameters that override the PSpice default
parameters for a BJT.
The PROBE display is a graph of input and output voltage s (see Figure
11.64). The output waveform is valid from a logic standpoint, and it shows
the distortions that are to be expected from a TTL logic gate operated at
20.8 MHz.
Transient Analyses on astable circuits and free-runn ing oscillators can
~ 12-62:Qbrealcn - PSpice Model Editor Lite - [Model Text]

.t!elp
o dels List . mo de l Qbre akn NPN (BF= 50 BR= . l RB= 7 0 RC=40

Mod el Nam e Type
+ Tr=1 0n CJE= .9p CJC= 1 . 5p CCS= lp VA= 5 0)
Qb realcn* BIT
Figure 11.63 - Active MODEL EDITOR window for component QBREAKN.
.
V 6. 1U
I
t
.
; 5.1tU+----"
....
3."
2 .0 U
,...
..esL----L~_____.:;::====:;=::f..-~-~~~~====:::;:::t-~-~~ I
aU ( 1)
1 Dns
. U( ' ) "." "." 5 1n, 71... " ns 91n. 1 Ion s 11lns
Figure 11.64 - AMS Simulator window plotting the input and output waveforms of the inverter circuit.

be a bit tricky to accomplish, and one must pay careful attention to the initial
conditions in the circuit. For example, the circuit shown in Figure 11.65
has complete symmetry (at lea st on paper), but in reality, at the time power
is applied to the phy sical circuit, one tran sistor will go to saturation and
the other will become cut off. As far as PSpice is concerned, it is unknown
which transistor will win the race to conduction. In order to help PSp ice
with the transient solution, a good technique is to set some initial conditions
to give PSpice a starting point for further analysis. This , of course, requires
that you have an understanding of how the circuit starts and runs .
Initial conditions include the five node voltages specified in the voltage
source parameters, where at time 0 0 1 is on (set by V(1)=.1 and V(3)=O.8)
and 0 2 is off (set by V(4)=6 and V(5)=-6). Of course, in a phys ical circuit,
slight differences in transistor parameters and/or stray circ uit capacitance
might just as likely cau se the oppo site condition. To aid the efficiency of the
computation during this simulation, options of the simu lation profile will
be modified. Parameters of the Transient Analysis will be entered into the
SIMULATION SETIINGS window as usual (see Figure 11.66).
In this window, select the OPTIO NS tab and assign the value of RELTOL
to be "0.0 I" (see Figure 11.67). This makes the relative tolerance 1%
instead of the default value of 0.1 %, which saves some computation time
R1 R4
1k 1k
VCC
<;> V1
C2
6V ~
20u -T
~
C1 -=-0
1 20u
4
Q2 03
'-L.
-=- 0
Figure 11.65 - Astable mult ivibrator circui t schematic.
11·40 Chapter 11
~""
Simulation Settings - TRAN
•• ..>.<"
~ Iype:
Run to time: 2.5s seconds (TSTOP)
[TITle Doman (Tr<mien) ... 1
Start saving data after: 0 seconds
Options :
General Settings - Transient options
lEJ Mott e CarlolWor.:tCase Maximum step size: 2.5ms seconds
IE] Parametric Sweep
lEJTempernlu"e (Sweep) [J Skip the initial transientbias point calculation (SKIPSP)
EJ Save BiasPoirt
[J Load Bias Poirt
EJ Save 01eck Poirts
EJ Run in resume mode IOutflUt Fae Options... )
EJ Restart SiTUation
OK I[ Ca1ceI I[ PWt )[ ~
Figure 11.66 - SIMULATION SETIINGS window,Transient Analysis.
Simulation Settings· Trans

- ~
General. I ~ I ~ Res J Options l Data CoIedion.. 1.Probe Wrxlow I
(.OPTlON)
~egory:
Relative ~uracy at V's andI's:
---
0.01
=ttt~ I
(RE LTOL)
Bestaccuracy at .!tollage;: 1.Ou volts (VNTOL)
Best accuracy ofcl!lrenls: U lp ,,",ps (ABSTOL)
Best accuracy at chaiges:
---
O.Olp coulombs (CHGTOL)
Mininurn conductance 101 any 1!Ianch: 1.(£·12 1/0hm (GMIN)
DCllndbills "blind"~eJation imt 150 OTL1)
DCandbills"bestguess" ~eration ~: 20 OTL2)
Irarnient tine point ~eJation timt 10 [ITL4)
Default ~ temperature: 27.0 'C (TNOM)
[J Use!!.MIN stepping to implove convergence. (STEPGMIN)

EJ Usell'eOIdeJing to reduce matrix fiD·h (PREORDER)
§~ge. .. l !MOSFET Options...IIAdv¥lCed Qplion$·..11Beset I
I OK II Qlncel ]1 ewr II ~ I
Figure 11.67 - Adjusting relative accuracy in SIMULATION SETTINGS window.

on a circuit such as this with very fast voltage transitions.
The graph in Figure 11.68 shows the collector voltage of 0 1 in the
lower plot and the base voltage of 02 in the upper plot, versus time. The
collector voltage is essentially a square wave, and the base voltage shows the
exponential charging of the 20 rtF timing capacitor connected to it. PROBE's
cursor used on the base voltage waveform allows the oscillation period to
be measured as 1.4539 s. The behavior of the circuit once free -running
oscillation has started confirms the validity of the original initial conditions.
·
u
?/
1 au
··•
t
/'
/ V
- 2 . SU
-: //
- S . 8U
D V( 2)
V /
U
.
~
t
6.W
: ' .IV
( (
Z ...
sn,» ~
ou
..D U ( 1)
1 .2 5 1 . "5 1S.6 s 1. l s 1 .b 1. 2 5
Ti ...
1....5 1 .6 5 1 •• s 2 . es 2 .25 2. "5 2. 6s
Figure 11.68- AMSSimulator window plotting the fr ee-running oscillation of the astable circuit.
RE
RA
5
10k
RC
10k
GAIN =50000
10k E
DA RIN2
2 1Meg
Dbreak
RB GAIN = 50000 E RD
DB
3 4
V1
10k
RIN1 5k
-=- 0
VOFF =0 Dbreak
"v 1Meg
VAMPL= 1V
FREQ = 100Hz
AC = 1V
-=- 0
-=- 0
Figure 11.69 - Precision recti fier schematic .
11-42 Chapter 11
A real diode has an offse t or barrie r voltage (about 0.6 V for silico n) that
mu st be overcome before forward conduction begin s. Thi s makes real diodes
unusable by themselves to rectify low-level voltages like audio signals. For
rectifying small voltages, another technique must be used to overcome thi s
limitation. Figure 11.69 is a pre cision rectifier circuit, sometimes called an
absolute value circuit. The input file in Figure 11.69 models the two op-
amps using VCVSs with a gain of 50 ,000 V N, which is controlled by the
differential voltage across nodes 10 and 20 in the subcircuit. Each VCVS
essen tiall y models an op-amp (similar to pri or examples) with a very high
input resi stance. The very large open-loop gain of the VCVS-m odel ed op-
amp Ell is used to negate the diode offset voltage.
The diodes are truly ordinary in that they are mod eled by the PSpice
default diode parameters, which gives them an offset voltage typi cal of
silicon. The input voltage is a I Vp, 100 Hz sinuso id, and the Tran sient
Analysi s occurs for two complete peri ods of the input. Thus the simulation
profi le will be set for a total runtime of 20 ms with a step size of 20 IlS.
In Figure 11.70 the input voltage is plotted in the top gra ph and the
output voltage in the one belo w. Th e output voltage is indeed the absolute
value of the input voltage, with no visib le differ ence between input and
output peak voltage caused by a diode . The accuracy of this circuit depends
on both the large op en -loop voltage gain of the op -am p and the ex act
matching of the resistors.
Figure 11.71 is the schematic diagram of an amplitude modulation
gen erator, although PSpice has a built -in model for a frequency modulation
generator (SFFM ind ependent source), it do es not ha ve an amplitude
U1
:
0\1 • Vi')
··Z
~....."' ;i"::::'"
':'::::\
• ./
~:::: . :::::/ '\ '-. l::: / ",;
fl. .
; .:::::::/:.:.: . .. . ~:::: :\ <I:::: '.:" .< . : .:\~:: : ::
·1::/ ::::::::::::: :::::::::: : : :

•.s
SEl»
\.:.:.·: .: :.·: .: .: .j·:· ·. /:...·:. ·.R.:".~~·~.l·~:~.:~ ~·.~ .: ·.; :.~;.·:.R :;.: '.: l,.:;.~.~ I··
i/ ::::::::::::: : ::::::::::::.:: ::::\ l-
.. .•.·;.. :::l :... .:' :.:\:
•.l:.'::..·. :\:.: :/:.:.::/::.::.:.:.: :.:.:.:. ::::::::. ....
.... ::: . \ .\j:::: .:" .. .. ....::\
au
o~ z es " ns 6n s a~ 10n s 12ns 11lns; 16ns Hln~ z ens
U(6 )
Figure 11.70 - AMS Simula tor window plotting the full-wave rectif ication of the input waveform.

modulation generator. By using a MULT component from the ABM (analog
behavior model) library, it is possible for a user to take a carrier waveform
and multiply it by a modulation waveform. The modulation inde x can be
changed, as can the carrier freq uency and modulation frequency. Wh ile
the SFFM source is limited to a pure sinusoid as the modulation, the AM
generator could be modulated by any kind of waveform. A basic Transient
Analysis will be carried out on this circuit with a run time of I ms and a
step size of I us,
The 40 kHz carrier waveform is shown in the top of the output plot in
Figure 11.72. The 2 kHz modulation waveform is shown as the trace in the
10
20
VCAR VMOD IN
VOFF=OV VOFF= 1V <: R2 30
VAMPL = 10V <: VAMPL = 1V 1
FREQ= 40kHz Rl FREQ = 2kHz v
AC= 1V 1 AC = lV
7"0
Figure 11.71 - AM generator schematic.
~ ' :11A~~AA ~ ~~!\A A.

GS 3~~UA ~.
tS
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..• V}'lJI-- . \. ._ u
.··\..1:1:: :V·.V:Y:::·2:..•
'1( 21 ) [
SEl »
.V V . .. - • '.r:~.!Y.~ .. :.\-1::\1..
. 0 - -
.:-:HJI:: ~V·.V.:y.~. ~:' •.:::.:.::•.:::.:~YY: ...
tJ...~.. . ·~u:··v~· .
•• ,
V·
•••• • •
-,'" - - - + - -- -
Is I . 1M D. 2ill1S D. 3 M 1 . lIftS 1 . 5ns 1 .6 M 1 .7 ns I . '"S D. 9 M 1 . 1M
II U( 3 1)
Figure 11.72 - AMs Simulator window plotting the carrier, modulation, and modulated waveforms.
11-44 Chapter 11
u , ..
I v
••
2•
.. -I----~- --~ --~--'--~ --L-~-L-~---'--~ -- ~---~--_I I

' . HZ 12 K": 3ltICHZ 31 KHZ il811: Hz 50K Hz
a U(R3 :1)
Fr pqum clI
Figure 11.73 - AMs Simulator window plotting a fast Fourier transform of the modulated waveform.
middle plot, and the amplitude-modulated waveform is shown in the bottom

plot. Remove all of the plot s from the PSpice window, aside from the AM
waveform from the bottom plot. With only the AM waveform displayed,
click the FFT button in the top of the AMS Simu lator window. Clicking the
FFT button performs a fast Fourier transform (FFr) and plots the component
frequencies of the output waveform. In Figure 11.73, the FFr is visible. The
carrie r amplitude is in the center of the plot, accompanied by the upper and
lower side frequencies present as a result of the 2 kHz modulation frequency.
In Summation
This chapter puts together all aspects of the design and simulation
procedures covered in the previo us chapter in an effort to demonstrate the
capabi lities of the OrCAD/PSpice software through practical applications.
The last chapter of this book takes these procedures a step further and begins
to explore some of the more advanced feature s of the Cadence software
package.
Sample Circuits 11 -45

Chapter 12
Advanced Analysis
Until this final chapter, the text has focused mainly on carrying out
four basic simulation types on various circuit designs and interpreting the
simulation results from the Cadence Allegro AMS Simulator or PSpice ND
software. From a design standpoint, these simulation types are essential
to lay the proper groundwork for a given circuit, but it is important to
remember that any simu lation results yielded by these designs are based
on the behavior of an ideal PSpice model. The Transient Analysis, DC
Sweep, AC Sweep and Bias Point Calculation can characterize the general
behavior and functionality of a circuit, but they do not take into consideration
component tolerances, environmental factors (such as temperature), and
noise generated from real components.
The PSpice software has the capability to take all of these factors
into consideration and give you an idea of what you might expect from a
particular component choice and all of the possible ways it can impact the
performance of a circuit. These types of simulations fall into the realm of
what we will call Advanced Analysis (AA).
There are five types of AA simulations that will be discussed in this
chapter. They are Sensitivity Analysis, Monte Carlo Analysis, Smoke
Analysis, Noise Analysis and Temperature Analysis. The point must be
made that all of these simulation types are so immensely complex that each
one could have multiple chapters devoted to it. The purpose of this chapter
is to define their most primary functions and give the user some insight by
using the most basic examples.
Advanced Analysis Schematic Preparation

To learn how to carry out these types of simulation procedures, we will
refer to the BJT amplifier that we biased at the end of Chapter 7 with the
help of the Cadence software. But before we can explore these simulation
techniques, we will need to make some modifications to the design . The
Advanced Analysis 12-1

circuit has been redrawn in a new project and is shown in Figure 12.1.
In order to carry out some of the AA simulation procedures, we will
need to incorporate tolerance parameters into the design. This is quite simple
with a majority of the pass ive compo nents in the PSpi ce library, such as
resistors, capacitors and inductors . Active components with more complex
PSpi ce models require the placement of AA components. In the case of the
circuit shown in Figure 12.1, all the resistors and capacitors remain in place.
The 2N3904 will be rem oved and substituted with a 2N3904 equivalent
model from the AA PSpi ce library. To do this, click the PLACE PART button
in the OrCAD Cap ture or Allegro Des ign Entry workspace to expand the
PLACE PART menu to the right of the screen and click the button to add a
new Component library, ju st as if you were adding a new Component library
to a project. In the PSp ice libra ry folder you should see all of the familiar
libraries that you have been using thus far, but this folder also contains a
folder with the title ADVANLS (for Advanced Analysis). This folder contains
all of the AA libra ries (see Figure 12.2). Open this folder and you will see
all the AA libraries that are available to you . Add these libraries to your
project to utilize these compo nents in the OrCAD work space.
After adding these libraries to the open project, the AA 2N3904 can
be added into the existing schematic design. Figure 12.3 shows the AA
2N3904 selected in the part list. At this point , you may be wondering how
to designate betwe en a standard 2N39 04 model and the AA 2N3904. With
VCC
vcc
<;> 1 2
~VDC
20V _ R1 RC
-T 40k 4.7k
C1
~ C2 Q1
3
f."-- - - ----l f--
10u Out
~O
VOFF=OV
VAMPL = 250mV
FREQ = 1kHz
AC = 250mV
~
f VIN 10u
R2
3.5k
42N3904
~ RE
470
<
RLOAD
47k
~o
Figu re 12.1 - BJT amplifier circuit schematic.
12-2 Chapter 12
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Figure 12.2 - Advanced Analysis componen t libraries.
~ • x
.. _--- - _. . -- - - - -
2N3897ITHYRISTR ", i
2N3898ITHY1
2N3898ITHYRISTR
2fl38991THY1
2N38991THYRISTR
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2N390318 JN
~I
1
1l§li~~~!!~~!;tW~.":-
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h:OT •
74Af:.
I 74Af:.T •
Figure 12.3 - Advanced
Analysis 2N3904 selected in I74ALS
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Parts per Pkg
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the part selected in the part list, look for the AMS Simulator icon at the
bott om of the screen ju st to the right of the schematic symbol. As you
recall from Chapter 3, the presence of the AMS Simulator icon indicates
that the schematic symbol to be used in the Allegro Design Entry or OrCAD
Captu re circuit has a PSpice model. In the case of an AA component, the
AMS Simulator icon is overlaid with an uppercase P. This is seen with the
OP designation for the 2N3904 shown in Figure 12.3.
In Figure 12.4 this component has been substituted in place of the
standard 2N3904 from the original design. The schematic symbo l is virtually
identical to the original component. The differe nce lies in the mode l data
that will be used durin g the simulations.
At this point, the schematic design is set, and now tolerance parameters
need to be attached to the components within the circuit. AA simulations will
consider comp onent tolerances only if you declare them. If a user neglec ts
to declare a tolerance for a comp onent, the software will use the ideal model
for any simulation data. For the purposes of the examp les to be com pleted
in this chapter, tolerances will be assigned to the biasing resistors R1 and
R2, the collector resistor RC, the emitter resistor RE, and the beta factor of
the transistor. With these new parameters in place we will determine if any
variation in these tolerances (of R1, R2, RC, or RE) will affect the integrity
of the bias of this BJT circuit.
To begin, let' s assume that we would like this circuit to be constructed
using resistors with a 10% tolerance. To assign a tolerance to these resistors,
VCC
9
~VDC
20V _ R1
-T 40k
~
-=- 0 C2
~
I:IN 10u
VOFF =OV ~
VAMPL = 250mV
FREQ = 1kHz R2 < RLOAD
AC =250mV 3.5k 47k
Figure 12.4 - BJT amplifier schematic desi gn with AA 2N3904 model.
12-4 Chapter 12
select R1, R2, RC, and RE in the OrCAD Capture schematic capture window
and double -click on them to open the Property Editor. There is a column
within the Property Editor labeled TOLERANCE . Under this column, declare
the desired tolerance percentage for each compon ent. In Figure 12.5, the
10% tolerance has been declared for each of the four resistors.
After applying the changes, with the TOLERANCE column still selected,
you can click the DISPLAY button to label this parameter in the OrCAD
workspace. This has been done in Figure 12.6.
All<g'" ~ n EnbyCIS' IP~ d,""

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Figure 12.5 - PROPERTY EDITOR window displaying tolerances.
VCC
VCC <;>
9
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20V _ R1 RC
40k 4.7k
OLERANCE = 10%
C1
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"':-'
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OLERANCE = 10% f OLERANCE = 10%

R2
3.5k
RE
470
42N3904
RLOAD
47k
-=-0
Figure 12.6 - BJT amplifier schematic with labeled tolerances.

We have now declared tolerances for each resistor. The last step will
be to declare a tolerance for the beta factor of the transistor. To do this,
right-click on the transistor and select EDIT PSPICE MODEL to open Model
Editor (see Figure 12.7).
When using Mode l Editor with the standard PSpice components
in previous chapters, you might recall that Model Editor would dictate
component characteristics in a text format. All of the alterations made
to the examples in Chapters 10 and 11 strongly resembled a text editor
window. With the AA components, the model data opens into an interactive
spreadsheet. This is shown in Figure 12.8.
Notice in the MODEL EDITOR window the presence of two columns,
POSTal and NEGTOL. The se columns indicate the percentage tolerance that
the beta factor can sway in the positive and negative direction, respectively,
from the defined beta value . In Figure 12.8 it has been declared that the
Mirror Horizo nta lly

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Figure 12.7 - Opening Model Editor for an AA component.
12-6 Chapter 12
~. bitAoUWb2n3904 - AMS Model EdROf- Sirnullhon Pat'Ml"eh~f . '~
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Figure 12.8 - MODEL EDITOR window dis playi ng AA 2N3904 model data.
tolerance of the transistor can deviate 20% in the positive direction and
20 % in the negative direction. The 2N3904 transi stor model has a beta
value defined at 254.395. With these tolerances in place, an AA can predict
variations in the behavior of this amplifier circuit with arbitrary beta
values that fall within the range of 203.516 to 305 .274 . It can be noted
that these POSTOl and NEGTOl columns are modifiable for all component
parameters. In this example, a tolerance has been assigned only to the beta
factor. In actuality, the results of an AA simulation would be more closely
representative of a real component if one were to assign tolerances to more
of these model parameters.

Review of Ideal Circuit Behavior
Our schematic has been fully prepared and can now undergo the AA
simulations. Before we do so, it is important to determine the general behavior
of the circuit with the declared values. This will establish a baseline to help
interpret any data that will be obtained from future AA simulations. A Bias
Point Calculation, Transient Analysis, and AC Sweep will be conducted.
These basic simulations will not take the declared component tolerances
into consideration. Figure 12.9 shows a Bias Point Calculation with all of
the node voltages labeled.
Next we will set up a simulation profile for a Transient Analysis. The
sinusoidal voltage source VIN is operating at 1 kHz. A run time has been set
at 1 ms to display one cycle of the output waveform, and a step size has been
set at 1 us. These simulation settings are shown in Figure 12.10 .
Figure 12.11 shows a BJT class A amplifier. With a 250 mV input signal
applied to the input, an output voltage of approximately 2.167 V is measured
across the load resistor. It is important to remember that this voltage is
measured across the load resistor. We have not associated a tolerance with
this load resistor, but for all the sample simulations in this chapter we will
assume that the load is ideal and fixed at 47 kQ. To compensate for this, an
additional marker has been placed on the other side of the coupling capacitor
on node 3, the output of this amplifier at the collector terminal, and the trace
VCC
?J ··
~VDC 2
20V _ TOLERANCE= 10%
R1 RC
40k 4.7k
:r
OLERANCE= 10%
3
-=-0 C2
v
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IN 4 2N3904;,.,_...
VOFF = OV :--
VAMPL = 250mV
FREQ= 1kHz
OLERANCE = 10%
R2
f~·~·~·~;~CE :
RE
10%
RLOAD
AC=250mV 3.5k 470 47k
Figure12.9 - Bias Point Calculationresults, voltage.
12-8 Chapter 12
has been added to the plot shown in Figure 12.12 .
Obviously, the same gain can be observed in both waveforms. The key
difference is the de offset seen with the trace of the node 3. Referring to
the Bias Point Calculation, this voltage is determined to be 10.93 V. During
the AA simulations, using node 3 as a reference point, we will assess the
Simulation Setti ngs - Transient
Run to time: -,;:;;;--!seconds (T5TOPI

ITme Dornao1 cr- 1· 1
Start saving dala efter: 0 : seconds
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--- ---..- . . . ._-
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EJ Parametric Sweep
EJ T~lXe (Sweep)
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EJ Save 01ed< Pons
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Figure 12.10 - SIMULATION SETTINGS window, Transient Analysis.
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Figure 12.11 - AMS Simulator window plotting load voltage with respect to time .

stability of the bias of the BJT amplifier as component values fluctuate due
to tolerances.
Lastly, an AC Ana lysis is performed on the circuit to determine the
frequency response of this BJT amplifier. The simulation parameters can be
seen Figure 12.13 . The sweep begin s at 10 Hz and ends at 100 MHz with
100 data points per decade plotted along a logarithmic axis.
The load voltage is measured during this frequency sweep and is shown
in the plot of Figure 12.14. A data point has been marked to again verify
voltage gain.
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Figure 12.12 - AMS Simulator window plotting load voltage and node 3 voltage with respect to time.
Simulation ~tti ngs • AC Figure 12.13-

SIMULATION SETTING S
window, AC Analysis.
AC Sweep Type
~I CO Linear Start Frequency. 10Hz
Options : ~, Logarithmic End Frequency: 100MegHz

;f IDec ode ~I Poinls/Decade: 1100 • J
EJ MorteCalo lWoot Case
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12·10 Chapter 12
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Figure 12.14 - AMSSimulatorwindow,frequency responseplot.
Sensitivity Analysis
The first simulation type to be discussed is the Sensitivity Analysis. The
Sensitivity Analysis will carry out a series of runs on a circuit while varying the
values of components within their declared tolerance ranges. (Note that in the
Lite - demo - version of the software there are limitation s on the number of
runs that can be used. You may need to set the number of runs to a value lower
than that used in the example s in this chapter.) Let's begin by opening the AA
window. To do this, select ADVANCED ANALYSIS, then SENSITIVITY under the
PSpice drop-down menu. This is shown in Figure 12.15.
This opens the AMS ADVANCED ANALYSIS window (see Figure 12.16).
Mo st of the Sensitivity Analysis simulations discussed in thi s chapter
utilize this window. You will immediately notice that the drop-down menu
at the top of the screen reads SENSITIVITY. In the OrCAD window, had
the user selected Monte Carlo, or Smoke, this same window would have
opened; however, the user interface would look slightly different based on
the selected simulation type . Also, it is important to note that all of the
parameterized components are listed in the upper portion of the window.
The lower portion of the window is devoted to measurements and project
specifications.

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Figure 12.15 - Opening PSpice Advanced Analysis, Sensitivity.
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Figure 12.16 - AMS ADVANCED ANALYSIS win dow, Sensitivity.
12-12 Chapter 12
First, we will demonstrate how to declare a measurement; then we will
discuss how this measurement is relevant to the Sensitivity Analy sis, what
the Sensitivity Analy sis is, and its applications. Earlier, it was stated that
we will be using the voltage at node 3 as a reference and would monitor
the stability of the bias as component values varied . Therefore, for our
Sen sitivity Analysis, we use the same measurement V(3), the voltage at
node 3, that was seen in the Bias Point Calculation and used as a trace
measurement for the Transient Analy sis and AC Sweep .
To add this V(3) measurement to the Sensiti vity Analysis window, select
CREATE NEW MEASUREMENT under SENSITIV ITY under the ANALYSIS drop-
down menu . This is shown in Figure 12.17.
The EDIT MEASU REM ENT window (see Figure 12.18) bears a
remarkable resemblance to the ADD TRACE window in the AMS Simulator
software . In the top left corner of the window, there is a PROFILE drop-down
menu. Earlier in the chapter, three simulations were carried out on the BIT
amplifier - a Transient Analysi s (Simulation Profile Title, transient.sim),
AC Sweep (Simulation Profile Title, ac.sim), and a Bias Point Calculation.
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Figure 12.17 - Creating a new reference measureme nt.
~=======""J- NUt.!

,.... . -* - -\~} ..
Edit Measurement .
~--- -- - ~ - ~ - -- .
Profile: [ transient. sim
Simulation Output Variables Functions or Macros

I [ Measurements ... 1
I(Cl) ... ~ Voltages Bandwidth(l ,dbJevel)

I(C2)
I(Ql :B) n ~ Currents
Bandwidth_Bandpass_3dB(1)
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I(Rl) ConversionG ain(l ,2J
50 items
I[R2) ConversionG ain XRenqell ,2,bec -
I (~C) ... Full List • III ~
Measurement:
OK
Figure 12.18 - EDIT MEASUREMENT window.
These profiles exist in this drop-down menu. Transient.sim has been selected
in Figure 12.18. With the transient simulation profile selected, all of the
available measurements (V, I, and W) that existed in the ADD TRACE window
are now visible in the column browser of the EDIT MEASUREMENT window.
The measurement V(3) can either be found and selected in the column
browser, or it can be entered manuall y into the measurement text box. Click
OK to add this measurem ent. The measurem ent text box can also be used
in conjunction with the functions and analog operators at the right of the
EDIT MEASUR EMENT window to perform any measuremen t imaginable to
evaluate a circuit' s performance. You also may have noticed the IMPORT
MEASUR EMENT feature under the analysis menu shown in Figure 12.17.
This method allows you to directly import a trace function saved from an
earlier simulation. This can be especially handy if you are dealing with a
complicated funct ion from the AMS Simulator and simply want to carry that
function over into the AMS ADVANCED ANALYSIS window.
Now that our measurement is in place , we must define the purpose
of the Sen siti vity Analys is. The Sen siti vity Analys is will dete rmine
which components of a design have values that are the most critical to the
performance of the circuit. In other words, if each component value is varied
within its tolerance range, which will yield the most significant change in
the reference measurement declared in the EDIT MEASUR EMENT window.
12-14 Chapter 12
Remember, the BIT amplifier has four resistors with tolerances and the
transistor itself has a tolerance for its beta factor. The Sensitivity Analysis
will determine this and can present the data in a variety of ways.
The two types of sensitivity results that will be presented in this chapter
are Absolute Sensitivity and Relative Sensitivity. The easiest way to define
each interpretation of the data is to also offer a series of examples, as follows:
• Absolute Sensitivity - A ratio that illustrates the amount of change
in a measured value due to an incremental change in a component value
Example - If there is a 1 n change in resistance, there will be a
0.7 V change in output voltage .
• Relative Sensitivity - The percent change seen in a measured value
if a component value is varied by 1%.
Example - If there is a I % change in resistance, there will be a 4%
change in output power.
With the measurement in place, to run the Sensitivity Analysis, click
the RUN button at the center of the toolbar at the top of the screen. The
results of the Absolute Sensitivity Analysis are shown in Figure 12.19.
SCHEMATlCl - AMS Adv.nerd A",~ - ~tMty

a f ile :Edit ¥Jew Bun Analym Window !:id p cadence 0 '" x
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e
U - -------- -- --- --- --- Secnsitivityanalysis com plleted ----- ---------------
For Hdp. pressf1 NUt.!

--
Figure 12.19 - AMS ADVANCED ANALYSIS window, Absolute Sensitivity results.

Referring to our definition of the Absolute Sensitivity, we know that these
results are a funct ion of the simulation software adjusting resistances and
the beta factor in incremental values and determining the change in the
measurement that was set as V(3), the voltage at node 3. After running the
simulation, the maximum and minimum calculated component values will
appear in the columns in the upper half of the window along with a bar graph
representing the ratio of the change in voltage with respect to the change in
a component's parameter.
Based on these results, it can be concluded that an incremental change
in the resistance of RE, the emitter resistance, will yield the most significant
change in the voltage at node 3. Thi s ratio stands out far beyond the rest
of the components being evaluated , the next being R2 with a ratio of 21, in
com parison to 98. At the other end of the spectrum, it can be noted that an
incremental change in R1, or the beta value of the tran sistor, will yield a
minimal change in voltage at node 3.
Afte r clicking RUN, the PSp ice or Allegro AMS Advanced Analysis
Simulator will perform sensitivity run s on each of the parameterized
components in the circuit. The se runs produce the bar graph seen at the
top of the screen. These sensitivity runs are followed by what are called
worst-case run s. Worst-ca se runs determine the greatest changes in the
user-defined measurements (in this case, V(3) and calculate maximum and
minimum values. The bottom half of the screen display s the measurement
V(3). To the right of this measurement there are three data columns. The
first column is the original value ( 1O.9297V ) of voltage at node 3, calculated
using the exact component values. This is the same value of voltage that
was seen earlier in the chapter with the Bias Point Calculation and in the de
offset of the Tran sient Analysis. The next two columns, MIN and MAX, show
the largest possible deviation from the measured value that could possibly
occur with components values being at the limits of their tolerance. In this
example, component tolerances could potentially yield a minimum voltage
of 5.7634 V and a maximum voltage of 14.5216 V at node 3.
Right-click on the bar graph and select RELATIVE SE NSIT IVITY . The
bar graph and columns will change to dep ict the results of the Relative
Sen sitivity Anal ysis. Thes e results can be seen in Figure 12.20. Remember,
the key difference between Absolute and Relative Sensitivity Analysis is
that Relative is based on a percentage change in a component's parameter,
as opposed to an incremental value. When each component varies a single
percentage within its tolerance range, R2 and R1 seem to have the greatest
impact toward the change in V(3) . This could be because a percen tage change
in a large resistor like R1 accounts for a significant change in resistance.
When varying the values of R1 and R2, the voltage divider that is biasing
12-16 Chapter 12
SCHEMATIC! • AMS Advanced Ana is - sibvityJ _ ~ _~ ~ . ' I--=- ~ ~ l<__,
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250' 21• .. ; 234 .. f'OBOm 1
·
• V
. 0nI0!f
i"
I Profile
tranunt.sm
I U eas u rement
V(3-)
-
to 9291
'I..
~!~bonl
5.1034
Max
1452 f6
~ .... , - . <0<.<
·
Son_ 1j;l """. Cario I ·

E3
4 Sensitivity run; 4 of 5 co m plet ed .
Sensitivity run: 5 of 5 com pleted
w crst case ru ns u nderway .....
Minimum run; 1 of 1 cc mp reeed
-
M;»:imu m run: 1 of 1 co m pleted
Runs for sim ulation profile transient.sim co m pleted
---- -- ----- --------- Sensitivity analysis c omplet~ ---- - -- --- --- -- -- - --
~
for t-klp, pres s F1 NUM
Figure 12.20 - AMS ADVANCED ANALYSIS window, Relative Sensit ivity results.
this common emitte r configuration is directly affected as well. That would

have a significant impact on the behavior of the circuit and could certainly
have an impact on the voltage measurement at node 3.
When comp aring the results of the Relative Sensitivity Analysis to
the Absolute Sensitivity Analysis, it makes perfect sense that the smaller
resistor values, RE and R2, would have the highest ratios of change in V(3).
This is because a I D. variation in the resistance of a smaller resistor like RE
or R2 accounts for a larger percent age of change in resistance in comparison
to a I D. shift for a larger resistor like R1. One last note on the Sensitivity
Analysis is that results can also be presented in a logarithmic scale. With
either the Absolute or Relative results displayed , simply right-click on the
graph and select the logarithmic option.

Monte Carlo Analysis
Next we will move on to the Monte Carlo Analysis. The Monte Carlo
Analysis predicts the statistical probability that a certain measurement will
be achieved throughout a set number of runs (simulations) where each run
will have random component values within their respective tolerance ranges .
To begin, expand the drop -down menu at the top of the screen that currently
reads SENSIT IVITY and change it to MONTE CARLO. The AMS ADVANCED
ANALYSIS window will change and look similar to what is shown in
Figure 12.21.
Before we go any further, we need to create a measurement for reference.
We will use the same reference point and type of measurement as was
used for the Sensitivity Analysis in the previous example - the voltage at
node 3. Add this measurement with the same procedure used for the
Sensitivity Analysi s. Open the EDIT MEASUREMENT window by selecting
CREATE NEW MEASUREMENT under MONTE CARLO in the ANALYSIS drop-
down menu. The very same EDIT MEASUREMENT window will appear,
except this time you will be adding the V(3) measurement to the MONT E
CARLO window. This is shown in Figure 12.22 .
Next we will modify some of the parameters . Under the EDIT menu select
the PROFILE SETTINGS option . When the window opens, select the MONTE
CARLO tab to display a window similar to the one shown in Figure 12.23.
'5tK .....nn · ~ Ado--..d l'4' e..to: • • • • - - "1;",' ~

S r. ttllt v- """ ~ w".,.", .... cadence ~ • •
Pr obebilily DenMy Gf_ph (RlIIIl; 1 to 100)
'~~~F1TTT i] ' r i T : i i iTTi [ ;',Tii TTT'i -r-, rl"j-rrrTri j TTT;-j : TTli r: : ~1

OOIn 006 01 0 14 01 ' 0 22 O~ 0) 034 OJf: 0 .(2 04 5 05 05.1 osa 0 &2 0" or 0 11 0 11 012 on 09 ow 0. 11 02
--...- c__ ... c....- ---

lido....
0010 . . . . ........
] SqN lSoglM
._".....
».-
Figure 12.21 - A MS ADVANCED ANA LYSIS window, Monte Carlo.
12-18 Chapter 12
/'_..,....;.... .o;;<ro:"'.' ,," .,,~.~ •..:.
Edit Measurement ,~
" "-'UJ
Profile: [ transient.sim ~I
. Simulation Output Variables Functions or Macros-
I I [ Measurements
I(C1) .. lfl] Voltages Bandwidth(1 ,dbJevel) ..

I(C2)
I(01:B) o ~ Currents I Bandwidth_Bandpass_3dB(1 ) n
Bandwidth_B andpass_3dB_XRalLl
1(01 :C) ~ Power CenterFrequency(1 , dbJevel)
1(01:E) CenterFrequency_XRange[1 , db_
I(R1 ) ConversionGain[1,2)
I(R2)
50 items ConversionGain XRanqe[1,2,bec ...
I[RC) ... Full List .. I III ,I ~
Measurement:
t
n ---------------'
Cancel 1[ HeiR
Figure 12.22 - EDIT MEASUREMENT window.
Profile Setting,
- --
l'Urber d Pu1s: 100
RandomSeed V...,: -1- -.
l'Urber d Bins:
OK II c..nc.I II Reset II Hot>
Figure 12.23 - PROFILE SETTINGS window, Monte Carlo.

We will increase NUMBER OF RUNS to 100. This means that the circuit will
be simulated 100 times, each time with different component values . (Note
that the "Lite" version of the software is limited to fewer runs.) Also increa se
NUMB ER OF BINS to 20. The Mont e Carlo Analysis will present the results of
these calculations using a histogram. The bin number means that the range of
V(3), plotted along the X axis, will be subdivided into 20 equal region s. Each
bin will be repre sented by a single bar in the histogram . The Y axis can plot
either the number of runs or the percentage of runs, depending on how the
user decides to configure the plot. The default setting will plot the number of
runs on the Y axis. Th is can be changed by simply right-clicking the Y axis
and selecting the alternative.
Click the RUN button to begin the simulation. The number of runs and
the complexity of the schematic design can have a significant impact on the
time that it takes to complete the simulation, so it may take a few moments.
What is happening during each run is a random selection of component
values. The simulation software performs a Small Signal Bias Solution
and ext racts only the relevant data. In thi s case , the relevant data is the
mea surement that was ju st created - the calculated voltage at node 3. That
calculated data falls into one regionlbin of the X axis , and after all of the
run s are complete, the collective run data is calculated and plotted in each
region of the histogram. Th is type of graph is referred to as a Probability
Density Function graph, often abbreviated as PDF.
The results of the simulation are shown below in Figure 12.24. A total
of 100 runs were completed. According to the PDF graph, 12 of the runs
with randomized components produced circuits that would achieve a voltage
ranging from 9.82 V to 10.10 V. The greatest probability falls within this
region. With random component values, the circuit s tested produced a range
of V(3) at a minimum of 8.1 V and a maximum of 13.74 V. This type of
simulation can be an especiall y important tool that may be used during the
manufacturing proce ss. When fabricat ing a real circuit and using components
with the tolerances defined in this design , it would be beneficial to have a
prediction of how many circuits would meet a certain specification. Depending
on the resu lts of the PDF plot, an engineer might want to further refine the
tolerance of certain components in a design to produce more circuits within
a set of random runs that would meet a particular specification.
The Monte Carlo Analysis results can be viewed using a different
interpretation of the data . The plot shown in Figure 12.24 is a Probability
Distribution Graph and is the default output of the Monte Carlo Analysis .
Righ t-click on the graph and select CDF GRAPH. CDF stands for Cumulative
Distribution Function, and from a mathematical standpoint, this graph is
nothing more than the integral of the PDF.
This graph is shown in Figure 12.25. To further expand upon this
12-20 Chapter 12
Figure
12.24-AMS cadence - if x
ADVANCED
ANALYSIS
window,
Probobil ity Donsity G~pIIIRuns: 1 to 100)
Monte Carlo
PDF.
:..~ ,:I:·T,LrrLfIILI ',:Er:I::;:rfTfFlj,:EFrrI:I:fJ

···~· · · i· · ·i·· · t·· ·;· · ·i·· . . . " '~" '~"'j" '~" ' i'
2 "-;--'t '· T- - : "' ~"'T
o I I
1.5 77 19 8 1 8 3 8.5 e7 ss " 93 95 91 99 101 10,~ 109 12.' 12~ izs 133 131
VOl
. I-
......
MordeCldorvn t$;(~td
Monte CIdQ1'\Il"l96 c~td
Mon(t C~ run J1 tomplttfod
-
Monu· CM'to Nn M c-.pkted
Montt C.do Nl'l 9:licom,ltted
MonteCMk>Ntl lD:lc~otd
MonttCMfo .~s(~td.
,....
Figure
cadence _ " x
12.25- AMS
ADVANCED
ANALYSIS
window, Cumulativ e Disttibution Gnlph (Runs: 1 to 100)
Monte Carlo
1"~ ]""'" t+" i~": " j''~; '+"" i!': "'i:"' i;"'i":' ':!:
:i' 7f'+'f";"'
' :' :' ' t:' ',:"""""'
CDF.
so +'+-'H" 'i +'1" '~ '.; . : ;":''':'++';''':''+'+'~''j'''~'+'1''+
."s. t ,m"!:" '!:",,""-nti
,'";"""'j:"''"
:j '-!' """' :i' " :""",
, ,n,.,..':t tmtt !:' "',:"'1
t t:""''n:t
~ . : :t:l:t::[l:# RfHr!" l::r: [ :rl:: :! ::FI::+ ::r:rl+r~+Tt: : rr:f::Fl
7,5 7.7 a, 8.5 as 9.3 91 99 10.3 10.7 11 1 11.5 11.9 12 3 12.7 13.' 13.5 13.9 14.3 14.7
VOl
I
CJd l"><tfl! lO ~ " lM UIlf' lIItnI Ctf.tIN Vt lllitt PS;ict
+--1-,
1- ..
.r--l -+ F1. I
1-
1-
I
I
I .. oj 9 , I~===::j~==!
-j --
-
1- -'... ~

definition, we can examine a few data points and determine exactly what
they mean. The X axis of this graph rema ins V(3), and the Y axis is still set
as the number of runs. Let's pick a point on the X axis that was referenced
while talking about the PDF plot - 10.1 V. Looking at the CDF graph, and
using the cursor, this point corresponds with 34 runs on the Y axis. This
data is interpreted as 34 out of 100 runs of yielded voltage measurements at
node 3 that were 10.1 V or less. Now we can refer to Figure 12.24, the PDF
graph. Starting at the bin with the upper boundary of 10.1 V and descending,
the total sum of the quantities of each bin is equal to 34. Looking to the left
and right boundaries of the CDF plot, the maximum and minimum values
corre spond with the outer regions of the maximum and minimum bins of
the PDF plot.
Temperature Analysis
The next type of simulation , the Temperature Sweep, technically is not
considered an AA simulation method in the most recent version of Cadence,
but it is slightly more complex than the standard simu lation procedures.
We know that electrical components will exhibit different behavior
under different temperature conditions, and PSpice will simulate all circuits
at a default value of 27 °C. This default setting can be changed under the
OPTIO NS tab in the SIMULATION SETIINGS window (see Figure 12.26) . This
poses a question as to whether it is possible to observe how a measurement
will change as the environmental temperature varies . This can be studied
: Simulation Settings - Temp
G<neroI I ~ I Conf9.raticn Res j ()pt;ons IDola CoIedJon I Probe Wndow I

[alegay: __ (.OPTlON)
ip""rt'T2!9 Reletive eccuecy olv's endl's: 0.001 (RELTOL)
~ ~ Best accuracy 01 yoltages: ~ voks (VNTOL)
Best accuracy of cy nents: ~ amps (ABSTOL)
Best accuracy01cbarges: ~ coulombs (CHGTOL)
Minimum conductance for any,branch: 1.0E-12 1/ohm (GMIN)
DCand bies "blind" jterationlimit: 150 (1TL1 )
- -
DC and bias "best guess" , eratioo)imit: 20 (ITL2)
l ramient timepoint iteration6mit 10 (ITL4)
Defauknominaltemperature: 27.0 ·C (TNOMj
EJ Use §.MIN stepping 10improve convergence. (STEPGMIN)

EJ Use QreOfdering to reduce matrix fill-in (PREOROERj
I OK " Qn:<i II !Wt 11 f!o:rP I

Figu re 12 .26 - SIMULATION SETIINGS window, Options tab.
12-22 Chapter 12
through a variation of the DC Sweep simulation type. As you may recall
from Chapter 3 and our discussion of a particular component's element line,
there exists a temperature coefficient that dictates change in a component 's
parameter as the temperature of the environment changes.
Before going any further, we must make sense of this temperature
coefficient. The temperature coefficient (TC) reads from the element line
as follows:
TC =TC 1, TC2
Example: Default Value, TC = 0, 0
Recall that the default temperature of any simulation is at the nominal
default of 27 °C. The ma thematical formula that interprets this temperature
coefficient is given as:
R Emv-r-iemp = R Nom-r-i emp [1 + TCl (EnvTemp - NomTemp) + TC2 (EnvTemp

- Norn'Iempj']
where
NomTemp = Nominal Temperature
EnvTemp = Environmental Temperature
For example, assume there is a res istor wi th a val ue of 350 n
in the nominal temperature of 27 °C with a temperature coefficient of
TC = - 0.004, O. Us ing the formu la given above, if the environmental
temperature were 127 °C, the resi stance would be 2 10 n.
If the temperature coefficient is not modified, the resis tance will remain
fixed throughout a Temperature Sweep simulation. It can also be noted that
Simulation Srlting, . Trmp ~. ~
~~, I ~ Re. 1~ I DalaColedicn I Probe Wndcw !
!'naIysis1)Ile :
loc Sweep
0p00ns:
~I
Sweep variable
e> VoUage source
e> Currentsource
() Global parameter
Name
Moriettj'fl~
L __=-__. .J
~. '"-. o Model parameter M o(j'~l n"rlll?' I

EJ SecondarySweep
o Moo-te CatIoiWorst Case
~) Temperature p ar ail'.~~~1 n-:301'!:'" I - --
EJ Param<tric Sweep
EJ T~..., (Sweep ) Sweep type
---
o Save Ilia, Pori l*) Linear
Start value: 20
- ---
EJ Load Ilia, Port r: -' ,._-- .... End value: 37
() Logarithmic lE'.<~d:_ __ :J
Inclement: .2
e> Value list I
I OK II Cancel I ~; 1 ~ I
Figure 12.27 - SIMULATION SETIINGS window,Temperature Sweep.

standard transistors and AA transistors may have temperature characteri stics
associated with their default model s. We will illustrate this in the following
example.
To sweep the temperature of a circuit, return to the DreAD window
and create a new DC Sweep simulation profile. As shown in Figure 12.27,
select TEMPERATURE as the sweep variable. At the bottom of the window,
declare the sweep parameters as you would with a typical DC Sweep. For
this example, a sweep will take place with a starting temperature of 20 °C
that ends at 37 °C with incremental data points every 0.2 degrees. Apply
these simulation parameters and run the simulation.
Like the AA simulations done in earlier examples, add a trace for the
measurement of the voltage at node 3. This will plot a change in the node
voltage with respect to temperature as a result of the temperature parameters
of the AA 2N3904 transistor model. Figure 12.28 shows linear function of
the transistor's temp erature parameter. At 20 °C, the voltage at node 3 is
approximately 10.98 V. Continuing across the X axis, at the temperature
27 °C we see the voltage at the nominal temperature bias is 10.93 V. This
is the same voltage that was seen in the Transient Analysis simulation and
the Bias Point Calculation. Then at the far end of the sweep, at 37 °C, the
voltage continues its linear decrease to slightly less than 10.86 V. This trend
will continue. If the temperature continues to fall, the voltage at node 3 will
also continue to fall.
H 11 OOU
o
;
d • •• .. ··· f·· ·'·· · ··' f· ··' ·· " O_' -.-, _._, , _. - , " , , , "-..,, · ·· ..··· t···r··· """' ,"' ,'"
~g::::::::::::+: T::: ::;

1 1 0. 95U • •. : : :
• ••. • ••••.••
t
; ••=.•••••••••••••• •••••••••• •••;•• :•••.••• ~~2~··:· ··· ~· · ·· · · · ~

10 .90U : :~
10 .85U
...,
:: ::: :::::iiiiii::rtiii::: '"1''':''':''' , , , ·..,..···..·.. ·N .. · ~ ..·
20 22 24 26 28 30 32 34 36 38
a U( 3 )
TEllP
Figure 12.28 - AMs Simulator window,Temperature Sweep.
12-24 Chapter 12
Noise Analysis
The next type of simulation also is not considered an AA simulation
method in the most recent version of Cadence, but is extremely important
and will be able to help us assess the effectiveness of a design and ensure that
this design will produce a quality output. This simulation method is Noise
Analysis, and it expands upon a basic AC Sweep simulation. Return to the
DreAD window and create a new simulation profile for an AC Sweep. In the
SIMULATION SETT INGS window, set the sweep to start at 10Hz and continue
to 100 MHz with a logarithmic scale and 100 data points per decade (see
Figure 12.29). In the bottom half of this window, check the box to enable
the NOISE ANALYSIS. The first text box in this region declares the voltage
output of the circuit. The net alias for the node above the load resistor in the
amplifier has been labeled "Out", so in this text box , simply enter "V(Out)."
The next text box declares the reference name for the voltage or current
source supplying the input signal. This feature makes this simulation type
incredibly versatile when considering the fact that certain circuits require more
than one analog voltage or current source. Take a differential amplifier for
example. If this differential amplifier has two inputs, two separate simulations
can be carried out to determine the amount of noise contributed at each input.
The reference name for the VSIN source for this circuit is "VIN".
Lastly, the user must enter an interval. The interval parameter can be
thought of as similar to the way the user defined the resolution of a Transient
Simulation Settings
I~J Analysis I~ Reo I~. IOala Coledion IProbeWKWJow I

Analysi, type: ACSweep Type
IfoeSweep lNoise 3 0 Linear SlartFrequency: 10Hz
0pt10ns: ~} Logarithmic End Frequency: 100MegHz

IDecade ~ I Poinl,/D ecede: 100
EJ Morte CarloiWoot Case
o Paramelric Sweep NoiseAnalysis
o Temperature (Sweep )
o Save Bas Pon III Enabled OulpulVoltage: VIOul)
o Load Bia, Poot IN Source: VIN
Interval: .01
outputFile 0 ptions
o Include detailed biaspoint information far nonlinear
controlledsourcesand semiconductors (.OPl
OK II e-:el I [-~ ~]
Figure 12.29 - SIMULATION SETTINGS window, AC Sweep/Noise Analysis.

Analysi s with the step size. An interval of 0.1 would produce a plot with a
very high resolution , as a noise data point would be plotted at every 0.1 Hz.
All of these parameters have been entered into the simulation profile and
are shown in Figure 12.29.
Run the simulation and once the AMS Simu lator window appears, enter
the traces:
-: V(INOISE) " - Trace name for input noise voltage
"- V(ONOISE )" - Trace name for output noise voltage
These traces will be plotted along the X axis within the range declared
in the AC Sweep settings. This output is shown in Figure 12.30.
It is easier to interpret these results in decibels (dB), as noise is typically
expressed in terms of dB when discussing a circuit. This can be achieved
using the analog operator s and functions availabl e in the ADD TRACE
window. Double -click on each of them to modify the trace names. Adding
the DBO trace function to each measurement will perform a dB calculation
on both the input noise voltage and output noise voltage . This is shown in
the ADD TRACES window shown in Figure 12.31. This changes the Y axis
of the plot to a dB scale, as shown in Figure 12.32.
cade nce - " x
---i······--_· : j--_. _-_..• ·· ·.· ----i·.·· ·· ···· : -.. - :----.... .. ---.- ~ _ .

·-:::::::f:::::::::: :::::::::1:::::::::: :::::::::):::::::::: :::::::::j:::::::::: :::::::::~~::::: :: ::J: :::::::::f:::::::::: :::::::::f::::::::::
........: : : : -; : ; .
.. . .. ., .. .. .
:~ : :~ f ~ ~ ~: :~ :~ ~ ~ ~f~: : ~ ~: ~ ~: :~ ~ : :::L: ~ ~ ~ ~ ~ ~~~ ~~I~~~ ~ ~~ : ~ ~ ~ ~ ~ ~ ~ T~~: ~ ~ :~ : :~~~F~ ~ ~ ~ ~: ~: ~ ~ ~~+:~~~~~~ ~
U nU
·········i·········· ·········i·.········ ..·······i·········· ~ ; _- ; _- - ; .
········i·········· j••••.••..•..•• ...••{.••..••.••. .••••••• ~ .•••••..-- ...••.••••.;--... •..•• ••..•-•..:.••.•••.--- .-.••••.-; ------ -•••
.....-: _-..:. ~ .
..
_ ----. _ '_ - ; -- :
.........: : __.; ; ;- : ;.......•..
11Hz 1I ..z 1 • • Hz 1. "2 lOC*Nz 1.ltItz 1etlfz 111t11z
" U( DHUIU ) • U(l HOISE )
Fn quf'nc!.j
Figure 12.30 - AMs Simulator window plott ing input and output noise voltage with respect to frequency.
12-26 Chapter 12
---- - - - --
I~-~
--- -~ ~-
SIDJotion OllpU v..."... functiono 01 Macro:

I~ OP'"a1Ol'ondFunctiono ·1
Fr~ U
~ 6nolOll ~
Vll}
9
Vl3}
~~l
O llioJaI
;, ~~.
. {]
I I
VlOIIOISE} Q(t erb @
VIOlA} AllSlJ
V\VCC) ARCTANl)
V\VIN:'1 eo- ATANlJ
Noj:er.-Ill: ) AVGlJ
AVGlq .J
AM.!!..... ~~(J
:
O ~..t>aCUII llodn
EfIIII,lA)q .J
EINMIN(. J
E>cJ'l1
GlJ
IMGlJ
LOGII
1 0 v~ b(ed LO G1 ~ 1
Mil
MAXlI .
FlAI Li:t
I raceE"I'feuion:jD8M1NOISElJ
. - - 1 []D 1 ~1 ~
Figure 12.31 - ADDTRACES window, dB t race function.
-.
H -1 4 5
0
i
s
e Output Noise dB
- 150
\
---
-.
d lJ
B --.....
- 15 5
- 16 0
\
-16 5
- 17 0
~
1 0Hz 100llz 1 .OKHz
Input Noise dB
-,
10KHz 100K llz 1 .011l1z 10 1lliz
/'
100UHz
e OB(U(OHOI SE» • OB(U( IHOI SE»
F r e qu ~ ncy
Figure 12.32 - AMS Simulator window plotting noise voltage in dB with respec t to frequency.

It would also be easier to put these values into perspective if these
traces were plotted alongside the results of the AC Sweep. When the noise
sim ulation runs, an AC Swee p is also carried out. To view these results,
simply add a second plot to the window and add a trace plotti ng V(Out).
This is shown in Figure 12.33. Looking at the X axis, starting at 10 Hz and
moving right, as the outp ut acros s RLOAD rises to its maximum value, the
output noise drops to approximately -152 dB and the input to -170 dB. As
the frequency increases , approaching approximately 10 MHz, the output
voltage begins to roll off from its marked 2.1675 V peak value, as does the
output noise . During the roll off of the output voltage a slight increase in the
input noise is observed where the input noise nears approximately - 167 dB.
Even though this simulation is not considered an AA , it can be an
important tool in assessment of a design and can be used in conjunction
with AA simulations. Earlier, it was mentioned that it is possible to import
measurements from the AMS Simu lato r to the AA simu lation windows
to be used to evaluate desig n performance. The traces DB(V(INOISE)) and
DB(V(ONOISE)) can be imported into Sensitivity Analy sis simulations or
Monte Carlo simulations to determine how parameterized components
can impact input and output noise, and to predict the probability of noise
occurrence over a number of runs.
V 3.0V
0
I (10 000K,2 .1675) \
Volt;Jge Acr es RLOAO ___
I
a 2.DV
9
• ~~
1.0V
SEL»
-.
OV
a V (OUI)
H -1~ 0
0
i
s
e - 15 0
<, PUlpUI Noise dB
~
d
8
- 160
""'---.
- 170
10HZ 1 00Hz
a 08( U( OHOlSEJ) • OB( U( lHOI SE»
Inpul NOise dB ,
1. 0KHz 10KHz
Ft"equfoncy
100K Hz 1.0I111 z 101111z
----
100 11llz
Figure 12.33 - AMs Simulato r window, noise plot.
12-28 Chapter 12
Smoke Analysis
For the last simulation type to be discus sed in this chapter, return to
the ADVANCED ANALYSIS window. In this example we will perform a Smoke
Ana lysis on the BJT amplifier design . The Smoke Anal ysis will evaluate
the stress on all the components in a circuit due to power dissipation,
temperature, excessive curr ent, or voltage. To begin , open the drop -down
menu in the toolbar at the top of the windo w and select SMO KE. The window
shown should resemble that shown in Figure 12.34.
To perform these assessments, the Cadence soft ware utili zes
manufacturer operating conditions (MOCs) and derating factors . These two
factor s are used to determine whether all the components of a circuit will
operate under safe operating limit s.
Before running the Smoke Analysis, it is important to implement a
derating factor . A derat ing facto r is a percentage of the MaC of a component
parameter. For example, if a Smoke Analysis simulation with a 100%
derating factor were to be completed, the Cadence software would compare
a component's level of performanc e directly to the MaC. If a Smoke
Analy sis simulation with an 80% derating factor were to be completed, the
Caden ce software would compare a component's level of performance to
80% of the Mac. Designing a circuit with components that operate well
under the MaC will certainl y have a gre ater life expectancy than a circui t
with components that operate very close to or at the MaC.
cadence _ ~ x
"r1* '-dV... "s. o....., IUcCl.~.-g v....;l "'""-

Jl.-* s.ct . lr........... . .... _ :s-. ~
.- t
-I- _.- -+ -1 .+-_... :. . . . .
'to - - -. ~.:r------=i --f-: • t .- .
.. . _.-_._ . . _- --._-- - _ ._- -
.+==: -
:~--::- --_
---1--.-1 j -- --
~ .. " ±=t.
=!~-,
- -I
1--.
,
i.,
.- .. -
H·
1" -!-=±:± .-==
's .....
Figure 12.34 - AMS ADVANCED ANALYSIS wi ndow, Smo ke.
Advanced Analysis 12·29

The PSpice or Allegro AMS Advanced Analysis Simulator calculates
the performance of a component based on certain parameters. Some of these
Smoke Parameters, specifically the ones used in this example, are listed in
Table 12.1 along with their associated components.
The Smoke Parameter abbreviations listed in the left column of Table
12.1 will appear in a PARAMETER column upon simulation and describe
the Smoke Analysis type for each component. Before running the Smoke
Analysis, it is important to select the derating factor. The default derating
setting for the Smoke Analysis simulation is NO DERATING, which implies
a 100% derating factor. Th is derating factor can be set by open ing the
PROFILE SETTINGS window in the EDIT menu and clicking the SMOKE tab
(see Figure 12.35) .
After closing the PROFILE SETTINGS window, run the simulation.
The results for the Smoke Analysis are shown in Figure 12.36 and share
Table 12.1 - - - - - - - - -- - - - - - - - - - - - - - - - -
Smoke Parameters
Smoke Componen t Definition (wlunit)
Parameter
IB BJT Maximum base cur rent (A)
IC BJT Maximum collec tor current (A)
PDM BJT Maximum power dissipation (W)
RCA BJT Thermal resistance, Case- to-A mbient (degCIW)
RJC BJT Thermal resistance, Junction-to-Case (degCIW)
SBINT BJT Secondary breakdown intercept (A)
SBMI N BJT Derated percent at TJ (secondary breakdown)
SBSLP BJT Secondary breakdown slope
SBTSLP BJT Temperature derating slope (secondary breakdown)
TJ BJT Maximu m junction temperature (degC)
VCB BJT Maximum collector-base voltage (V)
VCE BJT Maximum collec tor-emitter voltage (V)
VEB BJT Maximum emitter-base voltage (V)
CI Capacitor Maximum ripple (I)
CV Capac itor Voltage rating (V)
SLP Capaci tor Temperature de rating slope (V/degC)
TBRK Capacitor Breakpoint temperature (degC)
TMAX Capacitor Maximum temperature (degC)
IV Current Supply Maximum voltage current source can withstand (V)
LI Inductor Cur rent rating (I)
LV Inductor Dielectric strength (V)
PDM Resisto r Maximum power dissipation (W)
RBA Resistor Slope of power dissipa tion vs. temperature (W/degC)
RV Resistor Voltage rating (V)
TMAX,TB Resistor Maximum temperature resistor can withstand (degC)
VI Voltage Supply Maximum current voltage source can withstand (I)
12-30 Chapter 12
Figure 12.35-
PROFILE SETTINGS
window, NO DERATING
setting.
Select deramg type:
I~
Createa is! d customderamg fie. . Twe or browse to

specify the fij path d)'OLI" customfie . Fie. entered below
wi be added to the is! d avaiable deramg types.
i Custom Deramg Res:
OK II Caral II Reset II
Figure
cadence - if " 12.36-AMS
ADVANCED
ANALYSIS
window,
" .... Smoke
,". Analysis, NO
>7
n DERATING
n setting.
"
""
""
IS
::00
::00 ...
IS
,.."" .
Smo« ............_ _
Snd.eAAt~r~
........- s. Sm .....,... .. - .•- .••.••.•.•. .
SmokIf~W((ffiItd
__..
Perf~rt9StnoltA.NJyM(WI;ptol"" tu~. Wn'_
Srnoke ,e".- ,-w fiftisMd

.................... .....,...
,~Otml"'9SmG ..~ ANfyMOftpt'of.. 'tJ~~· _
SmoteAnlIIy$i5 wc:cNdtd
_ _..
$mo '''''''''''
- - · --- --- ----- St~ ~. ~.-. - --- -_._._---. -
, tifc ,MH'19 Srf.cM~ Oft pl'Cf'H't,ltlMnt.siM·.~

SMokeAM~ wc UH td
SmoU rlMtMd
,...
a similar layout and display to those of the Sensitivity Analys is. The
components are listed in the first column; the second column names the
smoke parameter tested. These results can be given in three representations,
using a peak value, average value, or RMS value. The type of measurement
is indicated in the third column. The rated value repre sents the MOC for
the particular component. Notice the % DER AT ING column is constant at
100 since the default setting for the simulation is NO DERATI NG. The % MAX
column describe s how close in percentage the component operates within its
maximum value. This percentage is calcul ated by taking the value from the
MEASURED VALUE column and dividing by the rated value and multiplying
by 100. The results are sorted by the % MAX value in descendin g order.
According to the simulation results, all the components fall well under the
100% deratin g factor (MOC).
The Smoke Analysis simulation will be done once more, but this time
it will be completed with standard derating factor s. Open the PROF ILE
Select detatng type :
___3
Create a list of customderatn g ties . Typeorbrowse to

specifythe fullpath of your customfile . Rles entered below
wi! be added to the listof avaiable detatng types .
Custom DeratW1g Files: ,...3 X 1" ""
OK JI Cancel I[ Reset II ~
Figur e 12.37 - PROFILE SETTINGS window, STA NDA RD DERATING sett ing.
12-32 Chapter 12
SOGlAllCt·
1361< { <lit ~ a... ~
_.
l!{....... lJ«II' cadence - if "
-- "'- -
ib~ ~ e • •...-t.. - LD -:>
. ............ _v_.. - '--"',:!!- L!~"""'J "-Ir"'t - l '

,. ....
.
.... ....
"-'" T_ ..........HV. .
01 'o'a SO :lO 12.4tt1
CI CN ...." at.
,.
SO to
" 14.t:St
,.
2S
... C•
Cl
CN
AIlS
I
se
10 •• 1012M
... """"
CN
I 10 OS 'OC.t2et 2S
1lI
T1I
1-
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m
' OCI
l OCI ,..
2CG
"'5'1
.-,3711
2S
:1
- .,.
'"
01 T' A...... ISO ICC )1)132' :11
)0_
~ Ol
.. 0'
~
..""
.. "" ~ A_
"".
1:
:scm
m-
, -. ' CC
.,
101)
') ~:'~~
£C
~.uiie..
1' .1tJO
17' -
Zt
:c
"17
..... .,. .... ....
zee sa....
--
R' 11- A...... 2CC ICC 17
RI
II< 11 A_
:co
eee
lOCI :flO
lOt
"
:lA07fl
11
.
'OCI IS
RE 1lI 2CC
,..
20C :0=
..... ...."
'CC
-
llLOAO 1lI A_ :co '01) :am
"
..............
RLOAO 1lI :co 'cc :co :>-
.
R:
R:
RI
11
....
11
A
A_
i :co
:co
:scm
'OCI
'cc
••
lOll
:co
114l'QZa
21.5$.4:1
277"" .•
lUI Il>lS :- os 114i'i,...
••
ti.. l "'" ....
A_ 1-11.teo1l"11 7$ o.I: .~ _ . l& Tm>oo
-
..r.i~ •
·•
lUI 417.1&1)'", I• t6. 7~
c:
CN
CN
A_ se
so
to
to
••
'S
1!41'3
1!.I:t -I
8 -. I
Smoh~wcc.~ .
-
_ .......... fiMIwd
._ •••••••••_ •••••• Sl~ Smol................... . . .. .. .. .....
Perl'ON'l"lt"9 StnoU AtWysitOC\ Frcf iLt 'tramifotLsiftol'_
Smote ~ ~Hd td
q-,
_.
Smob ........... fonishfd
Figure 12.38 - AMS ADVA NCED AN A LYSIS window, SmokeAnalysis, STANDARD DERATING setting.
SETTINGS win dow for the Smoke Analysis and select STANDARD DERATING
(see F igure 12.3 7) . This will implement a set of derating factors designated
wit hin the Ca dence software for a give n component. These two derating
types are the on ly selectable choices in the PROFILE SETT INGS window,
though it is possible for a user to declare derating factors in custom derating
files and import them.
After making this cha nge to the profile, close the PROFILE SETTI NGS
window and run the sim ulation. The results are shown in Figure 12.38. Take
note of the % DERATING column. The column is no longer fixed at 100. To
unde rstan d how this will impact the result, we will dissect the first row, 01.
The veE (max collector emitter voltage) smoke parameter is rated at 40 V.
The derating factor imposed by the Cadence software is 50. Th is means
that the derated maximum value will be 50 % of the rated value, 20 V. This
is indicated in the MAX DERATING column. The % MAX will be calc ulated
based on the measured co llec tor-emitter voltage with respect to the MAX
DERATING value, 20. This comes out to approximately 63%. With the results

again listed in descending order in the % MAX column , and based on these
results with standard derating, all components still fall within an acceptable
region of operation .
In the event that a % MAX exceeds a rated/derated MOC, the bar in
the % MAX column will appear red. If the % MAX value is calculated to be
within 90% to 100% of the derated MOC, the bar in the % MAX column will
appear yellow.
In Summation
There are two other types of AA not discussed in this chapter. They
are the Optimizer and the Parametric Plotter, and they are typically used
heavily during the design process of a circuit. The Optimizer can assist
in finding certain component values to ensure that a design will meet a
user-defined specification. The Parametric Plotter is a simulation type that
sweeps multiple component values or model parameters simultaneously.
More inform ation and literature regarding these simulation types can be
obtained through Cadence Design Systems.
12-34 Chapter 12
Appendix
Additional Circuit
Examples
This appendix provides additional circuitry that was not covered in earlier
chapters. In these pages we are going to look at circuits for 1) Low-Pass Filter;
2) Operational Amplifier; 3) Phase-Shift Oscillator, 4) Astable Multivibrator;
and 5) Hartley Oscillator.
1) Low-Pass Filter
A low-pass filter is an electronic filter that passes low-frequency
signals and attenuates (reduces the amplitude of) signals with frequencies
higher than the cutoff frequency. The actual amount of attenuation for each
frequency varies from filter to filter. It is sometimes called a high -cut or
treble cut filter when used in audio applications. As one would imagine, a
low-pass filter is the oppo site of a high -pass filter, and a band -pass filter is
a combination of a low-pass and a high-pass. See the low-pas s RC circuit in
Figure A.t . The AC Analysis in Figure A.2 shows VIN versus VOUT from
R1
vin
10K
vou!
I
V1
10Va ~
OVdc 1 C1
0.0015"'
- - - -'
I
Figure A.1 - Low-pass RC circuit.
Additional Circuit Examples A-1

~yn : i:~:i- q•:-;- ;- - -,- -,-_: _. _
" " Z SKU 1 • • '1'
. ; ("bl · U( ". "t )
1S U ;z: 1 .ll z ZSKll z 211Mz UI Il;r ' . lIz
Figure A.2 - AC Analysis showing VIN versus OUT for the low-pass RC filter.
I Hz to 100 kHz . Other output graphs could be phase versus frequency, linear
amplitude versus frequency, and logarithmic amplitude versus frequ enc y.
2) Operational Amplifier
In Figure A.3 an operational amplifier has been introduced as a PSpi ce
element, providing gain for an active filter. An AC Analysis is shown.
Figure A.4 offers a Bode plot of amplitude versus frequency, with results
showing VOUTIVIN . It has range of frequencies from 1 Hz to 10 kHz.
C2 Figure A.3-
Operational
amplifier as
0.033uF a PSpice
element.
R2
R1 C1
VI
VOUT
2.7K 0.033 F
A-2 Appendix
11
iA
........................ -_ ........................ ....._------------------ ._ .... _---- --------------- ----------------------. ........ -............... _-
---................. -.. ..---------............... ...........--.......... .............. _----- -_ .... --_............. _------ ---- ---- ---........ ---.. ...-----................ ...... _- ------------------
.-..................... - ...-.-----................ ......... __............ ............. _- ----------- --------_..._--- -------- -- -----.. -............ ...._-_................ ._--------------------....
--_ ...... __............ -------------_... __....... ------------------------ .._-- ..._...-------------- ·······················t ·········· ············· ----------------_ .._.... -..............._- --_..... -
5
~
-------------_._--_.. __.- ---- _._------ ._.. .......... :~ . . ........ ...... . ....
::::::::::::::::::::::J --------------_..-..-..-- ... ----_.- _._.. ................ .... . - ... - - - _.__................... .. ...
--.-................. .. - .. _-------...-.-........ ..... _._. .............. . ..... ........... ..... _ - ............ ..._... ....
-------... -... ---------- ----------- ---..--------- .. ... -------- ........... ~ •
................... ... . ..................... -
r~r--. -- - -- - ...
,• 3 . IHz
'OIl ' 3 1Hz ,'OIl, 310Hz , ,"'",
. 011'
U(UQUT) I U( UI")
r r enuenc
"'"' 3
"'"'
Figure A.4 - Frequency response, Bode plot.
3) Phase-Shift Oscillator
The RC phase -shift oscillator circuit seen in Figure A.S is a great
example of using a common op-amp to make a sinusoidal oscillator. In the
original circuit , R5 was a I Mn potentiometer. A 300 kn fixed resistor can
be used, giving a gain of - 300 kilO k = - 30. VI was added to kickstart the
oscillator for the simulation. Since the RC-RC -RC feedback network has a
R5
1M
C5
R1 t, f-=2,-+--,
10uF
10K U1 r-+-- - - +--=ft--- - - -- - - - - - - - - - - - -----,
3
+ R2 R3 R4
OUl>---=----~
10K 10K 10K
2 , O~+-'--
2 2 2
uA741
1 C1 1 C2 C3
1 Q1uF 1 Q1~ O.1uF
-:-0
-:-0
Figure A.S - RC phase-shift oscillator circuit.

2. On*---+-+- -----f- - - - +- - -- + - -- -+-- -- - f - - - - I - -- -t - -- - +--l
1. On
- -- -_ __. _-_.. _--- ---_ _--_ - ---- -.-.------.- ..-.--------------_ .

30Hz 300H Z 3 .OKHz
Figure A.6 - Output of circuit, oscillations.
gain of - Yz9at the frequency where oscillation will occur, the output graph of
pin 6 versus time (a Transient Analysis) will show the growth of oscillation
until clipping occurs . Figure A.6 shows the output of the circuit, and the
oscillations can be observed. Maximum variation can be seen between
1 Hz and 3 Hz. As frequency increases, variation in signal decreases.
Readers may try decreasing the value of R5 and rerunning the analysis.
Eventually the oscillator won't start due to insufficient gain.
A-4 Appendix
4) Astable Multivibrator
Figure A.7 show an astable multivibrator. Again, V I was added to
kickstart the circuit. We implemented a Transient Analysis, evaluating the
value of resistance and capacitance to calculate time. Initially, the input
voltage was set to 12 V, then by reduc ing voltage we observe that time is
increasing as voltage decreases (see Figure A.S).
-'--0
R1 R2 R3 R4
1 C1 10 47 C3 470
-1 J---------j -11-------1
100uF 10uF
vo ut
vin
20
~
5
2N2=1
-'--0
Figure A.7 - Circuit implemented, Transient Analysis.
21 .115 ..
21 . 01 On
\ :
..
:
21 . 1 15l1li
:
J-+-- -;--:
:
:
21 .IItOR
es 1 . 2a s 0 . /f" 5 1 .6 M G.8 ns 1 .0n5 1 . 2n 5 1....n 5 1 .6 l1li5 1 . 8"5 2 . ln s
U(uo ut) I V( ui n)
.,
Figure A.a - Response graph ,Transient Analysis.

5) Hartley Oscillator
Figur e A.9 shows a Hartley oscillator circuit, which works from
frequencies below the radio range up into the gigahert z range . L1 is tapped ,
forming the reactive divider characteristics of a Hartley circuit. C4 and
L1 form a resonant tank circuit to determine the oscillator frequency. The
amplifier is a 2N2222 BJT. In Figure A.tO we have a buffer amplifier that
could be added to the oscillator output. V2 is added to simulate the output of
the oscillator that would drive the buffer amplifer. A buffer circuit provides
isolation; decoupl ing prevents ac signal from flowing between circuits. Gain
bandwidth product is a measure of a transistor's ability to amplify a high-
frequency signal (see Figure A.ll).
01
C2
2.7pF
Q2N2222
D1 R1
C4 1N4148 1M
200pF
L1
2uH
III
vout
Figure A.9 - Circuit of Hartley oscillator.
A·6 Appendix
V1
2v
R4
,-----------.ll,jl./'v--.----..-- - , vout
68 f-- - - - ----'
C3 C2
0.01 l O.01
R1
-=-0 47
10Va r\..,
V2
O1okT
l
R3 2N~2222l
~
1Vdc -
4.7k
-=- 0
l R5
270
Figure A.10 - Buffer circu it added to RF amplifier.
. , . . : . . --- ---- ---- --- ---- _. - - ~ - - _ . _ _----
~~:~:, _:~::.:~::: r: :. :. :.:.:.:.'.:.::,.::,=:,:.:.:, :.:.:.:. ~. :. :.:.:. ~.: :.:,:, :,!,:.:,:,'. :,:,:.:, :.;,: :, :. :, ~.,' :, :, :, ~,',' :, :,:, :.:,:' :" :.~ :, :, :. :. :.~:, :, :, ,: ~,;:, :, :, :, =.~:' ,'',.:: .. ::~:: ::1 ::::~:::: ----.;....";" ---'.-- ::::}:::t ::t ::: :::::::::::: .r .
.,
, .+-+--+--+--+-+---+---+---1f--i--;-+--+--+--+-+--+---+-f--i-+-+--+--+--+-+---+---+---1f--i--;-+--+--+--+-+--+---+-f--i--I
, :, ,: .' :, 1
,:,' :, :, ,: ,1
:. :, :,,::,
, , - - ~----~-- : ::j::::r :t:::: ----~--.+-- + -- '--..--'--.----y--.
-, .
Is
U2 (C 1}
' . 2"5
I (R 3 :1 ) U( TX1: 1I)
' ./iUK 1 . 6" s '.8M 1 ....5 1 . 2111"0 1. l as 2._
Ti ...
Figure A.11 - Voltage, current response .

....... .
. . . - . .i
.:. •
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Circuit Simulation

and Analysis byDrSaeidMoslehpour

An introduction to computer-aided circuit

Copyright secured under the Pan-American

All rights reserved. No part of this work may

Printed in the USA

Quedan reservados todos los derechos

"orCAD," "PSpice," and

David Sumner, KIZZ

Saeid Moslehpour, PhD

Circuit analysis is a necessary part of circuit design. Once a design for

The Need for Circuit Analysis

Cadence Design Systems

The O,CAD User

Familiarization and Preparation of the

The DreA D User Interface 2-1

Figure 2.2 - DesignEntry workspace.

The OreAD User Interface 2-3

Nam e Date mo d ified

J' J' ,~",~.~;t;:;7;1XT'"""AL

Figure 2.7- Active component libraries.

Drawing a Schematic Design

the dc voltage source and

The OreAD User Interface 2-5

RYAl DC l.oalbofox..coordlMllt l outiotly -Coontorwlte SOCIrc..,m

Figure 2.12- PROPERTY EDITOR window.

UseO/CAPSYM syrnbol tc place 0 de ground !

The OreAD User Interface 2·7

In the previous chapter we introduced the Cadence Allegro Design

Generating a Netlist from a Schematic De sign

Netlist Element Lines 3-1

Df... .·'. "'"'-"'"

= ' =.. · L·· · I)··

l E.dng "c'OrCAl)DrCAD_:6~U.. ...IolZ~

tiF O(ORCAP-32002\ NeGISl:nQ melJe""..ql

Figure 3.3 - DrCAD Capture/Allegro Design Entry window, PROJECT

~ """" ORC -... for em.. ..., W_

Figure 3.4 - CREATE NETLIST windo w.

Figure 3.5 - Netlist window for three-resistor circuit in Figure 3.1.

Netlist Element Lines 3-3

.U!JI OrCAD Capture CIS - Lite - IC:\OrCAD\OrCAD_16.5_'

SCHEMATIC1 -NeUist ....

Start Page )(Em1 Netlist* ](~ PAGEl

Figure 3.6 - Netlist close-up showing the five element lines.

Generating a Netlist Without Net Aliases

Netlist Element Lines 3-5

Figure 3.9 - Schematic design from Figure 3.7

Netlist Element Lines 3-7

We now have a complete sch ematic design drawn in the Cadence

~ OrCAD Captu re CIS - Lite - [C:\ARRL\Cade nce Po

~ SCHEhtATlCl -3 Resisl "r 1t2Yf1 JV

Figure 4.1 - NEW SIMULATION profile button.

Basic Simulation Types 4-1

Basic Simulation Types 4-3

Figure 4.9 - Two-voltage source circu it.

:'.:"'IabonS<t!;ng• • DC~ lV.}R

",.w,.;. _: Sweep variable

m" l ~ I !~) ~oltage source tla me: VAIGHT

bi ' o ,Model oe emeter H.:,d,:tlm,l1l!!' '1

Basic Simulation Types 4-5

Figure 4.11 - PSpice A/DIAllegro AMS Simuiatorwindow, also referred to as PROBE .

as the sweep takes place. To

FOf ""' ~l fl 1....