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Ellesmere Linux Board Production Suite Reference Guide
Ellesmere Linux Board Production Suite Reference Guide
Guide
1.1 Introduction
The purpose of this document is to specify the overall functionality and test definitions for the AMD Board Production
Diagnostic Test Suite.
1.2 Overview
The Board Production Diagnostic Test suite contains functional/stress tests for validating external connec-
tions/components (such as bus interfaces, display connectors, memory, and power), latency incurred by external
connections/ components to the GPU internal functionalities, and workmanship.The test suite assumes a work-
ing(qualified) GPU,and is used primarily as a tool for testing manufacturing quality on the production line.The test
suite is used by both internal and external customers. The test suite is not intended to be used for looping or for the
product qualification process(the Board Qulification Diagnostic Test Suite serves that purpose).The test suite has
several options for test coverage which have to be manually specified-these use cases are covered in the "Suite
Usage" section below.
1.3 SuiteInstallation
Download the Board Production Diagnostic Test Suite from the ORC.
If the system used for downloading is not the test system, copy the diagnostic suite over to the test system
using the network or a USB key/drive.It is NOT recommended to extract the suite in Windows and then copy
the files over to a Linux system!
Extract the diagnostic suite using the command tar xvfz suitename.tar.gz
(Optional) Delete the .tar.gz suite file to save hard drive space.
Please use the original tool with the suite to do the diagnostics, any other tool copied to this suite is not verified
and could cause potential issue.
2 Ellesmere Linux Board Production Suite Reference Guide
1.4 SuiteUsage
There are five typical use cases for the AMD Board Production Diagnostic Test Suite:
WHAT: The quick manufacturing suite is the recommended minimum test coverage for a graphics board on
the manufacturing line. This test option executes several general test blocks with default options and specified
guardband (varies from GPU to GPU). Set to Exit without pause on error.
NOTES AND IMPORTANT FLAGS: (1)-boardtest=quickmfg is intended only for PCIe Gen3 platforms as it will
run some Gen3 verification tests. To test in a Gen2 system, the flag -boardtest=quickmfg2 should be used
instead. Type ./tserver -boardtest=quickmfg2 (2) The Margin is added by default in quickmfg (typically +2%
eng and +2% mem but it can vary from GPU to GPU). The margin can be manually specified by adding the
flag -suitemargin= x, y (i.e. ./tserver -boardtest=quickmfg -suitemargin=1,1 will add 1% to engine speed, and
1% to memory speed based on highest state of perf mode). For MBA test,please use command ./tserver
-boardtest=mba, it will add 1% margin by default
WHAT: The extended manufacturing test executes a custom set of tests (which can include all of the tests
in the Quick Manufacturing Test) in addition to several additional tests. Guardband is optional (i.e. can add
standard guardband margins, or no guardband), and the error reporting method is not fixed (i.e. can chose to
exit, pause, or continue on error). Basically, this gives the tester a little bit more flexibility with regards to the
test environment and coverage.
HOW: ./tserver -boardtest=extmfg if run on Linux, tserver.exe -boardtest=extmfg if run on windows to config
test block and execute the selected tests
WHAT: The System Integration test is a quick verification test that basically ensures the graphics card has been
properly installed in the PCI Express slot. A quick 3D test, memory test are run, and the total coverage takes
less than 1 minute. This test is intended for Assembly-Line production (after the graphics boards have gone
through full quick manufacturing test r coverage during the manufacturing process).
WHAT: Runs the memory failure analysis tool on the graphics board under test. Please consult with applicable
training documentation for the proper use of this tool.
WHAT: Runs an individual diagnostic test (from the suite). This is a typical use case to reproduce failures and
check for test dependencies, etc.
HOW:SET CLOCKS(appropriate clocks must be set for the test being run), RUN TEST (using ./tserverlite
-test=IDxxx.yy if run on Linux, tserverlite.exe -test=IDxxx.yy if run on windows) -d=gpu.∗
1.5 TestResultReporting
Beginning with Baffin time frame (Oct2015) logging outputs were simplified down to two files: log.yml and log.←-
txt. Their contents are raw log stream data which includes multi-thread test data, time stamps, thermal events,
and many other forms of data.
These files are available for post-processing analysis, without requiring binary recompiles or re-release of
Suites. For Release and other builds, YAML parsing support was added into the Perl libraries, to be used by
post-processing scripts if desired.
If it defines eofe flag in tserver.cf or command line, the test suite will exit immediately when any error happens,
including event handler failure, test case failure, tools command failure and so on. It will print a big red "FAIL"
on screen. And if entire test suite pass without any error, it will show a big green "PASS" instead.
2)Test ID log
With -tid flag, it will generate testid.log which records test result for each test case. There will NO testid.log from
Baffin time frame (Oct2015) logging during suites running by default.
3)Log files
With -log flag, the detailed test result is logged into log.txt. The content of log information depends on different
log levels. You can get more detailed log information with -v=debug. Please note test result Pass+/Skip+/←-
Fail+/Abort+ means a real failure for end user. "+" means event handler failures. And please check the detailed
error message to understand which kind of event handler failures it is.
Overview
The PCIE bus suite checks for link quality by monitoring the NAKs, detects, recoveries occurred during the
normal bus operations. PCIE link width speed are also monitored during the course of the testing. Usually
PCIE tests are run in conjunction with memory and 3D tests in order to simulate normal bus operations.
Introduction
Initializes the GPU PCIE performance counters to monitor NAK received or generated events from the GPU
endpoint device. This test is normally run prior to running 3D or memory tests.
Failcase
Verifies the NAKs received and generated by the GPU endpoint device are below the threshold value. The
default threshold value is 0, but the user can overwrite the setting by using the "pcienaks" parameter.
Failcase
NAKs generated or received by the asic are above the threshold value.
Introduction
Initializes the GPU PCIE performance counters to monitor PCIE link detect or recovery events from the GPU
endpoint device. This test is normally run prior to running 3D or memory tests.
Failcase
PCIE Link detects or recovers occurred during the normal asic bus operations.
6 AG (PCI Express Suite)
Introduction
Verifies there are no PCIE Link detect or recovery events recorded in the GPU endpoint device.
Failcase
PCIE Link detects or recovers occurred during the normal asic bus operations
Failcase
The current PCIE link width does not match with therequested PCIE link width.
Introduction
Failcase
The current PCIE link speed does not match with the requested PCIE link speed.
Overview
PCIE phy suite tests features associated with PCIE physical link layer.
3.1 Test AJ015: PCIE PHY Dynamic Link Speed Switching Test (Bridge Initiated)
Introduction
These tests validate the stability of the PCIE link during PCIE link speed switching.
Passcase
The requested PCIE link speed switching is successful without any errors.
Failcase
1) The requested PCIE link speed is not supported by endpoint or bridge device.
2) PCIE link NAKs received and generated are above the threshold values.
4) PCIE link width is not same before and after PCIE link speed switching.
3.1.1 Variation AJ015.001: Link speed change between Gen1 and Gen1
3.1.2 Variation AJ015.002: Link speed change between Gen1 and Gen2
3.1.3 Variation AJ015.003: Link speed change between Gen1 and Gen3
3.1.4 Variation AJ015.004: Link speed change between Gen2 and Gen2
3.1.5 Variation AJ015.005: Link speed change between Gen2 and Gen3
3.1.6 Variation AJ015.006: Link speed change between Gen3 and Gen3
8 AJ (PCIE Phy Suite)
3.2 Test AJ018: PCIE PHY Dynamic Link Width Switching Test (Up/Down Config)
Introduction
These tests validate the stability of the PCIE link during PCIE link width switching.
Passcase
The requested PCIE link width switching is successful without any errors.
Failcase
1) The requested PCIE link width is not supported by endpoint or bridge device.
2) PCIE link NAKs received and generated are above the threshold values.
4) PCIE link speed is not same before and after PCIE link width switching.
3.2.10 Variation AJ018.021: Link width change between x16 and x16
3.3 Test AJ020: PCIE PHY Symbol Per Clock Switching Test
Introduction
These tests validate the stability of the PCIE link during symbol per clock (SPC) mode switching.
Passcase
Failcase
3.3.1 Variation AJ020.001: SPC mode change between Gen1 1SPC and Gen2 1SPC with Endpoint Initiated
3.3.2 Variation AJ020.002: SPC mode change between Gen1 1SPC and Gen2 2SPC with Endpoint Initiated
3.3.3 Variation AJ020.003: SPC mode change between Gen1 2SPC and Gen2 1SPC with Endpoint Initiated
3.3.4 Variation AJ020.004: SPC mode change between Gen1 2SPC and Gen2 2SPC with Endpoint Initiated
3.3.5 Variation AJ020.005: SPC mode change between Gen1 1SPC and Gen3 2SPC with Endpoint Initiated
3.3.6 Variation AJ020.006: SPC mode change between Gen1 2SPC and Gen3 2SPC with Endpoint Initiated
3.3.7 Variation AJ020.007: SPC mode change between Gen2 1SPC and Gen2 2SPC with Endpoint Initiated
3.3.8 Variation AJ020.008: SPC mode change between Gen2 1SPC and Gen3 2SPC with Endpoint Initiated
3.3.9 Variation AJ020.009: SPC mode change between Gen2 2SPC and Gen3 2SPC with Endpoint Initiated
Overview
The memory diagnostic tests are used in external diagnostic suites to validate the memory between the GPU
memory controller and memory chips on the board. The tests use different test patterns and graphics engines
to generate different noise levels in the memory interface and DRAMs.
There are two important groups of memory tests (BLIT tests and CB tog tests) that will be described in this
section rather than test by test. This is because the tests are very closely related, and in addition, tests in these
two groups are often leveraged by other memory tests.
The main purpose of this group of tests is to use bit BLITs to stress the memory interface from the ASIC to the
memory chips. The BLITs can be further grouped based on two types of variations:
• Data pattern used (e.g. Colorbar, Walkbit, Walkpat, Maskpat, Randbit, and Randmask)
• Direction or movement of the BLITs (e.g. Horizontal, Diagonal, Random) The data patterns are used
primarily to test the data lines. The direction or movement of the blits, (i.e., the source and destination
coordinates of the blits) are mostly designed to test the address lines.
There are five subgroups of BLIT tests to cover all BLIT direction and data pattern variations.
A description of the six data patterns used in the blit tests follows.
1. Colorbar
The lower half contains the primary (red, green, blue) and complementary (cyan, magenta, yellow) colors in
their full intensity (0xFF for 32bpp) while the upper half are about half the maximum intensity (0x9E for 32bpp).
There are also the black and white colors and shades of gray.
1. Walkbit
This pattern is intended to generate SSO pattern operations. In the presence of a DBI signal (i.e., GDDR4), it
will make the DBI signal toggle instead. Without a DBI signal (as is the case internally in the ASIC), this pattern
will generate SSO on all bits most of the time.
1. Walkpat
This pattern will generate SSO patterns even with the presence of a DBI signal. However, not all bits will be
doing SSO at the same time but rather the data bits with SSO operations will shift temporally as the pattern
walks down vertically.
1. Maskpat
This pattern is composed of a foreground and a background color. This pattern is intended to be used for color
compare blits to transfer only the foreground color. As such, this is a good pattern to test the write mask (byte
enable bits) when transferring data.
1. Randbit
This pattern is also intended to generate SSO operations like the walkbit pattern. Basically, it contains data with
a single bit randomly turned or data with single bit randomly turned off. The sequence of whether it is a single
bit on or single bit off data is also in pseudo-random order.
1. Randmask
This pattern is similar to the Maskpat pattern. The only difference is in the sequence of the foreground and
background colors which is in pseudo-random order.
CB Tog is a set of memory tests which uses the 3D engine to perform BLIT operations. These tests are more
stressful than CP, DMA or CPU operations.
• The pattern drawn is transferred to a temporary buffer using a single 2D BitBltMulti operation
• This pattern in the temporary buffer is then checked by xor-ing it with the original patterns using another
2D PaintMulti operation. This should clear (set to zero) the data unless there are anomalies
• The xor-ed data are then transferred to a result buffer using another 2D BitBltMulti operation, this time
or-ing it with the destination pattern. This way, all anomalies will be or-ed together
Introduction
This test is similar to the Write Mask (HDP) test except it uses the CP DMA to do the byte, word, and dword
data transfer. It exercises the write mask bits or data mask commands for GDDR5.
Failcase
For a test description, please refer to the section in the Introduction entitled: Group 1B: Horizontal BLIT tests
[AK307-AK312]
Introduction
For a test description, please refer to the section in the Introduction entitled: Group 1B: Horizontal BLIT tests
[AK307-AK312]
For a test description, please refer to the section in the Introduction entitled: Group 1B: Horizontal BLIT tests
[AK307-AK312]
For a test description, please refer to the section in the Introduction entitled: Group 1B: Horizontal BLIT tests
[AK307-AK312]
Introduction
For a test description, please refer to the section in the Introduction entitled: Group 1D: Random BLIT tests
[AK319-AK324]
This test does a basic sanity check to the full video memory. A pass in this test means that the GMC can
correctly complete basic read and write transactions for the whole frame buffer (FB). This test is based on Fill
Memory test (AK001) except that it does not exercise all the addressable memory, instead in skips every 65
dword address.
Failcase
This is a basic memory test. It fills full memory with sequential 32-bit values, inverse of sequential 32-bit values,
and a few content 32-bit patterns. It reads back the full memory content to check for errors after each fill. The
fills are done by simple DMA. No 2D or 3D engine is involved. It intends to catch workmanship issue, stuck
memory cells, and memory configuration issue.
Failcase
This is a memory interface stress test. It does stressful mix of memory reads and writes of stressful data
patterns. To achieve a very high level of stress, 3D engine is used to generate tight sequences of memory
read/write mix. It intends to catch signaling issues on the memory interface.
• AK301.6 Colorbar
• AK305.6 Randbit
• AK302.6 Walkbit
• AK303.6 Walkpat
• AK306.6 Randmask
The major difference is that these tests are first run multiple times without checking the result. The purpose of
this step is to pre-saturate the MC clients rather than starting from an idle state. Afterwards, the actual tests
are then run and results are checked.
Failcase
The test pattern that is used in the blits is preserved throughout each blit movements within the tests. As such,
the test patterns as well as background are checked for consistency at the end of the test.
Introduction
This is a memory failure analysis test. It does a stressful mix of memory reads and writes of stressful data
patterns and intends to determine the problematic memory channels as well as DRAMs.
Passcase
The connectivity between the board’s ASIC and DRAMs are good.
Failcase
The connectivity between the board’s ASIC and DRAMs may have issues. The failure analysis personnel should
also ensure there is acceptable noise in the power supplies.
4.11 Test AK751: Mixed: Classic Moving Blt Walkbit, Walkpat, Randbit
4.11.1 Variation AK751.406: VM8: Mixed Sysmem/FB Random BigK/4K - Alternating Snooped/NonSnooped
4K GFX 1024x768 @ 32bpp
Overview
The display output (DP) suite tests the functionality of the various display output blocks on the GPU. These
include DAC (a.k.a VGA), DVI/HDMI, LVDS, and DisplayPort, in various configurations depending on the GPU
and board design.
Introduction
This test is intended for verifying the display outputs on a graphics board by way of visual inspection.
20 DOUT (Display Output Suite)
Overview
The PM4 player plays back the contents of a PM4 trace file that was captured from the production graphics
driver as it was rendering a 3D application. The PM4 trace contains command packets for drawing geometric
primitives as well as graphics resources such as textures, vertex buffers and shader programs stored in binary
format. The player reads the graphics resources from the PM4 trace and uploads them into system and video
memory. It then reads the command packets from the PM4 trace and submits them to the GPU where they are
processed by the graphics core to re-create a scene from the 3D application. The PM4 player suite contains
one test per captured 3D application and one variation per supported GPU variant in each test.
Introduction
This test is captured from the Canyon Flight graphics test of the 3DMark06 Direct3D 9.0c benchmark.
Failcase
This test will fail if the actual CRC of any rendered frame does not match the corresponding expected CRC.
A failure could be caused by a defective GPU graphics core or memory controller, defective graphics board
components (e.g. memory chips, voltage regulators), or a defective power supply.
Introduction
This test is captured from the Heaven Direct3D 11.0 benchmark based on the Unigine 3D engine.
Failcase
This test will fail if the actual CRC of any rendered frame does not match the corresponding expected CRC.
A failure could be caused by a defective GPU graphics core or memory controller, defective graphics board
components (e.g. memory chips, voltage regulators), or a defective power supply.
Overview
The Power Management (PM) suite deals with features related to power saving and Chip Pervasive Logic (CPL)
functionality.
Miscellanous Test is a set of tests for different features. These features include reg read/write, pcc, display
timer, 3d sanity check, evv, etc.
Passcase
This test passes if max required VDDC is under or equal Max Voltage limits.
Failcase
This test fails if max required VDDC is over Max Voltage limits.
This test ensures that the Thermal Critical Temperature Fault (CTF) feature is working properly. The purpose of
the CTF feature is to shut down the system in case the GPU temperature has reached levels that are dangerous
for the GPU to operate. The feature is tested by artificially introducing and verifying the CTF condition using
GPIO pin GPIO19. The board is expected to hang after the CTF test is run; additionally, an LED will be turned
on if this test is executed on a board where CTF is actually connected to the voltage regulator on the board.
The system should be restarted after this test is run, therefore, it is recommended that this test be run at the
end of any test suite.
Passcase
GPU board powered off, CTF LED light up and fan run at full speed
24 PM (Power Management Suite)
Failcase
Introduction
This test need command line parameter: -v=info -skiptextbuffering=1. This test is to test GPU(ASIC) CTF works
or not. After the test, system need to reboot.
TBD
TBD
7.2.3 Variation PM013.017: Get Temperature Via SMBUS from External LM96163(0x98)|EMC2103(0x5C)|E←-
MC1402|ADM1032
TBD
TBD
This test validates the correct operation of the fan in regulating the asic temperature.
Guide
Introduction
Passcase
Fan is spinning normally, read back RPM normally and static fan drive mode works
Failcase
two-wire fan
Skipcase
No Fan in VBIOS
This test is to verify the Zero RPM Fan control is working and should be run under enabled Powerplay function.
During the test, Expected Behaviour If GPU temperature goes below a certain value (“Fan stop temperature”),
SMU turns off the fan. The fan will not be turned on again until the GPU temperature has gone up by a certain
value (determined by “Fan start temperature”). It is expected that by the time the GPU temp gets to “Fan stop
temperature”, the AFC has already reduced the PWM to its minimum value or close to it, so change in the
acoustics and cooling capacity will not be significant and will not cause a sudden rise in GPU temp. These
temperature values should be adjusted for each heatsink design. Also, for each heatsink design, it should
be tested whether the design at 0-rpm can support the idle power of the GPU (not every heatsink has that
capability, e.g., blower heatsink design cannot support this feature).
Passcase
if the fan rpm go to zero when current_temp is less than fan_stop_temperature and if the fan rpm is not zero
when current_temp is bigger than fan_start_temperature
Failcase
Most baco test will switch PCIE land in parallel . However, some platforms(or PCIE slots on that) don’t support
PCIE lane up/down switch, in that case, test case will skip. But you can specify "-q" option to let case go on
without switching PCIE lane. The "-q" option is not recommanded, you should test these cases on right platform
with right PCIE slot.
Failcase
Passcase
Failcase
Overview
Secure Asset Management (SAM) unit is a collection of hardware blocks responsible for accelerating various
security algorithms. The purpose this suite is to verify each blocks of hardware for their correct functionality.
• Basic AM32 instructions (SRBM register access, MLA, Montgomery exponentiation, big number multipli-
cation, all instuctions user app, etc.)
The tests will either pass or fail if the block exists, and if the intended block does not exist the test will skip.
Note: When SAM FWV has failed, system has to be power cycled before SAM FWV can pass again.
Introduction
Passcase
This test will pass when Data copied to and read from Secure Memory is successful and uncorrupted.
Failcase
This test will fail when either Data read/write from/to Secure Memory is unsuccessful or data read from Secure
Memory does not match the original.
28 SAM (Secure Asset Management (SAM) Suite)
This test will pass when soft reset handshake with kernel is successful and the reset is performed.
Failcase
This test will fail when soft reset is not successful or the reset is not performed.
Introduction
Passcase
This test passes when the encrypted result matches the expected golden result.
Failcase
This test fails when the encrypted result does not match the expected golden result.
Introduction
Passcase
This test passes when the decrypted result matches the expected golden result.
Failcase
This test fails when the decrypted result does not match the expected golden result.
Passcase
This test passes when the decrypted result matches the expected golden result.
Failcase
This test fails when the decrypted result does not match the expected golden result.
Introduction
Passcase
This test passes when the encrypted result matches the expected golden result.
Failcase
This test fails when the encrypted result does not match the expected golden result.
Passcase
This test passes when the decrypted result matches the expected golden result.
Failcase
This test fails when the decrypted result does not match the expected golden result.
Introduction
Passcase
This test passes when the encrypted result matches the expected golden result.
Failcase
This test fails when the encrypted result does not match the expected golden result.
Passcase
This test passes when the decrypted result matches the expected golden result.
Failcase
This test fails when the decrypted result does not match the expected golden result.
Overview
The sdma suite checks for issues in SDMA. It tests the functionality of copying surface between system and
local memory. Usually, the sdma suite contains 2 variations. One is for SDMA0, the other is for SDMA1.
We use parameter "SdmaEngine" to separate them. SdmaEngine = 0, 1, 2, 3, 4, 5 stand for SDMA0_GFX,
SDMA0_RLC0, SDMA0_RLC1, SDMA1_GFX, SDMA1_RLC0, SDMA1_RLC1.
Introduction
Passcase
Failcase
sDMA engine hang or Linear to tiled Copy sub-window command doesn’t complete Content in tiled buffer is not
identical to the content in destination buffer sub-window
9.1.1 Variation SDMA006.001: Test linear to tiled sub-window copy using sDMA0
32 SDMA (SDMA Suite)
Overview
The Stress3D suite is a set of graphics/compute stress tests that model typical 3D applications such as bench-
marks and games. Each test renders a different animated 3D scene. The stress level generated by a particular
test depends on the scene on which the test is based.
Introduction
This test renders a scene consisting of static food store meshes, animated spaceships and buses, and one
animated light.
Failcase
This test fails if the actual CRC of any rendered frame does not match the corresponding expected CRC.
A failure could be caused by a defective GPU graphics core or memory controller, defective graphics board
components (e.g. memory chips, voltage regulators), or a defective power supply.
Introduction
This test renders a scene consisting of static mountain meshes, animated skulls, trucks, an animated food store
and highway, and one animated light.
Failcase
This test fails if the actual CRC of any rendered frame does not match the corresponding expected CRC.
A failure could be caused by a defective GPU graphics core or memory controller, defective graphics board
components (e.g. memory chips, voltage regulators), or a defective power supply.
Introduction
This test renders one scene to a texture and then applies that texture to a plane in another scene. The first scene
consists of static mountain meshes, animated skulls, trucks, a food store and a highway, and one animated light.
The second scene consists of a growing sphere with a fur material applied, an animated plane containing the
first scene, and one animated light.
Failcase
This test fails if the actual CRC of any rendered frame does not match the corresponding expected CRC.
A failure could be caused by a defective GPU graphics core or memory controller, defective graphics board
components (e.g. memory chips, voltage regulators), or a defective power supply.
This test renders a scene consisting of some animals with normal 3D models, teapot and elepant models with
tessellation, and one animated light.
Failcase
This test fails if the actual CRC of any rendered frame does not match the corresponding expected CRC.
A failure could be caused by a defective GPU graphics core or memory controller, defective graphics board
components (e.g. memory chips, voltage regulators), or a defective power supply.
Failcase
This test fails if the actual CRC of any rendered frame does not match the corresponding expected CRC.
A failure could be caused by a defective GPU graphics core or memory controller, defective graphics board
components (e.g. memory chips, voltage regulators), or a defective power supply.
Overview
The Unified Video Decoder, previously called Universal Video Decoder, or UVD in short, is a video decoding
unit that supports hardware decoding. The formats supported include:
• Full VC-1 and H.264 decoding (UVD 1)
• Frequency transformation and motion compensation in MPEG-2 (UVD 2)
• Full decoding support for MVC, MPEG-2, and MPEG-4/DivX/Xvid (UVD 3)
• Full decoding support for WMV9 (UVD 4) Each test is composed of approximately 30 frames, each with
a pair of bitstream data/decode messages. A decoding session in the UVD hardware will output to a
memory buffer in YUV format, one image for each decoded frame. The HW CRC delivered by UVD
FirmWare (FW) is used to validate the decoding process (and to determine if the test passed or failed)
Introduction
These tests verify the access of UVD registers through various access methods.
Guide
Passcase
Read back of the registers under test are matching the expected values written by the test.
Failcase
Read back of the registers under test do not match expected values written by written by the test.
Guide
Passcase
UVD MIF CRCs collected from FW feedback structure must match the reference
Failcase
UVD MIF CRCs collected from FW feedback structure do not match the reference
Guide
Passcase
UVD MIF CRCs collected from FW feedback structure must match the reference
Failcase
UVD MIF CRCs collected from FW feedback structure do not match the reference
Guide
Passcase
UVD MIF CRCs collected from FW feedback structure must match the reference
Failcase
UVD MIF CRCs collected from FW feedback structure do not match the reference
Guide
Passcase
UVD MIF CRCs collected from FW feedback structure must match the reference
Failcase
UVD MIF CRCs collected from FW feedback structure do not match the reference
Guide
Passcase
UVD MIF CRCs collected from FW feedback structure must match the reference
Failcase
UVD MIF CRCs collected from FW feedback structure do not match the reference
These tests verify UVD decoding of 4K resolution H264 streams with H264 performance mode
Guide
Passcase
UVD MIF CRCs collected from FW feedback structure must match the reference
Failcase
UVD MIF CRCs collected from FW feedback structure do not match the reference
Introduction
These tests verify UVD decoding of H265 streams, including 10-bit decoder and dithering
Guide
Passcase
UVD MIF CRCs collected from FW feedback structure must match the reference
Failcase
UVD MIF CRCs collected from FW feedback structure do not match the reference
11.8.6 Variation UVD019.103: H265-HD 10-bit 4096x2160 Boston Harbor p010_mode msb_mode
11.8.10 Variation UVD019.120: H265-HD 10-bit 3840x2160 Boston Harbor rate control p010_mode lsb_mode
11.8.14 Variation UVD019.201: H265-HD 10-bit Grand Bend Patio 4096x2160 dithering trunction
11.8.15 Variation UVD019.209: H265-HD 9bitY_9bitC Grand Bend Patio 4096x2160 dithering roundingA
11.8.16 Variation UVD019.216: H265-HD 10bitY_8bitC Grand Bend Patio 4096x2160 dithering roundingB
11.8.17 Variation UVD019.223: H265-HD 8bitY_10bitC Grand Bend Patio 4096x2160 dithering fixed
11.8.18 Variation UVD019.230: H265-HD 8bitY_9bitC Grand Bend Patio 4096x2160 dithering random
These tests verify the decode operation of the UVD MJPEG engine
Guide
Passcase
YUV generated frames are a match against reference decoder, make sure YUV looks good visuallly.
Failcase
YUV generated frames are different than the one generated by reference decoder, ouptut YUV show corruption
on vissual inspection.
Guide
Passcase
UVD HW CRCs collected from FW feedback structure must match the reference
Failcase
UVD HW CRCs collected from FW feedback structure do not match the reference
Overview
The VCE suite tests the functionality of Video Compression Encoding block on the GPU designed to encode
raw video data (YUV 4:2:0) to various compression standards, including H.264, H.263, and MPEG-4.
Introduction
In all the regular encoder tests, YUV data and encode parameters are feed in, the encoder will output the
bitstreams of types specified for each test. The tests use the golden CRC references for validation. The input
YUV data will be encoded and collected H/W CRC are compared.
Passcase
Failcase
Tests fail if CRC references and H/W CRC are not identical.
Introduction
In all the regular encoder tests, YUV data and encode parameters are feed in, the encoder will output the
bitstreams of types specified for each test. The tests use the golden CRC references for validation. The input
YUV data will be encoded and collected H/W CRC are compared.
Passcase
Failcase
Tests fail if CRC references and H/W CRC are not identical.
HEVC encode is new codec type in UVD hardware, this test is for basic HEVC protocol
Passcase
Failcase
Tests fail if CRC references and H/W CRC are not identical.