ANUPRIYA MISHRA

M.Tech in Electronics and Communication Engineering Mobile: +91-8468069326

House No. – 350 Sector-16 Email id- anupriyaece.2013@gmail.com
Dwarka, Delhi-110075

Objective

Seeking a position with an organization where I can contribute my skills for organization’s success
and synchronize with new technology while being resourceful, innovative and flexible.

Work Experience

Job profile: Project Mentor

Department: Research and Education
Duration: From July, 2017 to March, 2018
Key Responsibilities Handled:

 Conducted sessions for teacher and students.

 Worked on sensors and microcontroller.
 Worked on BEAK projects.
 Worked on 3D printer.
 Worked on innovative ideas of students.
 Projects design and testing.
 Worked on live projects of Noise meter and Air pollution checker.

PG-CERTIFICATE IN VLSI DESIGN

DKOP LABS NOIDA July 2018 to Present

• Got training and hands on experience in Bash , tcl/tk, verilog, system verilog.
• Pursuing with verilog project – AMBA AHB –Lite Protocol.

Industrial Training Projects

• Project 1: Design and Verification of AMBA AHB Lite Protocol in Modelsim.
• Project 2: Design and Verification of ATM machine using Verilog HDL in Modelsim.
• Project 3: Design and Implementation of VGA controller on FPGA.

Skill Set and Interests

 Software/ Hardware languages : Verilog, System Verilog

 EDA Tools
 Scripting Language
 Platforms
 Bus Architecture
 Signal Integrity
: Mentor Graphics, Tanner , Xilinx,Questasim.
: Bash Shell, TCL/TK.
: Windows, Linux.
: I2C, UART, SPI
: LVTTL, LVPECL, LVCMOS
Academic Profile

Degree Board / University Year CGPA / Percentage

M.Tech [ECE] GGSIPU 2018 75.05%
B.Tech [ECE] UPTU 2013 66.66%
Higher Secondary CBSE 2009 73.40%
Secondary CBSE 2007 69%

Projects
M.Tech Final Year Project
 Project 1: Design of Low Power Dynamic Comparator in 180 nm CMOS Technology.
Description: I have successfully Dynamic CMOS comparator in 180nm CMOS technology.
Comparator is proposed using circuit level techniques LECTOR, GALEOR, ONOFIC, LCNT &
LCMT in which two leakage transistors are added between pull up and pull down network of logic
circuit in different styles and are used to design circuit with no critical path. Proposed comparator
circuit performance analysis is done in respect of power dissipation and delay.

 Project 2: Design of Low Power SERF Full adder using LCNT Technique.
Description: Design SERF Full adder using leakage control NMOS transistor technique. Power
consumption in SERF full adder is 113.39pW at 1.8V power supply. When LCNT technique is
applied in SERF adder then power reduces to 105.68pW at transistor size of W P=0.45µW,
WN=0.18µW. When transistor size is WP=0.5µW, WN=0.2µW power reduces to 98.78pW.

 Project 3: Design of Low Power Dynamic Comparator using low Power Stacking Technique.
Description: The dynamic comparator is implemented using stacking technique to reduce leakage
power using Mentor Graphics Pyxis tool.

B.Tech. Project

Title: Designed Fixed point Unsigned number Multiplier and Adder by ADD/SHIFT method
using VHDL.
Achievements

Anupriya Mishra and Manoj Kumar, “Design of Low Power Dynamic Comparator in 180
nm CMOS Technology”, IEEE International Conference on Advances in Computing,
Communication Control and Networking. Status: Published

Declaration
I hereby declare that all the information provided here is correct to the best of my knowledge and
belief and I promise to abide all the norms laid down by your esteemed organization.

Anupriya Mishra