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Navigating SoC

Veri cation with Perspec


Portable Stimulus
Nick June 16, 2017

Gone are the days when you used to use manual navigation aids to move

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around the town. Opening the Global Positioning System (GPS) to public
use enticed technology rms to provide automation in navigation. Just
by using your local coordinates and destination (“The goal”)  automated
navigation tools can provide multiple choices to reach it.

There was a time when navigating SoC Veri cation was a purely manual
task. It was getting tedious for users to plan and write manual tests and
was common to see thousands of manually written SoC tests that were
hard to maintain and port across projects. Furthermore, it was very
dif cult to understand what these tests where really doing, functional
cover points provided some clues but it wasn’t suf cient to understand
what the test intent was.

The introduction by Accellera of the Portable Stimulus Standard (PSS)


and the Cadence implementation in Perspec have changed the way we
look at this problem and it has solved the complex problem of navigating
SoC use cases. It has given EDA vendors a path to automate SoC use case
solving and generating stimulus for different engines used for
veri cation.
Given user goals (“SoC coordinates”) and modelling the constraints on
path (“walk, drive, y”) to reach the goal (“destination”), PSS provides the
semantics that allow formal analysis and constraint solving of the SoC
state space for automatic scenario completion to reach the user
speci ed goals. Such automation results in the creation of a plethora of
possible legal paths to reach a goal – some user probably thought about
in his veri cation plan and some that the tool “ gured out” or as we call
in Perspec “planned” to reach user goals, very similar to how the GPS
based navigation tools plans your route(s) to help you reach your
destination (“the goal”). Such automatic planning of partially speci ed
scenarios capturing user goals provides interesting insights into what
the SoC could do!, and is proving to be far superior to directed tests
where user is expected to manually specify all the possible paths to
achieve a given goal. 

Through the development of PSS it became apparent that we could now

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start developing System Veri cation IPs (VIPs) based on PSS semantics
that could automate stimulus generation for different veri cation
engines. With the emergence of large designs serving mobile, server,
automotive markets, veri cation of these classes of systems is proving to
be extremely challenging. The embedded processors along with their
cache hierarchy, interconnects and memory subsystems need to be
architected carefully to get the best software performance. Cadence
developed the Perspec PSLib (Portable Stimulus Library) to tackle and
automate veri cation of such complex systems. The Cadence Perspec
PSLib for multicore Armv8 and Armv8.2 architectures comes with a
comprehensive veri cation plan (vPlan) and self-checking scenarios to
check complex interaction in compute subsystems low power
management (core, cluster, cache hierarchies), coherency (including I/O)
operations, different exclusive locking schemes (spin, global, ticket,
acquire/release), system page management with TLBi/DVM at different
exception levels (ELx). The code can be generated for AARCH 32/64 bit
architectures while supporting a wide range of compilers
To learn more about PSS and Perspec, join us at DAC – read here:

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Have You Fully Veri ed Your Multi-Core, Cache-Coherent SoC? Learn
More @ DAC

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