Professional Documents
Culture Documents
Navigating Soc Veri Cation With Perspec Portable Stimulus: June 16, 2017
Navigating Soc Veri Cation With Perspec Portable Stimulus: June 16, 2017
Gone are the days when you used to use manual navigation aids to move
Feedback
around the town. Opening the Global Positioning System (GPS) to public
use enticed technology rms to provide automation in navigation. Just
by using your local coordinates and destination (“The goal”) automated
navigation tools can provide multiple choices to reach it.
There was a time when navigating SoC Veri cation was a purely manual
task. It was getting tedious for users to plan and write manual tests and
was common to see thousands of manually written SoC tests that were
hard to maintain and port across projects. Furthermore, it was very
dif cult to understand what these tests where really doing, functional
cover points provided some clues but it wasn’t suf cient to understand
what the test intent was.
Feedback
start developing System Veri cation IPs (VIPs) based on PSS semantics
that could automate stimulus generation for different veri cation
engines. With the emergence of large designs serving mobile, server,
automotive markets, veri cation of these classes of systems is proving to
be extremely challenging. The embedded processors along with their
cache hierarchy, interconnects and memory subsystems need to be
architected carefully to get the best software performance. Cadence
developed the Perspec PSLib (Portable Stimulus Library) to tackle and
automate veri cation of such complex systems. The Cadence Perspec
PSLib for multicore Armv8 and Armv8.2 architectures comes with a
comprehensive veri cation plan (vPlan) and self-checking scenarios to
check complex interaction in compute subsystems low power
management (core, cluster, cache hierarchies), coherency (including I/O)
operations, different exclusive locking schemes (spin, global, ticket,
acquire/release), system page management with TLBi/DVM at different
exception levels (ELx). The code can be generated for AARCH 32/64 bit
architectures while supporting a wide range of compilers
To learn more about PSS and Perspec, join us at DAC – read here:
Feedback
Have You Fully Veri ed Your Multi-Core, Cache-Coherent SoC? Learn
More @ DAC
Feedback