IRF840L, SiHF840L

Vishay Siliconix

Power MOSFET

FEATURES
PRODUCT SUMMARY • Halogen-free According to IEC 61249-2-21
VDS (V) 500 Definition
RDS(on) () VGS = 10 V 0.85 • Dynamic dV/dt Rating
Qg (Max.) (nC) 63 • Repetitive Avalanche Rated
• Fast Switching
Qgs (nC) 9.3
• Ease of Paralleling
Qgd (nC) 32
• Simple Drive Requirements
Configuration Single • Compliant to RoHS Directive 2002/95/EC
D
I2PAK DESCRIPTION
(TO-262) Third generation Power MOSFETs from Vishay provide the
designer with best combination of fast switching,
ruggedized device design, low on-resistance and
G cost-effectiveness.
The I2PAK (TO-262) is a power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and lowest possible on-resistance.
S S The I2PAK (TO-262) is suitable for high current applications
D
G N-Channel MOSFET because of its low internal connection resistance and can
dissipate up to 2.0 W.

ORDERING INFORMATION
Package I2PAK (TO-262)
Lead (Pb)-free and Halogen-free SiHF840L-GE3
IRF840LPbF
Lead (Pb)-free
SiHF840L-E3

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS 500 V
Gate-Source Voltage VGS ± 20 V
TC = 25 °C 8.0
Continuous Drain Current VGS at 10 V ID
TC = 100 °C 5.1 A
Pulsed Drain Currenta IDM 32
Linear Derating Factor 1.0 W/°C
Single Pulse Avalanche Energyb EAS 510 mJ
Repetitive Avalanche Currenta IAR 8.0 A
Repetitive Avalanche Energya EAR 13 mJ
TC = 25 °C 125
Maximum Power Dissipation PD W
TC = 100 °C 50
Peak Diode Recovery dV/dtc dV/dt 3.5 V/ns
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 150
°C
Soldering Recommendations (Peak Temperature) for 10 s 300d
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 50 V, starting TJ = 25 °C, L = 14 mH, Rg = 25 , IAS = 8.0 A (see fig. 12).
c. ISD  8.0 A, dI/dt  100 A/μs, VDD  VDS, TJ  150 °C.
d. 1.6 mm from case.

* Pb containing terminations are not RoHS compliant, exemptions may apply

Document Number: 91069 www.vishay.com

S10-2554-Rev. B, 08-Nov-10 1
IRF840L, SiHF840L
Vishay Siliconix

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient RthJA - 62
°C/W
Maximum Junction-to-Case (Drain) RthJC - 1.0

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 μA 500 - - V
VDS Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mA - 0.78 - V/°C
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V
Gate-Source Leakage IGSS VGS = ± 20 V - - ± 100 nA
VDS = 500 V, VGS = 0 V - - 25
Zero Gate Voltage Drain Current IDSS μA
VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 250
Drain-Source On-State Resistance RDS(on) VGS = 10 V ID = 4.8 Ab - - 0.85 
Forward Transconductance gfs VDS = 50 V, ID = 4.8 Ab 4.9 - - S
Dynamic
Input Capacitance Ciss - 1300 -
VGS = 0 V,
Output Capacitance Coss VDS = 25 V, - 310 - pF
f = 1.0 MHz, see fig. 5
Reverse Transfer Capacitance Crss - 120 -
Total Gate Charge Qg - - 63
ID = 8 A, VDS = 400 V
Gate-Source Charge Qgs VGS = 10 V - - 9.3 nC
see fig. 6 and 13b
Gate-Drain Charge Qgd - - 32
Turn-On Delay Time td(on) - 14 -
Rise Time tr VDD = 250 V, ID = 8.0 A - 23 -
ns
Turn-Off Delay Time td(off) Rg = 9.1 , RD = 31, see fig. 10b - 49 -
Fall Time tf - 20 -
Between lead, D
Internal Drain Inductance LD - 4.5 -
6 mm (0.25") from
package and center of G
nH
Internal Source Inductance LS die contact - 7.5 -
S

Drain-Source Body Diode Characteristics

MOSFET symbol
Continuous Source-Drain Diode Current IS D
- - 8.0
showing the
integral reverse G
A
Pulsed Diode Forward Currenta ISM p - n junction diode S - - 32

Body Diode Voltage VSD TJ = 25 °C, IS = 8 A, VGS = 0 Vb - - 2.0 V

Body Diode Reverse Recovery Time trr - 460 970 ns
TJ = 25 °C, IF = 8.0 A, dI/dt = 100 A/μsb
Body Diode Reverse Recovery Charge Qrr - 4.2 8.9 μC
Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.

www.vishay.com Document Number: 91069

2 S10-2554-Rev. B, 08-Nov-10
 IRF840L, SiHF840L
Vishay Siliconix

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

VGS
Top 15 V
10 V 150 °C
8.0 V 101

ID, Drain Current (A)

ID, Drain Current (A)

7.0 V
101 6.0 V
5.5 V
5.0 V 25 °C
Bottom 4.5 V

100
4.5 V

100 20 µs Pulse Width 20 µs Pulse Width

TC = 25 °C VDS = 50 V

100 101 4 5 6 7 8 9 10

91069_01 VDS, Drain-to-Source Voltage (V) 91069_03 VGS, Gate-to-Source Voltage (V)

Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 3 - Typical Transfer Characteristics

3.0
RDS(on), Drain-to-Source On Resistance

VGS ID = 8.0 A
Top 15 V VGS = 10 V
101 10 V 2.5
8.0 V
ID, Drain Current (A)

7.0 V
2.0
(Normalized)

6.0 V
5.5 V 4.5 V
5.0 V 1.5
Bottom 4.5 V

1.0

100 0.5
20 µs Pulse Width
TC = 150 °C
0.0
100 101 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160

91069_02 VDS, Drain-to-Source Voltage (V) 91069_04 TJ, Junction Temperature (°C)

Fig. 2 - Typical Output Characteristics, TC = 150 °C Fig. 4 - Normalized On-Resistance vs. Temperature

Document Number: 91069 www.vishay.com

S10-2554-Rev. B, 08-Nov-10 3
IRF840L, SiHF840L
Vishay Siliconix

2500
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted

ISD, Reverse Drain Current (A)

2000 Crss = Cgd
Coss = Cds + Cgd
Capacitance (pF)

101
1500 Ciss

1000 150 °C

25 °C
Coss
500
Crss
VGS = 0 V
0 100
100 101 0.4 0.6 0.8 1.0 1.2 1.4

91069_05 VDS, Drain-to-Source Voltage (V) 91069_07 VSD, Source-to-Drain Voltage (V)

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage

20 102
ID = 8.0 A Operation in this area limited
VGS, Gate-to-Source Voltage (V)

5 by RDS(on)
16 VDS = 400 V
2 10 µs
ID, Drain Current (A)

VDS = 250 V
10
VDS = 100 V 100 µs
12 5

2 1 ms
8
1
10 ms
5
4
TC = 25 °C
For test circuit 2 TJ = 150 °C
see figure 13 Single Pulse
0 0.1
2 5 2 5 2 5 2 5 2 5
0 15 30 45 60 75 0.1 1 10 102 103 104

91069_06 QG, Total Gate Charge (nC) 91069_08 VDS, Drain-to-Source Voltage (V)

Fig. 6 - Typical Gate Charge vs. Drain-to-Source Voltage Fig. 8 - Maximum Safe Operating Area

www.vishay.com Document Number: 91069

4 S10-2554-Rev. B, 08-Nov-10
 IRF840L, SiHF840L
Vishay Siliconix

RD
VDS

VGS
D.U.T.
8.0 Rg
+
- VDD

10 V
ID, Drain Current (A)

6.0 Pulse width ≤ 1 µs

Duty factor ≤ 0.1 %

4.0 Fig. 10a - Switching Time Test Circuit

2.0 VDS
90 %

0.0
25 50 75 100 125 150

91069_09 TC, Case Temperature (°C) 10 %

VGS
td(on) tr td(off) tf

Fig. 9 - Maximum Drain Current vs. Case Temperature Fig. 10b - Switching Time Waveforms

10
Thermal Response (ZthJC)

1
D = 0.5
0.2
0.1 0.1 PDM
0.05
0.02 Single Pulse
0.01 (Thermal Response) t1
10-2 t2
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
10-3
10-5 10-4 10-3 10-2 0.1 1 10 102

91069_11 t1, Rectangular Pulse Duration (S)

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

L
VDS VDS
Vary tp to obtain
tp
required IAS
VDD
Rg D.U.T. +
V DD
- VDS
IAS
10 V
tp 0.01 W
IAS

Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms

Document Number: 91069 www.vishay.com

S10-2554-Rev. B, 08-Nov-10 5
IRF840L, SiHF840L
Vishay Siliconix

1200
ID

EAS, Single Pulse Energy (mJ)

Top 3.6 A
1000 5.1 A
Bottom 8.0 A
800

600

400

200

VDD = 50 V
0
25 50 75 100 125 150

91069_12c Starting TJ, Junction Temperature (°C)

Fig. 13 - Maximum Avalanche Energy vs. Drain Current

Current regulator
Same type as D.U.T.

QG 50 kΩ
10 V 12 V 0.2 µF
0.3 µF

QGS QGD +
VDS
D.U.T. -

VG
VGS

3 mA

Charge
IG ID
Current sampling resistors

Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit

www.vishay.com Document Number: 91069

6 S10-2554-Rev. B, 08-Nov-10
 IRF840L, SiHF840L
Vishay Siliconix

Peak Diode Recovery dV/dt Test Circuit

+ Circuit layout considerations

D.U.T.
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
-

- +
-

Rg • dV/dt controlled by Rg +
• Driver same type as D.U.T. VDD
-
• ISD controlled by duty factor “D”
• D.U.T. - device under test

Driver gate drive

Period P.W.
D=
P.W. Period

VGS = 10 Va

D.U.T. lSD waveform

Reverse
recovery Body diode forward
current current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
VDD

Re-applied
voltage
Body diode forward drop
Inductor current

Ripple ≤ 5 % ISD

Note
a. VGS = 5 V for logic level devices

Fig. 14 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91069.

Document Number: 91069 www.vishay.com

S10-2554-Rev. B, 08-Nov-10 7
 Package Information
Vishay Siliconix

TO-263AB (HIGH VOLTAGE)

A
(Datum A)
3 4 A A B
E c2
H
4 L1 4 Gauge
plane
0° to 8° B
D 5 Detail A Seating plane
H
C C L A1
1 L3 L4
2 3
Detail “A”
L2
Rotated 90° CW
B B
scale 8:1

A
2 x b2
2xb c
E
0.010 M A M B
± 0.004 M B
2xe
Base
5 metal D1
Plating 4
b1, b3

(c) c1 5

(b, b2)
Lead tip Section B - B and C - C E1 4
Scale: none View A - A

MILLIMETERS INCHES MILLIMETERS INCHES

DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.
A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 -
A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420
b 0.51 0.99 0.020 0.039 E1 6.22 - 0.245 -
b1 0.51 0.89 0.020 0.035 e 2.54 BSC 0.100 BSC
b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625
b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110
c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066
c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070
c2 1.14 1.65 0.045 0.065 L3 0.25 BSC 0.010 BSC
D 8.38 9.65 0.330 0.380 L4 4.78 5.28 0.188 0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.

Document Number: 91364 www.vishay.com

Revision: 15-Sep-08 1
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Material Category Policy

Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.

Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
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Revision: 12-Mar-12 1 Document Number: 91000