EJERCICIO 1:

a)

library ieee;
use ieee.std_logic_1164.all;
entity proyect is
port ( a , b ,c ,d : in std_logic;
g : out std_logic);
end proyect ;
architecture synth of proyect is
begin
g<=( d or not( (b and c) and ( a or d)) or ((a and not b) and d) or not c) ;
end synth;

SE OBSERVA EL
DISEÑO EN
VHDL

EL CIRCUITO DE LA
FUNCION

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 CRONOGRAMA DE
LA FUNCION

b)

library ieee;
use ieee.std_logic_1164.all;
entity circuitov is
port ( a , b ,c ,d : in std_logic;
h : out std_logic);
end circuitov ;
architecture synth of circuitov is
begin

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h<= ( ( ((a and not d) and b) and c) or ( ((not a and b) and d ))or ( not ((a and ((c and not d) or
b)) or d ))) ;
end synth;

SE OBSERVA EL
DISEÑO EN
VHDL

EL CIRCUITO DE LA
FUNCION

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 CRONOGRAMA DE
LA FUNCION

EJERCICIO 2:
A)

library ieee;
use ieee.std_logic_1164.all;
entity circuitov is

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port ( a , b ,c : in std_logic;
f : out std_logic);
end circuitov ;
architecture synth of circuitov is
signal a1 ,a2 : std_logic;
begin
a1<= a and b ;
a2<= not(b and c );
f<= a1 or a2 ;
end synth;

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B)

library ieee;
use ieee.std_logic_1164.all;
entity circuitov is
port ( a , b ,c : in std_logic;
f : out std_logic);
end circuitov ;
architecture synth of circuitov is
signal a1 ,a2 : std_logic;
begin
a1<= not ( a or b);
a2<= not(b and c );

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f<= a1 or a2 ;
end synth;

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C)

library ieee;
use ieee.std_logic_1164.all;
entity circuitov is
port ( a , b ,c : in std_logic;
f : out std_logic);
end circuitov ;
architecture synth of circutov is
signal a1 ,a2 , a3 : std_logic;
begin
a1<= not a;
a2<= not b;

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a3<= not c ;
f<= not( a1 or a2 or a3 );
end synth;

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D)

library ieee;
use ieee.std_logic_1164.all;
entity circuitov is
port ( a , b ,c : in std_logic;
z : out std_logic);
end circuitov ;
architecture synth of circuitov is

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signal a1 ,a2 : std_logic;
begin
a1<= not(not a and b and not c);
a2<= not(a and not b and c ) ;
f <= a1 or a2 ;
end synth;

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