Operating System Assignment No.

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Pratham Kumar Jha
189301211
May 20, 2020

Manipal University Jaipur

Q1. Given memory partitions of 100 KB, 500 KB, 200 KB, 300 KB, and
600 KB, how would each of the first fit, best fit and worst fit algorithms place
processes of 212 KB, 417 KB, 112 KB and 426 KB? Which algorithm makes
the most efficient use of memory?
Solution:
Process Size
P1 212KB
P2 417KB
P3 112KB
P4 426KB

First Fit
Waiting:P4
100KB:
500KB:P1
200KB:P3
300KB:
600KB:P2

Worst Fit
Waiting:P4

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 100KB:
500KB:P2
200KB:
300KB:P3
600KB:P1

Best Fit
This is the best algorithm as it makes the most efficient use of memory.
100KB:
500KB:P2
200KB:P3
300KB:P1
600KB:P4

Q2. For each of the following decimal virtual addresses, compute the virtual
page number and offset for a 4 KB page and for an 8 KB page: 20000, 32768,
60000
Solution:
Address PageNo.(4KB) Offset(4KB) PageNo.(8KB) Offset(8KB)
÷4 (mod 4) ÷8 (mod 8)
20000 4 3616 2 3616
32768 8 0 4 0
60000 14 2656 4 2656

Q3. Consider a logical address space of eight pages of 1024 words each,
mapped onto a physical memory of 32 frames.
(a) How many bits are in logical address?
(b) How many bits are in physical address?
Solution:
‘a) 1024= 210 8= 23 10+3=13 bits
10
‘b) 1024= 2 32= 25 10+5=15 bits

Q4. A machine has 48-bit virtual addresses and 32-bit physical addresses.
Pages are 8 KB. How many entries are needed for the page table?
Solution:
8KB = 8192 = 213

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Offset = 13 bits
No. of entries in page title = 248−13 = 235

Q5. A computer whose processes have 1024 pages in their address spaces
keeps its page tables in memory. The overhead required for reading a word
from the page table is 5 nsec. To reduce this overhead, the computer has a
TLB, which holds 32 (virtual page, physical page frame pairs), and can do a
look up in 1 nsec. What hit rate is needed to reduce the mean overhead to
2 nsec?
Solution:
2 = x + 5(1-x)
4x=3
x= 3/4 = 0.75
75 % hit rate would be sufficient.

Q6. A m/c has a 32- bit address space and an 8 KB page. The page table
is entirely in H/W, with one 32-bit word per entry. When a process starts,
the page table is copied to the H/W from memory, at one word every 100
nsec. If each process runs for 100msec (including the time to load the PT),
what fraction of CPU time is devoted to loading the page tables?
Solution:
8KB = 8192 = 213 bytes
Offset = 13 bits
No. of entries in the page table = 219
Time for loading the page table = 100nsec × 219
. = 52428800 nsec
. = 52.4 nsec
Fraction of CPU time devoted to loading page tables = 52.4/100 = .524

Q7. A computer has 32-bit virtual addresses and 4 KB pages. The pro-
gram and data together fit in the lowest page (0-4095). The stack fits in the
highest page. How many entries are needed in the page table if traditional
(one level) paging is used? How many page table entries are needed for two
level paging with 10 bits in each part?
Solution:
For normal page table no. of entries needed = 2(1 for stack + 1 for data/program)
For two-level page table no. of entries needed = 4(2 for page table 1 + 2 for

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page table 2)

Q8. Consider a paging system with the page table stored in memory. i. If a
memory reference takes 200 nsecs, how long does a paged memory reference
take? ii. If we add TLBs, and 75 % of all the page table references are found
in the TLBs, what is the effective memory reference time? ( Assume that
finding a page table entry in the TLB takes zero time)
Solution:
i.) 200ns to access page table + 200ns to access word in memory = 400ns
ii.) (.75 * 200)+(.25 * 400) = 250ns

Q9. Why we go for two level paging? A computer has 32-bit virtual ad-
dresses and 4 KB pages. The program and data together fit in the lowest
page (0-4095). The stack fits in the highest page. How many entries are
needed in the page table if traditional (one level) paging is used? How many
page table entries are needed for two level paging with 10 bits in each part?
Solution:
Most modern computer systems support a large logical address space.In such
an environment the page table itself becomes excessively large. So we divide
the page table into smaller piecies thus we go for two-level paging.

2nd part answered in Question 7

Q10. 10. Suppose that a 32-bit virtual address is broken up into four fields,
a, b, c, and d. The first three are used for a three-level page table system.
The fourth field, d, is the offset. Does the number of pages depend on the
sizes of all four fields? If not, which ones matter and which ones do not?
Solution:
No. of pages depend on d only.But as
a+b+c+d = 32
So d does depend on (a+b+c) but not on a,b,c individually thus making no
of pages depend on (a+b+c)

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Q11. 11. A computer with a 32-bit address uses a two-level page table.
Virtual addresses are split into a 9-bit top-level page table field, an 11-bit
second-level page table field, and an offset. How large are the pages and how
many are there in the address space?
Solution:
Page size = 232−9−11 = 212 = 4KB
Total Pages = 29 ∗ 211 = 220