FPGA DS 02012 2 1 ECP5 ECP5G Family Data Sheet

ECP5 and ECP5-5G Family
Data Sheet
FPGA-DS-02012-2.1
April 2019
Data Sheet
Contents
Acronyms in This Document .................................................................................................................................................8
1. General Description ......................................................................................................................................................9
1.1. Features ...............................................................................................................................................................9
2. Architecture ................................................................................................................................................................11
2.1. Overview ...........................................................................................................................................................11
2.2. PFU Blocks .........................................................................................................................................................12
2.2.1. Slice ...............................................................................................................................................................13
2.2.2. Modes of Operation ......................................................................................................................................16
2.2.2.1. Logic Mode ...........................................................................................................................................16
2.2.2.2. Ripple Mode .........................................................................................................................................16
2.2.2.3. RAM Mode ...........................................................................................................................................16
2.2.2.4. ROM Mode ...........................................................................................................................................17
2.3. Routing ..............................................................................................................................................................17
2.4. Clocking Structure .............................................................................................................................................17
2.4.1. sysCLOCK PLL.................................................................................................................................................17
2.5. Clock Distribution Network ...............................................................................................................................19
2.5.1. Primary Clocks ...............................................................................................................................................19
2.5.1.1. Dynamic Clock Control .........................................................................................................................20
2.5.1.2. Dynamic Clock Select ...........................................................................................................................20
2.5.2. Edge Clock .....................................................................................................................................................20
2.6. Clock Dividers ....................................................................................................................................................21
2.7. DDRDLL ..............................................................................................................................................................22
2.8. sysMEM Memory ..............................................................................................................................................23
2.8.1. sysMEM Memory Block ................................................................................................................................23
2.8.2. Bus Size Matching .........................................................................................................................................24
2.8.3. RAM Initialization and ROM Operation ........................................................................................................24
2.8.4. Memory Cascading .......................................................................................................................................24
2.8.5. Single, Dual and Pseudo-Dual Port Modes ...................................................................................................24
2.8.6. Memory Core Reset ......................................................................................................................................25
2.9. sysDSP™ Slice ....................................................................................................................................................25
2.9.1. sysDSP Slice Approach Compared to General DSP .......................................................................................25
2.9.2. sysDSP Slice Architecture Features ...............................................................................................................26
2.10. Programmable I/O Cells ....................................................................................................................................30
2.11. PIO .....................................................................................................................................................................32
2.11.1. Input Register Block ..................................................................................................................................32
2.11.1.1. Input FIFO .............................................................................................................................................33
2.11.2. Output Register Block ...............................................................................................................................33
2.12. Tristate Register Block .......................................................................................................................................34
2.13. DDR Memory Support .......................................................................................................................................35
2.13.1. DQS Grouping for DDR Memory ...............................................................................................................35
2.13.2. DLL Calibrated DQS Delay and Control Block (DQSBUF) ...........................................................................36
2.14. sysI/O Buffer ......................................................................................................................................................38
2.14.1. sysI/O Buffer Banks...................................................................................................................................38
2.14.2. Typical sysI/O I/O Behavior during Power-up...........................................................................................39
2.14.3. Supported sysI/O Standards .....................................................................................................................39
2.14.4. On-Chip Programmable Termination .......................................................................................................40
2.14.5. Hot Socketing............................................................................................................................................40
2.15. SERDES and Physical Coding Sublayer ...............................................................................................................41
2.15.1. SERDES Block ............................................................................................................................................43
2.15.2. PCS ............................................................................................................................................................43
2.15.3. SERDES Client Interface Bus .....................................................................................................................44
2.16. Flexible Dual SERDES Architecture ....................................................................................................................44
© 2014-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2 FPGA-DS-02012-2.1
Data Sheet
2.17. IEEE 1149.1-Compliant Boundary Scan Testability ........................................................................................... 44

2.18. Device Configuration ......................................................................................................................................... 45
2.18.1. Enhanced Configuration Options ............................................................................................................. 45
2.18.1.1. TransFR (Transparent Field Reconfiguration) ...................................................................................... 45
2.18.1.2. Dual-Boot and Multi-Boot Image Support ........................................................................................... 45
2.18.2. Single Event Upset (SEU) Support ............................................................................................................ 45
2.18.3. On-Chip Oscillator .................................................................................................................................... 46
2.19. Density Shifting ................................................................................................................................................. 46
3. DC and Switching Characteristics ............................................................................................................................... 47
3.1. Absolute Maximum Ratings .............................................................................................................................. 47
3.2. Recommended Operating Conditions ............................................................................................................... 47
3.3. Power Supply Ramp Rates ................................................................................................................................ 48
3.4. Power-On-Reset Voltage Levels ........................................................................................................................ 48
3.5. Power up Sequence .......................................................................................................................................... 48
3.6. Hot Socketing Specifications ............................................................................................................................. 48
3.7. Hot Socketing Requirements............................................................................................................................. 49
3.8. ESD Performance .............................................................................................................................................. 49
3.9. DC Electrical Characteristics .............................................................................................................................. 49
3.10. Supply Current (Standby) .................................................................................................................................. 50
3.11. SERDES Power Supply Requirements1, 2, 3 ......................................................................................................... 51
3.12. sysI/O Recommended Operating Conditions .................................................................................................... 53
3.13. sysI/O Single-Ended DC Electrical Characteristics ............................................................................................. 54
3.14. sysI/O Differential Electrical Characteristics ..................................................................................................... 55
3.14.1. LVDS.......................................................................................................................................................... 55
3.14.2. SSTLD ........................................................................................................................................................ 55
3.14.3. LVCMOS33D ............................................................................................................................................. 55
3.14.4. LVDS25E .................................................................................................................................................... 56
3.14.5. BLVDS25 ................................................................................................................................................... 57
3.14.6. LVPECL33 .................................................................................................................................................. 58
3.14.7. MLVDS25 .................................................................................................................................................. 59
3.14.8. SLVS .......................................................................................................................................................... 60
3.15. Typical Building Block Function Performance ................................................................................................... 61
3.16. Derating Timing Tables...................................................................................................................................... 62
3.17. Maximum I/O Buffer Speed .............................................................................................................................. 63
3.18. External Switching Characteristics .................................................................................................................... 64
3.19. sysCLOCK PLL Timing ......................................................................................................................................... 71
3.20. SERDES High-Speed Data Transmitter ............................................................................................................... 72
3.21. SERDES/PCS Block Latency ................................................................................................................................ 73
3.22. SERDES High-Speed Data Receiver .................................................................................................................... 74
3.23. Input Data Jitter Tolerance................................................................................................................................ 74
3.24. SERDES External Reference Clock ..................................................................................................................... 75
3.25. PCI Express Electrical and Timing Characteristics ............................................................................................. 76
3.25.1. PCIe (2.5 Gb/s) AC and DC Characteristics ............................................................................................... 76
3.25.2. PCIe (5 Gb/s) – Preliminary AC and DC Characteristics ............................................................................ 77
3.26. CPRI LV2 E.48 Electrical and Timing Characteristics – Preliminary ................................................................... 79
3.27. XAUI/CPRI LV E.30 Electrical and Timing Characteristics .................................................................................. 80
3.27.1. AC and DC Characteristics ........................................................................................................................ 80
3.28. CPRI LV E.24/SGMII(2.5 Gbps) Electrical and Timing Characteristics ................................................................ 80
3.29. Gigabit Ethernet/SGMII (1.25 Gbps)/CPRI LV E.12 Electrical and Timing Characteristics ................................. 81
3.30. SMPTE SD/HD-SDI/3G-SDI (Serial Digital Interface) Electrical and Timing Characteristics ............................... 82
3.31. sysCONFIG Port Timing Specifications .............................................................................................................. 83
FPGA-DS-02012-2.1 3
Data Sheet
3.32. JTAG Port Timing Specifications ........................................................................................................................88

3.33. Switching Test Conditions .................................................................................................................................89
4. Pinout Information .....................................................................................................................................................91
4.1. Signal Descriptions ............................................................................................................................................91
4.2. PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin ........................................................94
4.3. Pin Information Summary .................................................................................................................................94
4.3.1. LFE5UM/LFE5UM5G .....................................................................................................................................94
4.3.2. LFE5U ............................................................................................................................................................96
5. Ordering Information ..................................................................................................................................................97
5.1. ECP5/ECP5-5G Part Number Description ..........................................................................................................97
5.2. Ordering Part Numbers .....................................................................................................................................98
5.2.1. Commercial ...................................................................................................................................................98
5.2.2. Industrial .....................................................................................................................................................100
Supplemental Information ................................................................................................................................................102
For Further Information ................................................................................................................................................102
Revision History ................................................................................................................................................................103
4 FPGA-DS-02012-2.1
Data Sheet
Figures
Figure 2.1. Simplified Block Diagram, LFE5UM/LFE5UM5G-85 Device (Top Level) ............................................................ 12
Figure 2.2. PFU Diagram ..................................................................................................................................................... 13
Figure 2.3. Slice Diagram .................................................................................................................................................... 14
Figure 2.4. Connectivity Supporting LUT5, LUT6, LUT7, and LUT8 ..................................................................................... 15
Figure 2.5. General Purpose PLL Diagram .......................................................................................................................... 18
Figure 2.6. LFE5UM/LFE5UM5G-85 Clocking ...................................................................................................................... 19
Figure 2.7. DCS Waveforms ................................................................................................................................................ 20
Figure 2.8. Edge Clock Sources per Bank ............................................................................................................................ 21
Figure 2.9. ECP5/ECP5-5G Clock Divider Sources ............................................................................................................... 21
Figure 2.10. DDRDLL Functional Diagram ........................................................................................................................... 22
Figure 2.11. ECP5/ECP5-5G DLL Top Level View (For LFE-45 and LFE-85) .......................................................................... 23
Figure 2.12. Memory Core Reset ........................................................................................................................................ 25
Figure 2.13. Comparison of General DSP and ECP5/ECP5-5G Approaches ........................................................................ 26
Figure 2.14. Simplified sysDSP Slice Block Diagram ............................................................................................................ 28
Figure 2.15. Detailed sysDSP Slice Diagram ........................................................................................................................ 29
Figure 2.16. Group of Four Programmable I/O Cells on Left/Right Sides ........................................................................... 31
Figure 2.17. Input Register Block for PIO on Top Side of the Device .................................................................................. 32
Figure 2.18. Input Register Block for PIO on Left and Right Side of the Device.................................................................. 32
Figure 2.19. Output Register Block on Top Side ................................................................................................................. 33
Figure 2.20. Output Register Block on Left and Right Sides ............................................................................................... 34
Figure 2.21. Tristate Register Block on Top Side ................................................................................................................ 34
Figure 2.22. Tristate Register Block on Left and Right Sides ............................................................................................... 35
Figure 2.23. DQS Grouping on the Left and Right Edges .................................................................................................... 36
Figure 2.24. DQS Control and Delay Block (DQSBUF) ......................................................................................................... 37
Figure 2.25. ECP5/ECP5-5G Device Family Banks ............................................................................................................... 38
Figure 2.26. On-Chip Termination ...................................................................................................................................... 40
Figure 2.27. SERDES/PCS Duals (LFE5UM/LFE5UM5G-85) ................................................................................................. 42
Figure 2.28. Simplified Channel Block Diagram for SERDES/PCS Block .............................................................................. 43
Figure 3.1. LVDS25E Output Termination Example ............................................................................................................ 56
Figure 3.2. BLVDS25 Multi-point Output Example ............................................................................................................. 57
Figure 3.3. Differential LVPECL33 ....................................................................................................................................... 58
Figure 3.4. MLVDS25 (Multipoint Low Voltage Differential Signaling) ............................................................................... 59
Figure 3.5. SLVS Interface ................................................................................................................................................... 60
Figure 3.6. Receiver RX.CLK.Centered Waveforms ............................................................................................................. 68
Figure 3.7. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms ......................................................................... 68
Figure 3.8. Transmit TX.CLK.Centered and DDR Memory Output Waveforms ................................................................... 68
Figure 3.9. Transmit TX.CLK.Aligned Waveforms ............................................................................................................... 69
Figure 3.10. DDRX71 Video Timing Waveforms ................................................................................................................. 69
Figure 3.11. Receiver DDRX71_RX Waveforms .................................................................................................................. 70
Figure 3.12. Transmitter DDRX71_TX Waveforms .............................................................................................................. 70
Figure 3.13. Transmitter and Receiver Latency Block Diagram .......................................................................................... 73
Figure 3.14. SERDES External Reference Clock Waveforms ............................................................................................... 75
Figure 3.15. sysCONFIG Parallel Port Read Cycle................................................................................................................ 84
Figure 3.16. sysCONFIG Parallel Port Write Cycle............................................................................................................... 85
Figure 3.17. sysCONFIG Slave Serial Port Timing ................................................................................................................ 85
Figure 3.18. Power-On-Reset (POR) Timing ........................................................................................................................ 86
Figure 3.19. sysCONFIG Port Timing ................................................................................................................................... 86
Figure 3.20. Configuration from PROGRAMN Timing ......................................................................................................... 87
Figure 3.21. Wake-Up Timing ............................................................................................................................................. 87
Figure 3.22. Master SPI Configuration Waveforms ............................................................................................................ 88
Figure 3.23. JTAG Port Timing Waveforms ......................................................................................................................... 89
Figure 3.24. Output Test Load, LVTTL and LVCMOS Standards .......................................................................................... 89
FPGA-DS-02012-2.1 5
Data Sheet
Tables
Table 1.1. ECP5 and ECP5-5G Family Selection Guide ........................................................................................................10
Table 2.1. Resources and Modes Available per Slice ..........................................................................................................13
Table 2.2. Slice Signal Descriptions .....................................................................................................................................15
Table 2.3. Number of Slices Required to Implement Distributed RAM ..............................................................................16
Table 2.4. PLL Blocks Signal Descriptions ............................................................................................................................18
Table 2.5. DDRDLL Ports List ...............................................................................................................................................22
Table 2.6. sysMEM Block Configurations ............................................................................................................................24
Table 2.7. Maximum Number of Elements in a Slice ..........................................................................................................30
Table 2.8. Input Block Port Description ..............................................................................................................................33
Table 2.9. Output Block Port Description ...........................................................................................................................34
Table 2.10. Tristate Block Port Description.........................................................................................................................35
Table 2.11. DQSBUF Port List Description...........................................................................................................................37
Table 2.12. On-Chip Termination Options for Input Modes ...............................................................................................40
Table 2.13. LFE5UM/LFE5UM5G SERDES Standard Support ..............................................................................................42
Table 2.14. Available SERDES Duals per LFE5UM/LFE5UM5G Devices ...............................................................................43
Table 2.15. LFE5UM/LFE5UM5G Mixed Protocol Support .................................................................................................44
Table 2.16. Selectable Master Clock (MCLK) Frequencies during Configuration (Nominal) ...............................................46
Table 3.1. Absolute Maximum Ratings ...............................................................................................................................47
Table 3.2. Recommended Operating Conditions ................................................................................................................47
Table 3.3. Power Supply Ramp Rates .................................................................................................................................48
Table 3.4. Power-On-Reset Voltage Levels .........................................................................................................................48
Table 3.5. Hot Socketing Specifications ..............................................................................................................................48
Table 3.6. Hot Socketing Requirements..............................................................................................................................49
Table 3.7. DC Electrical Characteristics ...............................................................................................................................49
Table 3.8. ECP5/ECP5-5G Supply Current (Standby) ...........................................................................................................50
Table 3.9. ECP5UM .............................................................................................................................................................51
Table 3.10. ECP5-5G ............................................................................................................................................................52
Table 3.11. sysI/O Recommended Operating Conditions ...................................................................................................53
Table 3.12. Single-Ended DC Characteristics ......................................................................................................................54
Table 3.13. LVDS .................................................................................................................................................................55
Table 3.14. LVDS25E DC Conditions ....................................................................................................................................56
Table 3.15. BLVDS25 DC Conditions ...................................................................................................................................57
Table 3.16. LVPECL33 DC Conditions ..................................................................................................................................58
Table 3.17. MLVDS25 DC Conditions ..................................................................................................................................59
Table 3.18. Input to SLVS ....................................................................................................................................................60
Table 3.19. Pin-to-Pin Performance ....................................................................................................................................61
Table 3.20. Register-to-Register Performance....................................................................................................................62
Table 3.21. ECP5/ECP5-5G Maximum I/O Buffer Speed .....................................................................................................63
Table 3.22. ECP5/ECP5-5G External Switching Characteristics ...........................................................................................64
Table 3.23. sysCLOCK PLL Timing ........................................................................................................................................71
Table 3.24. Serial Output Timing and Levels .......................................................................................................................72
Table 3.25. Channel Output Jitter .......................................................................................................................................72
Table 3.26. SERDES/PCS Latency Breakdown .....................................................................................................................73
Table 3.27. Serial Input Data Specifications........................................................................................................................74
Table 3.28. Receiver Total Jitter Tolerance Specification ...................................................................................................74
Table 3.29. External Reference Clock Specification (refclkp/refclkn) .................................................................................75
Table 3.30. PCIe (2.5 Gb/s) .................................................................................................................................................76
Table 3.31. PCIe (5 Gb/s) ....................................................................................................................................................77
Table 3.32. CPRI LV2 E.48 Electrical and Timing Characteristics .........................................................................................79
Table 3.33. Transmit ...........................................................................................................................................................80
Table 3.34. Receive and Jitter Tolerance ............................................................................................................................80
Table 3.35. Transmit ...........................................................................................................................................................80
6 FPGA-DS-02012-2.1
Data Sheet
Table 3.36. Receive and Jitter Tolerance ............................................................................................................................ 81

Table 3.37. Transmit ........................................................................................................................................................... 81
Table 3.38. Receive and Jitter Tolerance ............................................................................................................................ 81
Table 3.39. Transmit ........................................................................................................................................................... 82
Table 3.40. Receive ............................................................................................................................................................. 82
Table 3.41. Reference Clock ............................................................................................................................................... 82
Table 3.42. ECP5/ECP5-5G sysCONFIG Port Timing Specifications ..................................................................................... 83
Table 3.43. JTAG Port Timing Specifications ....................................................................................................................... 88
Table 3.44. Test Fixture Required Components, Non-Terminated Interfaces .................................................................... 90
FPGA-DS-02012-2.1 7
Data Sheet
Acronyms in This Document

A list of acronyms used in this document.
Acronym Definition
ALU Arithmetic Logic Unit
BGA Ball Grid Array
CDR Clock and Data Recovery
CRC Cycle Redundancy Code
DCC Dynamic Clock Control
DCS Dynamic Clock Select
DDR Double Data Rate
DLL Delay-Locked Loops
DSP Digital Signal Processing
EBR Embedded Block RAM
ECLK Edge Clock
FFT Fast Fourier Transforms
FIFO First In First Out
FIR Finite Impulse Response
LVCMOS Low-Voltage Complementary Metal Oxide Semiconductor
LVDS Low-Voltage Differential Signaling
LVPECL Low Voltage Positive Emitter Coupled Logic
LVTTL Low Voltage Transistor-Transistor Logic
LUT Look Up Table
MLVDS Multipoint Low-Voltage Differential Signaling
PCI Peripheral Component Interconnect
PCS Physical Coding Sublayer
PCLK Primary Clock
PDPR Pseudo Dual Port RAM
PFU Programmable Functional Unit
PIC Programmable I/O Cells
PLL Phase-Locked Loops
POR Power On Reset
SCI SERDES Client Interface
SERDES Serializer/Deserializer
SEU Single Event Upset
SLVS Scalable Low-Voltage Signaling
SPI Serial Peripheral Interface
SPR Single Port RAM
SRAM Static Random-Access Memory
TAP Test Access Port
TDM Time Division Multiplexing
8 FPGA-DS-02012-2.1
Data Sheet
The Lattice Diamond™ design software allows large

1. General Description complex designs to be efficiently implemented using
The ECP5™/ECP5-5G™ family of FPGA devices is the ECP5/ECP5-5G FPGA family. Synthesis library
optimized to deliver high performance features such as support for ECP5/ECP5-5G devices is available for
an enhanced DSP architecture, high speed SERDES popular logic synthesis tools. The Diamond tools use
(Serializer/Deserializer), and high speed source the synthesis tool output along with the constraints
synchronous interfaces, in an economical FPGA fabric. from its floor planning tools to place and route the
This combination is achieved through advances in design in the ECP5/ECP5-5G device. The tools extract
device architecture and the use of 40 nm technology the timing from the routing and back-annotate it into
making the devices suitable for high-volume, high- the design for timing verification.
speed, and low-cost applications. Lattice provides many pre-engineered IP (Intellectual
The ECP5/ECP5-5G device family covers look-up-table Property) modules for the ECP5/ECP5-5G family. By
(LUT) capacity to 84K logic elements and supports up using these configurable soft core IPs as standardized
to 365 user I/O. The ECP5/ECP5-5G device family also blocks, designers are free to concentrate on the unique
offers up to 156 18 x 18 multipliers and a wide range of aspects of their design, increasing their productivity.
parallel I/O standards.
The ECP5/ECP5-5G FPGA fabric is optimized high
performance with low power and low cost in mind. The
1.1. Features
ECP5/ ECP5-5G devices utilize reconfigurable SRAM  Higher Logic Density for Increased System
logic technology and provide popular building blocks Integration
such as LUT-based logic, distributed and embedded  12K to 84K LUTs
memory, Phase-Locked Loops (PLLs), Delay-Locked  197 to 365 user programmable I/O
Loops (DLLs), pre-engineered source synchronous I/O  Embedded SERDES
support, enhanced sysDSP slices and advanced  270 Mb/s, up to 3.2 Gb/s, SERDES interface
configuration support, including encryption and (ECP5)
dual-boot capabilities.  270 Mb/s, up to 5.0 Gb/s, SERDES interface
The pre-engineered source synchronous logic (ECP5-5G)
implemented in the ECP5/ECP5-5G device family  Supports eDP in RDR (1.62 Gb/s) and HDR
supports a broad range of interface standards (2.7 Gb/s)
including DDR2/3, LPDDR2/3, XGMII, and 7:1 LVDS.
 Up to four channels per device: PCI Express,
The ECP5/ECP5-5G device family also features high Ethernet (1GbE, SGMII, XAUI), and CPRI
speed SERDES with dedicated Physical Coding Sublayer  sysDSP™
(PCS) functions. High jitter tolerance and low transmit
 Fully cascadable slice architecture
jitter allow the SERDES plus PCS blocks to be
 12 to 160 slices for high performance multiply
configured to support an array of popular data
and accumulate
protocols including PCI Express, Ethernet (XAUI, GbE,
and SGMII) and CPRI. Transmit De-emphasis with  Powerful 54-bit ALU operations
pre- and post-cursors, and Receive Equalization  Time Division Multiplexing MAC Sharing
settings make the SERDES suitable for transmission and  Rounding and truncation
reception over various forms of media.  Each slice supports
The ECP5/ECP5-5G devices also provide flexible,  Half 36 x 36, two 18 x 18 or four
reliable and secure configuration options, such as 9 x 9 multipliers
dual-boot capability, bit-stream encryption, and  Advanced 18 x 36 MAC and
TransFR field upgrade features. 18 x 18 Multiply-Multiply-Accumulate
ECP5-5G family devices have made some enhancement (MMAC) operations
in the SERDES compared to ECP5UM devices. These  Flexible Memory Resources
enhancements increase the performance of the  Up to 3.744 Mb sysMEM™ Embedded Block
SERDES to up to 5 Gb/s data rate. RAM (EBR)
The ECP5-5G family devices are pin-to-pin compatible  194K to 669K bits distributed RAM
with the ECP5UM devices. These allows a migration
path for you to port designs from ECP5UM to ECP5-5G
devices to get higher performance.
FPGA-DS-02012-2.1 9
Data Sheet
 sysCLOCK Analog PLLs and DLLs  Flexible Device Configuration

 Four DLLs and four PLLs in LFE5-45 and  Shared bank for configuration I/O
LFE5-85; two DLLs and two PLLs in LFE5-25  SPI boot flash interface
and LFE5-12  Dual-boot images supported
 Pre-Engineered Source Synchronous I/O  Slave SPI
 DDR registers in I/O cells  TransFR™ I/O for simple field updates
 Dedicated read/write levelling functionality  Single Event Upset (SEU) Mitigation Support
 Dedicated gearing logic  Soft Error Detect – Embedded hard macro
 Source synchronous standards support  Soft Error Correction – Without stopping user
 ADC/DAC, 7:1 LVDS, XGMII operation
 High Speed ADC/DAC devices  Soft Error Injection – Emulate SEU event to
 Dedicated DDR2/DDR3 and LPDDR2/LPDDR3 debug system error handling
memory support with DQS logic, up to  System Level Support
800 Mb/s data-rate  IEEE 1149.1 and IEEE 1532 compliant
 Programmable sysI/O™ Buffer Supports Wide  Reveal Logic Analyzer
Range of Interfaces  On-chip oscillator for initialization and general
 On-chip termination use
 LVTTL and LVCMOS 33/25/18/15/12  1.1 V core power supply for ECP5, 1.2 V core
 SSTL 18/15 I, II power supply for ECP5UM5G
 HSUL12
 LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS
 subLVDS and SLVS, SoftIP MIPI D-PHY
receiver/transmitter interfaces
Table 1.1. ECP5 and ECP5-5G Family Selection Guide
LFE5UM-25 LFE5UM-45 LFE5UM-85 LFE5U- LFE5U- LFE5U- LFE5U-
Device
LFE5UM5G-25 LFE5UM5G-45 LFE5UM5G-85 12 25 45 85
LUTs (K) 24 44 84 12 24 44 84
sysMEM Blocks (18 Kb) 56 108 208 32 56 108 208
Embedded Memory (Kb) 1,008 1944 3744 576 1,008 1944 3744
Distributed RAM Bits (Kb) 194 351 669 97 194 351 669
18 X 18 Multipliers 28 72 156 28 28 72 156
SERDES (Dual/Channels) 1/2 2/4 2/4 0 0 0 0
PLLs/DLLs 2/2 4/4 4/4 2/2 2/2 4/4 4/4
Packages (SERDES Channels / I/O Count)
256 caBGA
— — — 0/197 0/197 0/197 —
(14 x 14 mm2, 0.8 mm)
285 csfBGA
2/118 2/118 2/118 0/118 0/118 0/118 0/118
(10 x 10 mm2, 0.5 mm)
381 caBGA
2/197 4/203 4/205 0/197 0/197 0/203 0/205
(17 x 17 mm2, 0.8 mm)
554 caBGA
— 4/245 4/259 — — 0/245 0/259
(23 x 23 mm2, 0.8 mm)
756 caBGA
— — 4/365 — — — 0/365
(27 x 27 mm2, 0.8 mm)
10 FPGA-DS-02012-2.1
Data Sheet
2. Architecture
2.1. Overview
Each ECP5/ECP5-5G device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Interspersed
between the rows of logic blocks are rows of sysMEM™ Embedded Block RAM (EBR) and rows of sysDSP™ Digital Signal
Processing slices, as shown in Figure 2.1. The LFE5-85 devices have three rows of DSP slices, the LFE5-45 devices have
two rows, and both LFE5-25 and LFE5-12 devices have one. In addition, the LFE5UM/LFE5UM5G devices contain
SERDES Duals on the bottom of the device.
The Programmable Functional Unit (PFU) contains the building blocks for logic, arithmetic, RAM, and ROM functions.
The PFU block is optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic
Blocks are arranged in a two-dimensional array.
The ECP5/ECP5-5G devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large, dedicated 18 Kb
fast memory blocks. Each sysMEM block can be configured in a variety of depths and widths as RAM or ROM. In
addition, ECP5/ECP5-5G devices contain up to three rows of DSP slices. Each DSP slice has multipliers and
adder/accumulators, which are the building blocks for complex signal processing capabilities.
The ECP5 devices feature up to four embedded 3.2 Gb/s SERDES channels, and the ECP5-5G devices feature up to four
embedded 5 Gb/s SERDES channels. Each SERDES channel contains independent 8b/10b encoding / decoding, polarity
adjust and elastic buffer logic. Each group of two SERDES channels, along with its Physical Coding Sublayer (PCS) block,
creates a dual DCU (Dual Channel Unit). The functionality of the SERDES/PCS duals can be controlled by SRAM cell
settings during device configuration or by registers that are addressable during device operation. The registers in every
dual can be programmed via the SERDES Client Interface (SCI). These DCUs (up to two) are located at the bottom of the
devices.
Each PIC block encompasses two PIOs (PIO pairs) with their respective sysI/O buffers. The sysI/O buffers of the
ECP5/ECP5-5G devices are arranged in seven banks (eight banks for LFE5-85 devices in caBGA756 and caBGA554
packages), allowing the implementation of a wide variety of I/O standards. One of these banks (Bank 8) is shared with
the programming interfaces. Half of the PIO pairs on the left and right edges of the device can be configured as LVDS
transmit pairs, and all pairs on left and right can be configured as LVDS receive pairs. The PIC logic in the left and right
banks also includes pre-engineered support to aid in the implementation of high speed source synchronous standards
such as XGMII, 7:1 LVDS, along with memory interfaces including DDR3 and LPDDR3.
The ECP5/ECP5-5G registers in PFU and sysI/O can be configured to be SET or RESET. After power up and the device is
configured, it enters into user mode with these registers SET/RESET according to the configuration setting, allowing the
device entering to a known state for predictable system function.
Other blocks provided include PLLs, DLLs and configuration functions. The ECP5/ECP5-5G architecture provides up to
four Delay-Locked Loops (DLLs) and up to four Phase-Locked Loops (PLLs). The PLL and DLL blocks are located at the
corners of each device.
The configuration block that supports features such as configuration bit-stream decryption, transparent updates and
dual-boot support is located at the bottom of each device, to the left of the SERDES blocks. Every device in the
ECP5/ECP5-5G family supports a sysCONFIG™ ports located in that same corner, powered by VCCIO8, allowing for serial
or parallel device configuration.
In addition, every device in the family has a JTAG port. This family also provides an on-chip oscillator and soft error
detect capability. The ECP5 devices use 1.1 V and ECP5UM5G devices use 1.2 V as their core voltage.
FPGA-DS-02012-2.1 11
Data Sheet
Figure 2.1. Simplified Block Diagram, LFE5UM/LFE5UM5G-85 Device (Top Level)
2.2. PFU Blocks

The core of the ECP5/ECP5-5G device consists of PFU blocks. Each PFU block consists of four interconnected slices
numbered 0-3, as shown in Figure 2.2. Each slice contains two LUTs. All the interconnections to and from PFU blocks
are from routing. There are 50 inputs and 23 outputs associated with each PFU block.
The PFU block can be used in Distributed RAM or ROM function, or used to perform Logic, Arithmetic, or ROM
functions. Table 2.1 shows the functions each slice can perform in either mode.
12 FPGA-DS-02012-2.1
Data Sheet
Figure 2.2. PFU Diagram
2.2.1. Slice
Each slice contains two LUT4s feeding two registers. In Distributed SRAM mode, Slice 0 through Slice 2 are configured
as distributed memory, and Slice 3 is used as Logic or ROM. Table 2.1 shows the capability of the slices along with the
operation modes they enable. In addition, each PFU contains logic that allows the LUTs to be combined to perform
functions such as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (programmable as
synchronous/ asynchronous), clock select, chip-select and wider RAM/ROM functions.
Table 2.1. Resources and Modes Available per Slice
PFU (Used in Distributed SRAM) PFU (Not used as Distributed SRAM)
Slice
Resources Modes Resources Modes
Slice 0 2 LUT4s and 2 Registers RAM 2 LUT4s and 2 Registers Logic, Ripple, ROM
Slice 3 2 LUT4s and 2 Registers Logic, Ripple, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM
Figure 2.3 shows an overview of the internal logic of the slice. The registers in the slice can be configured for
positive/negative and edge triggered or level sensitive clocks.
Each slice has 14 input signals, 13 signals from routing and one from the carry-chain (from the adjacent slice or PFU).
There are five outputs, four to routing and one to carry-chain (to the adjacent PFU). There are two inter slice/ PFU
output signals that are used to support wider LUT functions, such as LUT6, LUT7, and LUT8. Table 2.2 and Figure 2.3 list
the signals associated with all the slices. Figure 2.4 shows the connectivity of the inter-slice/PFU signals that support
LUT5, LUT6, LUT7, and LUT8.
FPGA-DS-02012-2.1 13
Data Sheet
FCO
FXA
FXB
M1
M0
A1
B1 LUT4 &
C1 CARRY*
D1
F1
F1
FF
Q1
A0
B0 LUT4 &
C0 CARRY*
D0
F0
F0
FF
Q0
CE
CLK
LSR
FCI From Different Slice/PFU
Notes: For Slices 0 and 1, memory control signals are generated from Slice 2 as follows:
WCK is CLK
WRE is from LSR
DI[3:2] for Slice 1 and DI[1:0] for Slice 0 data from Slice 2
WAD [A:D] is a 4-bit address from slice 2 LUT input
Figure 2.3. Slice Diagram
14 FPGA-DS-02012-2.1
Data Sheet
PFU Col(n-1) PFU Col(n) PFU Col(n+1)

A1 A1 A1
LUT8 LUT8 LUT8
B1 F1 B1 F1 B1 F1
C1 C1 C1
3
3
D1 Q1 D1 Q1 D1 Q1
A0 A0 A0
B0 LUT5
SLICE
B0 LUT5 B0 LUT5
SLICE
SLICE
C0 F0 C0 F0 C0 F0
D0 D0 D0
FXB Q0 FXB Q0 FXB Q0
LUT7 Output FXA FXA FXA LUT7 Output
To Next PFU From Previous PFU
A1 A1 LUT6 A1
LUT6 LUT6
B1 F1 B1 F1 B1 F1
C1 C1 C1
2
2
D1 Q1 D1 Q1 D1 Q1
A0 A0 A0
LUT5 B0 LUT5 LUT5
SLICE
B0 B0
SLICE
SLICE
C0 F0 C0 F0 C0 F0
D0 D0 D0
FXA FXA FXA
A1 A1 A1
LUT7 LUT7 LUT7
B1 F1 B1 F1 B1 F1
C1 C1 C1
1
1
D1 Q1 D1 Q1 D1 Q1
A0 A0 A0
B0 LUT5
SLICE
B0 LUT5 B0 LUT5
SLICE
SLICE
C0 F0 C0 F0 C0 F0
D0 D0 D0
FXA FXA FXA
A1 A1 LUT6 A1
LUT6 LUT6
B1 F1 B1 F1 B1 F1
C1 C1 C1
0
0
0
D1 Q1 D1 Q1 D1 Q1
A0 A0 A0
LUT5 B0 LUT5 LUT5
SLICE
B0 B0
SLICE
SLICE
C0 F0 C0 F0 C0 F0
D0 D0 D0
FXA FXA FXA
Figure 2.4. Connectivity Supporting LUT5, LUT6, LUT7, and LUT8
Table 2.2. Slice Signal Descriptions

Function Type Signal Names Description
Input Data signal A0, B0, C0, D0 Inputs to LUT4
Input Data signal A1, B1, C1, D1 Inputs to LUT4
Input Multi-purpose M0 Multipurpose Input
Input Multi-purpose M1 Multipurpose Input
Input Control signal CE Clock Enable
Input Control signal LSR Local Set/Reset
Input Control signal CLK System Clock
Input Inter-PFU signal FCI Fast Carry-in1
Input Inter-slice signal FXA Intermediate signal to generate LUT6, LUT7 and LUT82
Input Inter-slice signal FXB Intermediate signal to generate LUT6, LUT7 and LUT82
Output Data signals F0, F1 LUT4 output register bypass signals
Output Data signals Q0, Q1 Register outputs
Output Inter-PFU signal FCO Fast carry chain output1
Notes:
1. See Figure 2.3 for connection details.
2. Requires two adjacent PFUs.
FPGA-DS-02012-2.1 15
Data Sheet
2.2.2. Modes of Operation

Slices 0-2 have up to four potential modes of operation: Logic, Ripple, RAM, and ROM. Slice 3 is not needed for RAM
mode, it can be used in Logic, Ripple, or ROM modes.
2.2.2.1. Logic Mode

In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16 possible
input combinations. Any four input logic functions can be generated by programming this lookup table. Since there are
two LUT4s per slice, a LUT5 can be constructed within one slice. Larger look-up tables such as LUT6, LUT7, and LUT8
can be constructed by concatenating other slices. Note that LUT8 requires more than four slices.
2.2.2.2. Ripple Mode

Ripple mode supports the efficient implementation of small arithmetic functions. In ripple mode, the following
functions can be implemented by each slice:
 Addition 2-bit
 Subtraction 2-bit
 Add/Subtract 2-bit using dynamic control
 Up counter 2-bit
 Down counter 2-bit
 Up/Down counter with asynchronous clear
 Up/Down counter with preload (sync)
 Ripple mode multiplier building block
 Multiplier support
 Comparator functions of A and B inputs
 A greater-than-or-equal-to B
 A not-equal-to B
 A less-than-or-equal-to B
Ripple Mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this
configuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are
generated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating Slices.
2.2.2.3. RAM Mode

In this mode, a 16 x 4-bit distributed single port RAM (SPR) can be constructed in one PFU using each LUT block in Slice
0 and Slice 1 as a 16 x 2-bit memory in each slice. Slice 2 is used to provide memory address and control signals.
A 16 x 2-bit pseudo dual port RAM (PDPR) memory is created in one PFU by using one Slice as the read-write port and
the other companion slice as the read-only port. The slice with the read-write port updates the SRAM data contents in
both slices at the same write cycle.
ECP5/ECP5-5G devices support distributed memory initialization.
The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the software
constructs these using distributed memory primitives that represent the capabilities of the PFU. Table 2.3 lists the
number of slices required to implement different distributed RAM primitives. For more information about using RAM in
ECP5/ECP5-5G devices, refer to ECP5 and ECP5-5G Memory Usage Guide (TN1264).
Table 2.3. Number of Slices Required to Implement Distributed RAM
RAM Number of Slices
SPR 16 X 4 3
PDPR 16 X 4 6
Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM
16 FPGA-DS-02012-2.1
Data Sheet
2.2.2.4. ROM Mode

ROM mode uses the LUT logic; hence, Slices 0 through 3 can be used in ROM mode. Preloading is accomplished
through the programming interface during PFU configuration.
For more information, refer to ECP5 and ECP5-5G Memory Usage Guide (TN1264).
2.3. Routing
There are many resources provided in the ECP5/ECP5-5G devices to route signals individually or as busses with related
control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments.
The ECP5/ECP5-5G family has an enhanced routing architecture that produces a compact design. The Diamond design
software tool suites take the output of the synthesis tool and places and routes the design.
2.4. Clocking Structure

ECP5/ECP5-5G clocking structure consists of clock synthesis blocks (sysCLOCK PLL); balanced clock tree networks (PCLK
and ECLK trees); and efficient clock logic modules (CLOCK DIVIDER and Dynamic Clock Select (DCS), Dynamic Clock
Control (DCC) and DLL). All of these functions are described below.
2.4.1. sysCLOCK PLL

The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The devices in the ECP5/ECP5-5G family support
two to four full-featured General Purpose PLLs. The sysCLOCK PLLs provide the ability to synthesize clock frequencies.
The architecture of the PLL is shown in Figure 2.5. A description of the PLL functionality follows.
CLKI is the reference frequency input to the PLL and its source can come from two different external CLK inputs or from
internal routing. A non-glitchless 2-to-1 input multiplexor is provided to dynamically select between two different
external reference clock sources. The CLKI input feeds into the input Clock Divider block.
CLKFB is the feedback signal to the PLL which can come from internal feedback path, routing or an external I/O pin. The
feedback divider is used to multiply the reference frequency and thus synthesize a higher frequency clock output.
The PLL has four clock outputs CLKOP, CLKOS, CLKOS2 and CLKOS3. Each output has its own output divider, thus
allowing the PLL to generate different frequencies for each output. The output dividers can have a value from 1 to 128.
The CLKOP, CLKOS, CLKOS2, and CLKOS3 outputs can all be used to drive the primary clock network. Only CLKOP and
CLKOS outputs can go to the edge clock network.
The setup and hold times of the device can be improved by programming a phase shift into the CLKOS, CLKOS2, and
CLKOS3 output clocks which advances or delays the output clock with reference to the CLKOP output clock. This phase
shift can be either programmed during configuration or can be adjusted dynamically using the PHASESEL, PHASEDIR,
PHASESTEP, and PHASELOADREG ports.
The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is detected.
FPGA-DS-02012-2.1 17
Data Sheet
PHASESEL[1:0] Dynamic
PHASEDIR Phase
PHASESTEP Adjust
PHASELOADREG
PLLREFCS
CLKOP
SEL VCO
Refclk Divider CLKOP
CLK0
(1-128 )
CLKI PLLCSOUT
CLKI2 Refclk Divider M Phase CLKOS
CLKI Detector, VCO
CLK1 Divider CLKOS
VCO, and (1-128 )
Loop Filter
FBKSEL VCO CLKOS2
CLKFB Feedback Divider CLKOS2
Clock Divider (1-128 )
VCO CLKOS3
Internal Feedback Divider CLKOS3
CLKOP, CLKOS, CLKOS2, CLKOS3 (1-128 )
ENCLKOP
ENCLKOS
ENCLKOS2
ENCLKOS3
RST Lock LOCK
STDBY Detect
Figure 2.5. General Purpose PLL Diagram
Table 2.4 provides a description of the signals in the PLL blocks.

Table 2.4. PLL Blocks Signal Descriptions
Signal Type Description
CLKI Input Clock Input to PLL from external pin or routing
CLKI2 Input Mixed clock input to PLL
SEL Input Input Clock select, selecting from CLKI and CLKI2 inputs
CLKFB Input PLL Feedback Clock
PHASESEL[1:0] Input Select which output to be adjusted on Phase by PHASEDIR, PHASESTEP, PHASELODREG
PHASEDIR Input Dynamic Phase adjustment direction.
PHASESTEP Input Dynamic Phase adjustment step.
PHASELOADREG Input Load dynamic phase adjustment values into PLL.
CLKOP Output Primary PLL output clock (with phase shift adjustment)
CLKOS Output Secondary PLL output clock (with phase shift adjust)
CLKOS2 Output Secondary PLL output clock2 (with phase shift adjust)
CLKOS3 Output Secondary PLL output clock3 (with phase shift adjust)
LOCK Output PLL LOCK to CLKI, Asynchronous signal. Active high indicates PLL lock
STDBY Input Standby signal to power down the PLL
RST Input Resets the PLL
ENCLKOP Input Enable PLL output CLKOP
ENCLKOS Input Enable PLL output CLKOS
ENCLKOS2 Input Enable PLL output CLKOS2
ENCLKOS3 Input Enable PLL output CLKOS3
For more details on the PLL, you can refer to the ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide
(TN1263).
18 FPGA-DS-02012-2.1
Data Sheet
2.5. Clock Distribution Network

There are two main clock distribution networks for any member of the ECP5/ECP5-5G product family, namely Primary
Clock (PCLK) and Edge Clock (ECLK). These clock networks have the clock sources come from many different sources,
such as Clock Pins, PLL outputs, DLLDEL outputs, Clock divider outputs, SERDES/PCS clocks and some on chip generated
clock signal. There are clock dividers (CLKDIV) blocks to provide the slower clock from these clock sources.
ECP5/ECP5-5G also supports glitchless dynamic enable function (DCC) for the PCLK Clock to save dynamic power. There
are also some logics to allow dynamic glitchless selection between two clocks for the PCLK network (DCS).
Overview of Clocking Network is shown in Figure 2.6 for LFE5UM/LFE5UM5G-85 device.
PIO PIO PIO PIO

DLL
Bank 0 Mid Bank 1 DLL
MUX
Edge Clocks
PLL PLL
Edge Clocks
Bank 2
12 DCC
Bank 7
Quadrant TL 12 Primary Sources Quadrant TR

Primary Primary
Clocks 16 Fabric Fabric 16 Clocks
Entry Entry
PIO
PIO
14 Primary Sources
PIO
PIO
CLK
DIV Mid 14 14 Primary Sources 14 Mid
CLK
DIV
MUX
14 DCC Center MUX 14 DCC MUX
CLK CLK
PIO
PIO
DIV DIV
PIO
PIO
16 Fabric Fabric
16
Primary Entry Entry Primary
Bank 3
Clocks 16 Primary Sources Clocks
Edge Clocks
Bank 6
Edge Clocks
Quadrant BL 16 DCC
Quadrant BR
PLL PLL
Mid
MUX
DLL PCSCLKDIV PCSCLKDIV DLL

Bank 8 Bank 4
SERDES DCU0 SERDES DCU1
Figure 2.6. LFE5UM/LFE5UM5G-85 Clocking
2.5.1. Primary Clocks

The ECP5/ECP5-5G device family provides low-skew, high fan-out clock distribution to all synchronous elements in the
FPGA fabric through the Primary Clock Network.
The primary clock network is divided into four clocking quadrants: Top Left (TL), Bottom Left (BL), Top Right (TR), and
Bottom Right (BR). Each of these quadrants has 16 clocks that can be distributed to the fabric in the quadrant.
The Lattice Diamond software can automatically route each clock to one of the four quadrants up to a maximum of 16
clocks per quadrant. You can change how the clocks are routed by specifying a preference in the Lattice Diamond
software to locate the clock to specific. The ECP5/ECP5-5G device provides you with a maximum of 64 unique clock
input sources that can be routed to the primary Clock network.
Primary clock sources are:
 Dedicated clock input pins
 PLL outputs
 CLKDIV outputs
 Internal FPGA fabric entries (with minimum general routing)
 SERDES/PCS/PCSDIV clocks
 OSC clock
These sources are routed to one of four clock switches called a Mid Mux. The outputs of the Mid MUX are routed to
the center of the FPGA where another clock switch, called the Center MUX, is used to route the primary clock sources
to primary clock distribution to the ECP5/ECP5-5G fabric. These routing muxes are shown in Figure 2.6. Since there is a
maximum of 60 unique clock input sources to the clocking quadrants, there are potentially 64 unique clock domains
that can be used in the ECP5/ECP5-5G Device. For more information about the primary clock tree and connections,
refer to ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide (TN1263).
FPGA-DS-02012-2.1 19
Data Sheet
2.5.1.1. Dynamic Clock Control

The Dynamic Clock Control (DCC), Quadrant Clock enable/disable feature allows internal logic control of the quadrant
primary clock network. When a clock network is disabled, the clock signal is static and not toggle. All the logic fed by
that clock does not toggle, reducing the overall power consumption of the device. The disable function does not create
glitch and increase the clock latency to the primary clock network.
This DCC controls the clock sources from the Primary CLOCK MIDMUX before they are fed to the Primary Center MUXs
that drive the quadrant clock network. For more information about the DCC, refer to ECP5 and ECP5-5G sysClock
PLL/DLL Design and Usage Guide (TN1263).
2.5.1.2. Dynamic Clock Select

The Dynamic Clock Select (DCS) is a smart multiplexer function available in the primary clock routing. It switches
between two independent input clock sources. Depending on the operation modes, it switches between two (2)
independent input clock sources either with or without any glitches. This is achieved regardless of when the select
signal is toggled. Both input clocks must be running to achieve functioning glitch-less DCS output clock, but it is not
required running clocks when used as non-glitch-less normal clock multiplexer.
There are two DCS blocks per device that are fed to all quadrants. The inputs to the DCS block come from all the output
of MIDMUXs and Clock from CIB located at the center of the PLC array core. The output of the DCS is connected to one
of the inputs of Primary Clock Center MUX.
Figure 2.7 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed to other
modes. For more information about the DCS, refer to ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide
(TN1263).
CLK0
CLK1
SEL
CLKO
Figure 2.7. DCS Waveforms
2.5.2. Edge Clock

ECP5/ECP5-5G devices have a number of high-speed edge clocks that are intended for use with the PIOs in the
implementation of high-speed interfaces. There are two ECLK networks per bank I/O on the Left and Right sides of the
devices.
Each Edge Clock can be sourced from the following:
 Dedicated Clock input pins (PCLK)
 DLLDEL output (Clock delayed by 90o)
 PLL outputs (CLKOP and CLKOS)
 ECLKBRIDGE
 Internal Nodes
20 FPGA-DS-02012-2.1
Data Sheet
Top Left / Right PCLK Pin From ECLK of

other bank on
Top Left / Right DLLDEL Output same side
Top Right / Left PLL CLKOP

From
Top Right / Left PLL CLKOS ECLKBRIDGE
ECLK Tree
ECLKSYNC
Bottom Right / Left PLL CLKOP
Bottom Right / Left PLL CLKOS
Bottom Left / Right PCLK Pin

To ECLK of other
Bottom Left / Right DLLDEL Output bank on same side
To ECLKBRIDGE
to go to other side
From Routing
Figure 2.8. Edge Clock Sources per Bank
The edge clocks have low injection delay and low skew. They are used for DDR Memory or Generic DDR interfaces. For
detailed information on Edge Clock connections, refer to ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide
(TN1263).
2.6. Clock Dividers

ECP5/ECP5-5G devices have two clock dividers, one on the left side and one on the right side of the device. These are
intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2, ÷3.5 mode
and maintains a known phase relationship between the divided down clock and the high-speed clock based on the
release of its reset signal.
The clock dividers can be fed from selected PLL outputs, external primary clock pins multiplexed with the DDRDEL Slave
Delay or from routing. The clock divider outputs serve as primary clock sources and feed into the clock distribution
network. The Reset (RST) control signal resets input and asynchronously forces all outputs to low. The SLIP signal slips
the outputs one cycle relative to the input clock. For further information on clock dividers, refer to ECP5 and ECP5-5G
sysClock PLL/DLL Design and Usage Guide (TN1263). Figure 2.9 shows the clock divider connections.
Primary Clock Pin OR

DLLDEL output clock
PLL clock output CLKDIV To Primary Clock Tree

(CLKOP/CLKOS) (/2 or /3.5) OR Routing
Primary
Clock Tree
OR Routing RST
SLIP
Figure 2.9. ECP5/ECP5-5G Clock Divider Sources
FPGA-DS-02012-2.1 21
Data Sheet
2.7. DDRDLL
Every DDRDLL (master DLL block) can generate phase shift code representing the amount of delay in a delay block that
corresponding to 90° phase of the reference clock input. The reference clock can be either from PLL, or input pin. This
code is used in the DQSBUF block that controls a set of DQS pin groups to interface with DDR memory (slave DLL).
There are two DDRDLLs that supply two sets of codes (for two different reference clock frequencies) to each side of the
I/O (at each of the corners). The DQSBUF uses this code to controls the DQS input of the DDR memory to 90° shift to
clock DQs at the center of the data eye for DDR memory interface.
The code is also sent to another slave DLL, DLLDEL, that takes a clock input and generates a 90° shift clock output to
drive the clocking structure. This is useful to interface edge-aligned Generic DDR, where 90° clocking needs to be
created. Figure 2.10 shows DDRDLL functional diagram.
DDRDLL
CLK
DDRDEL
RST
LOCK
UDDCNTLN
DCNTL[7:0]
FREEZE
Figure 2.10. DDRDLL Functional Diagram
Table 2.5. DDRDLL Ports List

Port Name Type Description
CLK Input Reference clock input to the DDRDLL. Should run at the same frequency as the clock to the delay code.
RST Input Reset Input to the DDRDLL.
Update Control to update the delay code. The code is the DCNTL[7:0] outputs. These outputs are
UDDCNTLN Input
updated when the UDDCNTLN signal is LOW.
FREEZE goes high and, without a glitch, turns off the DLL internal clock and the ring oscillator output
FREEZE Input
clock. When FREEZE goes low, it turns them back on.
DDRDEL Output The delay codes from the DDRDLL to be used in DQSBUF or DLLDEL.
LOCK Output Lock output to indicate the DDRDLL has valid delay output.
DCNTL [7:0] Output The delay codes from the DDRDLL available for the user IP.
There are four identical DDRDLLs, one in each of the four corners in LFE5-85 and LFE5-45 devices, and two DDRDLLs in
both LFE5-25 and LFE5-12 devices in the upper two corners. Each DDRDLL can generate delay code based on the
reference frequency. The slave DLL (DQSBUF and DLLDEL) use the code to delay the signal, to create the phase shifted
signal used for either DDR memory, to create 90° shift clock. Figure 2.11 shows the DDRDLL and the slave DLLs on the
top level view.
22 FPGA-DS-02012-2.1
Data Sheet
LFE5 Device
Config I/O
Figure 2.11. ECP5/ECP5-5G DLL Top Level View (For LFE-45 and LFE-85)
2.8. sysMEM Memory

ECP5/ECP5-5G devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of an 18 Kb RAM
with memory core, dedicated input registers and output registers with separate clock and clock enable. Each EBR
includes functionality to support true dual-port, pseudo dual-port, single-port RAM, ROM and FIFO buffers (via external
PFUs).
2.8.1. sysMEM Memory Block

The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in a
variety of depths and widths as listed in Table 2.6. FIFOs can be implemented in sysMEM EBR blocks by implementing
support logic with PFUs. The EBR block facilitates parity checking by supporting an optional parity bit for each data
byte. EBR blocks provide byte-enable support for configurations with 18-bit and 36-bit data widths. For more
information, refer to ECP5 and ECP5-5G Memory Usage Guide (TN1264).
FPGA-DS-02012-2.1 23
Data Sheet
Table 2.6. sysMEM Block Configurations

Memory Mode Configurations
16,384 x 1
8,192 x 2
4,096 x 4
Single Port
2,048 x 9
1,024 x 18
512 x 36
16,384 x 1
8,192 x 2
True Dual Port 4,096 x 4
2,048 x 9
1,024 x 18
16,384 x 1
8,192 x 2
4,096 x 4
Pseudo Dual Port
2,048 x 9
1,024 x 18
512 x 36
2.8.2. Bus Size Matching

All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word
0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for each port
varies, this mapping scheme applies to each port.
2.8.3. RAM Initialization and ROM Operation

If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block during
the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM.
2.8.4. Memory Cascading

Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade
memory transparently, based on specific design inputs.
2.8.5. Single, Dual and Pseudo-Dual Port Modes

In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory
array. The output data of the memory is optionally registered at the output.
EBR memory supports the following forms of write behavior for single port or dual port operation:
 Normal – Data on the output appears only during a read cycle. During a write cycle, the data (at the current
address) does not appear on the output. This mode is supported for all data widths.
 Write Through – A copy of the input data appears at the output of the same port during a write cycle. This mode is
supported for all data widths.
 Read-Before-Write – When new data is written, the old content of the address appears at the output. This mode is
supported for x9, x18, and x36 data widths.
24 FPGA-DS-02012-2.1
Data Sheet
2.8.6. Memory Core Reset

The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchronously or
synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B,
respectively. The Global Reset (GSRN) signal can reset both ports. The output data latches and associated resets for
both ports are as shown in Figure 2.12.
Memory Core
SET
D Q Port A[17:0]
LCLR
Output Data
Latches
D
SET
Q Port B[17:0]
LCLR
RSTA
RSTB
GSRN
Programmable Disable
Figure 2.12. Memory Core Reset
For further information on the sysMEM EBR block, see the list of technical documentation in Supplemental Information
section.
2.9. sysDSP™ Slice

The ECP5/ECP5-5G family provides an enhanced sysDSP architecture, making it ideally suited for low-cost,
high-performance Digital Signal Processing (DSP) applications. Typical functions used in these applications are Finite
Impulse Response (FIR) filters, Fast Fourier Transforms (FFT) functions, Correlators, Reed-Solomon/Turbo/Convolution
encoders and decoders. These complex signal processing functions use similar building blocks such as multiply-adders
and multiply-accumulators.
2.9.1. sysDSP Slice Approach Compared to General DSP

Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with fixed
data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by higher
clock speeds. In the ECP5/ECP5-5G device family, there are many DSP slices that can be used to support different data
widths. This allows designers to use highly parallel implementations of DSP functions. Designers can optimize DSP
performance vs. area by choosing appropriate levels of parallelism. Figure 2.13 compares the fully serial
implementation to the mixed parallel and serial implementation.
FPGA-DS-02012-2.1 25
Data Sheet
Operand Operand Operand

A A A
Operand Operand Operand
B B B
Operand Operand
A B
x x x m/k
loops
Single
Multiplier x M loops Multiplier
0
Multiplier
1
Multiplier
k
Accumulator
Function Implemented in
(k adds) +
General Purpose DSP
m/k
accumulate
Output
Function Implemented in ECP5/ECP5-5G
Figure 2.13. Comparison of General DSP and ECP5/ECP5-5G Approaches
2.9.2. sysDSP Slice Architecture Features

The ECP5/ECP5-5G sysDSP Slice has been significantly enhanced to provide functions needed for advanced processing
applications. These enhancements provide improved flexibility and resource utilization.
The ECP5/ECP5-5G sysDSP Slice supports many functions that include the following:
 Symmetry support. The primary target application is wireless. 1D Symmetry is useful for many applications that
use FIR filters when their coefficients have symmetry or asymmetry characteristics. The main motivation for using
1D symmetry is cost/size optimization. The expected size reduction is up to 2x.
 Odd mode – Filter with Odd number of taps
 Even mode – Filter with Even number of taps
 Two dimensional (2D) symmetry mode – supports 2D filters for mainly video applications
 Dual-multiplier architecture. Lower accumulator overhead to half and the latency to half compared to single
multiplier architecture
 Fully cascadable DSP across slices. Support for symmetric, asymmetric and non-symmetric filters.
 Multiply (one 18 x 36, two 18 x 18 or four 9 x 9 Multiplies per Slice)
 Multiply (36 x 36 by cascading across two sysDSP slices)
 Multiply Accumulate (supports one 18 x 36 multiplier result accumulation or two 18 x 18 multiplier result
accumulation)
 Two Multiplies feeding one Accumulate per cycle for increased processing with lower latency (two 18 x 18
Multiplies feed into an accumulator that can accumulate up to 52 bits)
 Pipeline registers
 1D Symmetry support. The coefficients of FIR filters have symmetry or negative symmetry characteristics.
 Odd mode – Filter with Odd number of taps
 Even mode – Filter with Even number of taps
26 FPGA-DS-02012-2.1
Data Sheet
 2D Symmetry support. The coefficients of 2D FIR filters have symmetry or negative symmetry characteristics.
 3*3 and 3*5 – Internal DSP Slice support
 5*5 and larger size 2D blocks – Semi internal DSP Slice support
 Flexible saturation and rounding options to satisfy a diverse set of applications situations
 Flexible cascading across DSP slices
 Minimizes fabric use for common DSP and ALU functions
 Enables implementation of FIR Filter or similar structures using dedicated sysDSP slice resources only
 Provides matching pipeline registers
 Can be configured to continue cascading from one row of sysDSP slices to another for longer cascade chains
 Flexible and Powerful Arithmetic Logic Unit (ALU) Supports:
 Dynamically selectable ALU OPCODE
 Ternary arithmetic (addition/subtraction of three inputs)
 Bit-wise two-input logic operations (AND, OR, NAND, NOR, XOR and XNOR)
 Eight flexible and programmable ALU flags that can be used for multiple pattern detection scenarios, such as,
overflow, underflow and convergent rounding.
 Flexible cascading across slices to get larger functions
 RTL Synthesis friendly synchronous reset on all registers, while still supporting asynchronous reset for legacy users
 Dynamic MUX selection to allow Time Division Multiplexing (TDM) of resources for applications that require
processor-like flexibility that enables different functions for each clock cycle
For most cases, as shown in Figure 2.14, the ECP5/ECP5-5G sysDSP slice is backwards-compatible with the
LatticeECP2™ and LatticeECP3™ sysDSP block, such that, legacy applications can be targeted to the ECP5/ ECP5-5G
sysDSP slice. Figure 2.14 shows the diagram of sysDSP, and Figure 2.15 shows the detailed diagram.
FPGA-DS-02012-2.1 27
Data Sheet
SLICE 0 SLICE 1
MUP0[35:18]
MUP1[35:18]
MUP2[35:18]
MUP3[35:18]
MUP0[17:0]
MUP1[17:0]
MUP2[17:0]
MUP3[17:0]
OutA0 (18)
OutA1 (18)
OutA2 (18)
OutA3 (18)
OutB0 (18)
OutB1 (18)
OutB2 (18)
OutB3 (18)
CIN[53:0] (hardwired COUT[53:0] (hardwired
cascade from left DSP) cascade to right DSP)
One of these
Accumulator/ALU (54) Accumulator/ALU (54)
ALU24 ALU24 ALU24 ALU24
Flags[7:0]
PR0 (36) PR1 (36) PR2 (36) PR3 (36)
CLK[3:0] SIGNEDA[3:0]
9x9 9x9 9x9 9x9 9x9 9x9 9x9 9x9
CE[3:0] SIGNEDB[3:0]
One of these
RST[3:0] SOURCEA[3:0]
Mult18-0 Mult18-1 Mult18-2 Mult18-1
SOURCEB[3:0]
DYNOP0[10:0], 36x36 (Mult36) GSR

DYNOP1[10:0] 18
Casc Casc
18
SRIA[17:0] In Reg A 0 In Reg A 1 In Reg A 0 In Reg A 1 SROA[17:0]
A0 A1
18 18
SRIB[17:0] In Reg B 0 In Reg B 1 In Reg B 0 In Reg B 1 SROB[17:0]
Hardwired from DSP
One of these
9+/-9 9+/-9 9+/-9 9+/-9 9+/-9 9+/-9 9+/-9 9+/-9 To DSP
Block on Left Block on
18+/-18 18+/-18 18+/-18 18+/-18 Right and to
CIB Outputs
MUA0[17:0]
MUA1[17:0]
MUA2[17:0]
MUA3[17:0]
MUB0[17:0]
MUB1[17:0]
MUB2[17:0]
MUB3[17:0]
C0[53:0]
C0[53:0]
Figure 2.14. Simplified sysDSP Slice Block Diagram
28 FPGA-DS-02012-2.1
Data Sheet
MUIA0 MUIB0 OPCODE_PA MUIA1 MUIB1
INT_A INT_B
IR
INT_B SRIBK_PA
IR IR
INT_A
IR IR
DSP
+/-
= +/- PreAdder
Logic
C OPA0 DYNOP OPA1
SROA
SRIA
IR IR IR
IR IR
SRIB SROB
MULTA MULTB
IR IR
PR PR PR
A ALU B ALU
0 0
Shift 18L
AMUX BMUX
C_ALU R= A ± B ± C
COUT
CIN R = Logic (B, C)
CMUX
ALU
==
OR OR FR OR
DSP
Core
Logic
MUOP0 R FLAGS MUOP1
DSP SLICE
Figure 2.15. Detailed sysDSP Slice Diagram
FPGA-DS-02012-2.1 29
Data Sheet
In Figure 2.15, note that A_ALU, B_ALU and C_ALU are internal signals generated by combining bits from AA, AB, BA BB
and C inputs. For further information, refer to ECP5 and ECP5-5G sysDSP Usage Guide (TN1267).
The ECP5/ECP5-5G sysDSP block supports the following basic elements.
 MULT (Multiply)
 MAC (Multiply, Accumulate)
 MULTADDSUB (Multiply, Addition/Subtraction)
 MULTADDSUBSUM (Multiply, Addition/Subtraction, Summation)
Table 2.7 shows the capabilities of each of the ECP5/ECP5-5G slices versus the above functions.
Table 2.7. Maximum Number of Elements in a Slice
Width of Multiply x9 x18 x36
MULT 4 2 1/2
MAC 1 1 —
MULTADDSUB 2 1 —
MULTADDSUBSUM 1* 1/2 —
*Note: One slice can implement 1/2 9x9 m9x9addsubsum and two m9x9addsubsum with two slices.
Some options are available in the four elements. The input register in all the elements can be directly loaded or can be
loaded as a shift register from previous operand registers. By selecting dynamic operation, the following operations are
possible:
 In the Add/Sub option the Accumulator can be switched between addition and subtraction on every cycle.
 The loading of operands can switch between parallel and serial operations.
For further information, refer to ECP5 and ECP5-5G sysDSP Usage Guide (TN1267).
2.10. Programmable I/O Cells

The programmable logic associated with an I/O is called a PIO. The individual PIO are connected to their respective
sysI/O buffers and pads. On the ECP5/ECP5-5G devices, the Programmable I/O cells (PIC) are assembled into groups of
four PIO cells called a Programmable I/O Cell or PIC. The PICs are placed on all four sides of the device.
On all the ECP5/ECP5-5G devices, two adjacent PIOs can be combined to provide a complementary output driver pair.
All PIO pairs can implement differential receivers. Half of the PIO pairs on the left and right edges of these devices can
be configured as true LVDS transmit pairs.
30 FPGA-DS-02012-2.1
Data Sheet
1 PIC
PIO A
Input
Register
Block
Output and
Tristate
Pin A
Register
Block
PIO B
Input
Register
Block
Output and
Tristate
Pin B
Register
Input Output
Block
Gearbox Gearbox
Core
Logic / PIO C
Routing Input
Register
Block
Output and
Tristate
Pin C
Register
Block
PIO D
Input
Register
Block
Output and
Tristate
Pin D
Register
Block
Figure 2.16. Group of Four Programmable I/O Cells on Left/Right Sides
FPGA-DS-02012-2.1 31
Data Sheet
2.11. PIO
The PIO contains three blocks: an input register block, output register block, and tristate register block. These blocks
contain registers for operating in a variety of modes along with the necessary clock and selection logic.
2.11.1. Input Register Block

The input register blocks for the PIOs on all edges contain delay elements and registers that can be used to condition
high-speed interface signals before they are passed to the device core. In addition, the input register blocks for the
PIOs on the left and right edges include built-in FIFO logic to interface to DDR and LPDDR memory.
The Input register block on the right and left sides includes gearing logic and registers to implement IDDRX1 and
IDDRX2 functions. With two PICs sharing the DDR register path, it can also implement IDDRX71 function used for 7:1
LVDS interfaces. It uses three sets of registers to shift, update, and transfer to implement gearing and the clock domain
transfer. The first stage registers samples the high-speed input data by the high-speed edge clock on its rising and
falling edges. The second stage registers perform data alignment based on the control signals. The third stage pipeline
registers pass the data to the device core synchronized to the low-speed system clock. The top side of the device
supports IDDRX1 gearing function. For more information on gearing function, refer to ECP5 and ECP5-5G High-Speed
I/O Interface (FPGA-TN-02035).
Figure 2.17 shows the input register block for the PIOs on the top edge.
INCK
Programmable INFF
D Delay Cell
INFF Q
SCLK IDDRX1 Q[1:0]

RST
Figure 2.17. Input Register Block for PIO on Top Side of the Device
Figure 2.18 shows the input register block for the PIOs located on the left and right edges.
INCK
Programmable INFF
D Delay Cell
INFF Q
Generic
IDDRX1
FIFO IDDRX2 Q[1:0]/
Delayed DQS ECLK IDDRX71* Q[3:0]/
Q[6:0]*
Memory
ECLK
IDDRX2
SCLK
RST
ALIGNWD
*For 7:1 LVDS interface only. It is required to use PIO pair pins (PIOA/B or PIOC/D).
Figure 2.18. Input Register Block for PIO on Left and Right Side of the Device
32 FPGA-DS-02012-2.1
Data Sheet
2.11.1.1. Input FIFO

The ECP5/ECP5-5G PIO has dedicated input FIFO per single-ended pin for input data register for DDR Memory
interfaces. The FIFO resides before the gearing logic. It transfers data from DQS domain to continuous ECLK domain. On
the Write side of the FIFO, it is clocked by DQS clock which is the delayed version of the DQS Strobe signal from DDR
memory. On the Read side of FIFO, it is clocked by ECLK. ECLK may be any high speed clock with identical frequency as
DQS (the frequency of the memory chip). Each DQS group has one FIFO control block. It distributes FIFO read/write
pointer to every PIC in same DQS group. DQS Grouping and DQS Control Block is described in DDR Memory Support
section.
Table 2.8. Input Block Port Description
Name Type Description
D Input High Speed Data Input
Q[1:0]/Q[3:0]/Q[6:0] Output Low Speed Data to the device core
RST Input Reset to the Output Block
SCLK Input Slow Speed System Clock
ECLK Input High Speed Edge Clock
DQS Input Clock from DQS control Block used to clock DDR memory data
ALIGNWD Input Data Alignment signal from device core.
2.11.2. Output Register Block

The output register block registers signal from the core of the device before they are passed to the sysI/O buffers.
ECP5/ECP5-5G output data path has output programmable flip flops and output gearing logic. On the left and right
sides, the output register block can support 1x, 2x, and 7:1 gearing enabling high speed DDR interfaces and DDR
memory interfaces. On the top side, the banks support 1x gearing. ECP5/ECP5-5G output data path diagram is shown in
Figure 2.19. The programmable delay cells are also available in the output data path.
For detailed description of the output register block modes and usage, refer to ECP5 and ECP5-5G High-Speed I/O
Interface (FPGA-TN-02035).
Programmable
D Delay Cell Q
OUTFF
RST
SCLK Generic
ODDRX1
D[1:0]
Figure 2.19. Output Register Block on Top Side
FPGA-DS-02012-2.1 33
Data Sheet
Programmable
D Delay Cell
Q
OUTFF
RST Generic
SCLK ODDRX1/
ECLK ODDRX2/
DQSW ODDR71*
DQSW270
Memory
D[1:0]/ ODDRX2
D[3:0]/ OSHX2
D[6:0]*
*For 7:1 LVDS interface only. It is required to use PIO pair pins PIOA/B.
Figure 2.20. Output Register Block on Left and Right Sides
Table 2.9. Output Block Port Description

Q Output High Speed Data Output
D Input Data from core to output SDR register
D[1:0]/D[3:0]/ D[6:0] Input Low Speed Data from device core to output DDR register
RST Input Reset to the Output Block
DQSW Input Clock from DQS control Block used to generate DDR memory DQS output
DQSW270 Input Clock from DQS control Block used to generate DDR memory DQ output
2.12. Tristate Register Block

The tristate register block registers tristate control signals from the core of the device before they are passed to the
sysI/O buffers. The block contains a register for SDR operation. In SDR, TD input feeds one of the flip-flops that then
feeds the output. In DDR, operation used mainly for DDR memory interface can be implemented on the left and right
sides of the device. Here two inputs feed the tristate registers clocked by both ECLK and SCLK.
Figure 2.21 and Figure 2.22 show the Tristate Register Block functions on the device. For detailed description of the
tristate register block modes and usage, refer to ECP5 and ECP5-5G High-Speed I/O Interface (FPGA-TN-02035).
TQ
TD
RST TSFF
SCLK
Figure 2.21. Tristate Register Block on Top Side
34 FPGA-DS-02012-2.1
Data Sheet
TQ
TD
TSFF
RST
SCLK
ECLK
THSX2
DQSW
DQSW270
T[1:0]
Figure 2.22. Tristate Register Block on Left and Right Sides
Table 2.10. Tristate Block Port Description

TD Input Tristate Input to Tristate SDR Register
RST Input Reset to the Tristate Block
TD[1:0] Input Tristate input to TSHX2 function
DQSW Input Clock from DQS control Block used to generate DDR memory DQS output
DQSW270 Input Clock from DQS control Block used to generate DDR memory DQ output
TQ Output Output of the Tristate block
2.13. DDR Memory Support

2.13.1. DQS Grouping for DDR Memory
Certain PICs have additional circuitry to allow the implementation of high-speed source synchronous and DDR2, DDR3,
LPDDR2 or LPDDR3 memory interfaces. The support varies by the edge of the device as detailed below.
The left and right sides of the PIC have fully functional elements supporting DDR2, DDR3, LPDDR2, or LPDDR3 memory
interfaces. Every 16 PIOs on the left and right sides are grouped into one DQS group, as shown in Figure 2.23. Within
each DQS group, there are two pre-placed pins for DQS and DQS# signals. The rest of the pins in the DQS group can be
used as DQ signals and DM signal. The number of pins in each DQS group bonded out is package dependent. DQS
groups with less than 11 pins bonded out can only be used for LPDDR2/3 Command/ Address busses. In DQS groups
with more than 11 pins bonded out, up to two pre-defined pins are assigned to be used as virtual VCCIO, by driving these
pins to HIGH, with the user connecting these pins to VCCIO power supply. These connections create soft connections to
VCCIO thru these output pins, and make better connections on VCCIO to help to reduce SSO noise. For details, refer to
ECP5 and ECP5-5G High-Speed I/O Interface (FPGA-TN-02035).
FPGA-DS-02012-2.1 35
Data Sheet
PIO A sysI/O Buffer Pad A (T)
PIO B sysI/O Buffer Pad B (C)
PIO C sysI/O Buffer Pad C
PIO D sysI/O Buffer Pad D
DQS DQSBUF Delay
Figure 2.23. DQS Grouping on the Left and Right Edges
2.13.2. DLL Calibrated DQS Delay and Control Block (DQSBUF)

To support DDR memory interfaces (DDR2/3, LPDDR2/3), the DQS strobe signal from the memory must be used to
capture the data (DQ) in the PIC registers during memory reads. This signal is output from the DDR memory device
aligned to data transitions and must be time shifted before it can be used to capture data in the PIC. This time shifted is
achieved by using DQSDEL programmable delay line in the DQS Delay Block (DQS read circuit). The DQSDEL is
implemented as a slave delay line and works in conjunction with a master DDRDLL.
This block also includes slave delay line to generate delayed clocks used in the write side to generate DQ and DQS with
correct phases within one DQS group. There is a third delay line inside this block used to provide write leveling feature
for DDR write if needed.
Each of the read and write side delays can be dynamically shifted using margin control signals that can be controlled by
the core logic.
FIFO Control Block shown in Figure 2.24 generates the Read and Write Pointers for the FIFO block inside the Input
Register Block. These pointers are generated to control the DQS to ECLK domain crossing using the FIFO module.
36 FPGA-DS-02012-2.1
Data Sheet
DQS Preamble/Postamble Management BURSTDET

&
READ[1:0] Burst Detect DATAVALID
READCLKSEL[1:0]
FIFO Control & Datavalid RDPNTR[2:0]

ECLK
Generation WRPNTR[2:0]
SCLK
DQSDEL
(90 Deg. Delay Code
from DDRDLL)
Read Side Slave Delay with DQSR90 (Read Side)
RDLOADN, RDMOVE, RDDIRECTION Dynamic Margin Control
(Read Side Dynamic Margin Control)
DQSW (Write Side)

WRLOADN, WRMOVE, WRDIRECTION DQSW270 (Write Side)
Write Side Slave Delay with
(Write Side Dynamic Margin Control)
Dynamic Margin Control RDCFLAG
WRCFLAG
PAUSE
DYNDELAY[7:0] Write
(Write Leveling delay) Leveling
Figure 2.24. DQS Control and Delay Block (DQSBUF)
Table 2.11. DQSBUF Port List Description

DQS Input DDR memory DQS strobe
READ[1:0] Input Read Input from DDR Controller
READCLKSEL[1:0] Input Read pulse selection
SCLK Input Slow System Clock
ECLK Input High Speed Edge Clock (same frequency as DDR memory)
DQSDEL Input 90° Delay Code from DDRDLL
RDLOADN, RDMOVE, RDDIRECTION Input Dynamic Margin Control ports for Read delay
WRLOADN, WRMOVE, WRDIRECTION Input Dynamic Margin Control ports for Write delay
Used by DDR Controller to Pause write side signals during
PAUSE Input
DDRDLL Code update or Write Leveling
DYNDELAY[7:0] Input Dynamic Write Leveling Delay Control
DQSR90 Output 90° delay DQS used for Read
DQSW270 Output 90° delay clock used for DQ Write
DQSW Output Clock used for DQS Write
RDPNTR[2:0] Output Read Pointer for IFIFO module
WRPNTR[2:0] Output Write Pointer for IFIFO module
DATAVALID Output Signal indicating start of valid data
BURSTDET Output Burst Detect indicator
RDFLAG Output Read Dynamic Margin Control output to indicate max value
WRFLAG Output Write Dynamic Margin Control output to indicate max value
FPGA-DS-02012-2.1 37
Data Sheet
2.14. sysI/O Buffer

Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the
periphery of the device in groups referred to as banks. The sysI/O buffers allow you to implement the wide variety of
standards that are found in today’s systems including LVDS, HSUL, BLVDS, SSTL Class I and II, LVCMOS, LVTTL, LVPECL,
and MIPI.
2.14.1. sysI/O Buffer Banks

ECP5/ECP5-5G devices have seven sysI/O buffer banks, two banks per side at Top, Left and Right, plus one at the
bottom left side. The bottom left side bank (Bank 8) is a shared I/O bank. The I/O in that bank contains both dedicated
and shared I/O for sysConfig function. When a shared pin is not used for configuration, it is available as a user I/O. For
LFE5-85 devices, there is an additional I/O bank (Bank 4) that is not available in other device in the family.
In ECP5/ECP5-5G devices, the Left and Right sides are tailored to support high performance interfaces, such as DDR2,
DDR3, LPDDR2, LPDDR3 and other high speed source synchronous standards. The banks on the Left and Right sides of
the devices feature LVDS input and output buffers, data-width gearing, and DQSBUF block to support DDR2/3 and
LPDDR2/3 interfaces. The I/O on the top and bottom banks do not have LVDS input and output buffer, and gearing
logic, but can use LVCMOS to emulate most of differential output signaling.
Each sysI/O bank has its own I/O supply voltage (VCCIO). In addition, the banks on the Left and Right sides of the device,
have voltage reference input (shared I/O pin), VREF1 per bank, which allow it to be completely independent of each
other. The VREF voltage is used to set the threshold for the referenced input buffers, such as SSTL. Figure 2.25 shows the
seven banks and their associated supplies.
In ECP5/ECP5-5G devices, single-ended output buffers and ratioed input buffers (LVTTL, and LVCMOS) are powered
using VCCIO. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as fixed threshold inputs independent of
VCCIO.
TOP
VCCIO0
VREF1(0)V
VCCIO1
VREF1(1)V
GND
GND
Bank 0 Bank 1
VREF1(7)
GND
V CCIO7
Bank 2
Bank 7
V CCIO2
GND V REF1(2)
RIGHT
LEFT
V REF1(6)
GND
Bank 3
V CCIO6
Bank 6
V CCIO3
V REF1(3)
GND Bank 8
CONFIG BANK Bank 4*
SERDES
V CCIO8
V CCIO4
GND
GND
BOTTOM
*Note: Only 85K device has this bank.
Figure 2.25. ECP5/ECP5-5G Device Family Banks
38 FPGA-DS-02012-2.1
Data Sheet
ECP5/ECP5-5G devices contain two types of sysI/O buffer pairs:

 Top (Bank 0 and Bank 1) and Bottom (Bank 8 and Bank 4) sysI/O Buffer Pairs (Single-Ended Only)
The sysI/O buffers in the Banks at top and bottom of the device consist of ratioed single-ended output drivers and
single-ended input buffers. The I/O in these banks are not usually used as a pair, except when used as emulated
differential output pair. They are used as individual I/O and be configured as different I/O modes, as long as they
are compatible with the VCCIO voltage in the bank. When used as emulated differential outputs, the pair can be used
together.
The top and bottom side I/O also support hot socketing. They support I/O standards from 3.3 V to 1.2 V. They are
ideal for general purpose I/O, or as ADDR/CMD bus for DDR2/DDR3 applications, or for used as emulated
differential signaling.
Bank 4 I/O only exists in the LFE5-85 device.
Bank 8 is a bottom bank that shares with sysConfig I/O. During configuration, these I/O are used for programming
the device. Once the configuration is completed, these I/O can be released and you can use these I/O for functional
signals in his design.
The top and bottom side pads can be identified by the Lattice Diamond tool.
 Left and Right (Bank 2, Bank 3, Bank 6 and Bank 7) sysI/O Buffer Pairs (50% Differential and 100% Single-Ended
Outputs)
The sysI/O buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two
single-ended input buffers (both ratioed and referenced) and half of the sysI/O buffer pairs (PIOA/B pairs) also has
a high-speed differential output driver. One of the referenced input buffers can also be configured as a differential
input. In these banks the two pads in the pair are described as true and comp, where the true pad is associated
with the positive side of the differential I/O, and the comp (complementary) pad is associated with the negative
side of the differential I/O.
In addition, programmable on-chip input termination (parallel or differential, static or dynamic) is supported on
these sides, which is required for DDR3 interface. However, there is no support for hot-socketing for the I/O pins
located on the left and right side of the device as the PCI clamp is always enabled on these pins.
LVDS differential output drivers are available on 50% of the buffer pairs on the left and right banks.
2.14.2. Typical sysI/O I/O Behavior during Power-up

The internal Power-On-Reset (POR) signal is deactivated when VCC, VCCIO8 and VCCAUX have reached satisfactory levels.
After the POR signal is deactivated, the FPGA core logic becomes active. It is your responsibility to ensure that all other
VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are
critical to the application. For more information about controlling the output logic state with valid input logic levels
during power-up in ECP5/ECP5-5G devices, see the list of technical documentation in Supplemental Information
section.
The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buffers. In
order to simplify system design while providing consistent and predictable I/O behavior, it is recommended that the I/O
buffers be powered-up prior to the FPGA core fabric. VCCIO supplies should be powered-up before or together with the
VCC and VCCAUX supplies.
2.14.3. Supported sysI/O Standards

The ECP5/ECP5-5G sysI/O buffer supports both single-ended and differential standards. Single-ended standards can be
further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2 V, 1.5 V, 1.8V,
2.5 V and 3.3 V standards. In the LVCMOS and LVTTL modes, the buffer has individual configuration options for drive
strength, slew rates, bus maintenance (weak pull-up or weak pull-down) and open drain. Other single-ended standards
supported include SSTL and HSUL. Differential standards supported include LVDS, differential SSTL and differential
HSUL. For further information on utilizing the sysI/O buffer to support a variety of standards, refer to ECP5 and ECP5-
5G sysI/O Usage Guide (FPGA-TN-02032).
FPGA-DS-02012-2.1 39
Data Sheet
2.14.4. On-Chip Programmable Termination

The ECP5/ECP5-5G devices support a variety of programmable on-chip terminations options, including:
 Dynamically switchable Single-Ended Termination with programmable resistor values of 50 Ω, 75 Ω, or 150 Ω.
 Common mode termination of 100 Ω for differential inputs.
V CCIO Zo = 50
TERM
Zo = 50 Ω, 75 Ω, or 150 Ω
control
to V CCIO /2
Zo
Zo +
2Zo -
Zo +
- Zo
VREF
OFF-chip ON-chip OFF-chip ON-chip
Parallel Single-Ended Input Differential Input
Figure 2.26. On-Chip Termination
See Table 2.12 for termination options for input modes.

Table 2.12. On-Chip Termination Options for Input Modes
IO_TYPE Terminate to VCCIO/2* Differential Termination Resistor*
LVDS25 — 100
BLVDS25 — 100
MLVDS — 100
LVPECL33 — 100
subLVDS — 100
SLVS — 100
HSUL12 50, 75, 150 —
HSUL12D — 100
SSTL135_I / II 50, 75, 150 —
SSTL135D_I / II — 100
SSTL15_I / II 50, 75, 150 —
SSTL15D_I / II — 100
SSTL18_I / II 50, 75, 150 —
SSTL18D_I / II — 100
*Notes:
 TERMINATE to VCCIO/2 (Single-Ended) and DIFFRENTIAL TERMINATION RESISTOR when turned on can only have one setting per
bank. Only left and right banks have this feature.
 Use of TERMINATE to VCCIO/2 and DIFFRENTIAL TERMINATION RESISTOR are mutually exclusive in an I/O bank. On-chip
termination tolerance ±20%.
Refer to ECP5 and ECP5-5G sysI/O Usage Guide (FPGA-TN-02032) for on-chip termination usage and value ranges.
2.14.5. Hot Socketing

ECP5/ECP5-5G devices have been carefully designed to ensure predictable behavior during power-up and power-down.
During power-up and power-down sequences, the I/O remain in tristate until the power supply voltage is high enough
to ensure reliable operation. In addition, leakage into I/O pins is controlled within specified limits. See the Hot
Socketing Specifications section.
40 FPGA-DS-02012-2.1
Data Sheet
2.15. SERDES and Physical Coding Sublayer

LFE5UM/LFE5UM5G devices feature up to four channels of embedded SERDES/PCS arranged in dual-channel blocks at
the bottom of the devices. Each channel supports up to 3.2 Gb/s (ECP5), or up to 5 Gb/s (ECP5-5G) data rate. Figure
2.27 shows the position of the dual blocks for the LFE5-85. Table 2.13 shows the location of available SERDES Duals for
all devices. The LFE5UM/LFE5UM5G SERDES/PCS supports a range of popular serial protocols, including:
 PCI Express Gen1 and Gen2 (2.5 Gb/s) on ECP5UM; Gen 1, Gen2 (2.5 Gb/s and 5 Gb/s) on ECP5-5G
 Ethernet (XAUI, GbE – 1000 Base CS/SX/LX and SGMII)
 SMPTE SDI (3G-SDI, HD-SDI, SD-SDI)
 CPRI (E.6.LV: 614.4 Mb/s, E.12.LV: 1228.8 Mb/s, E.24.LV: 2457.6 Mb/s, E.30.LV: 3072 Mb/s), also
E.48.LV2:4915 Mb/s in ECP5-5G
 JESD204A/B – ADC and DAC converter interface: 312.5 Mb/s to 3.125 Gb/s (ECP5) / 5 Gb/s (ECP5-5G)
Each dual contains two dedicated SERDES for high speed, full duplex serial data transfer. Each dual also has a PCS block
that interfaces to the SERDES channels and contains protocol specific digital logic to support the standards listed above.
The PCS block also contains interface logic to the FPGA fabric. All PCS logic for dedicated protocol support can also be
bypassed to allow raw 8-bit or 10-bit interfaces to the FPGA fabric.
Even though the SERDES/PCS blocks are arranged in duals, multiple baud rates can be supported within a dual with the
use of dedicated, per channel /1, /2 and /11 rate dividers. Additionally, two duals can be arranged together to form x4
channel link.
ECP5UM devices and ECP5-5G devices are pin-to-pin compatible. But, the ECP5UM devices require 1.1 V on VCCA,
VCCHRX and VCCHTX supplies. ECP5-5G devices require 1.2 V on these supplies. When designing either family device
with migration in mind, these supplies need to be connected such that it is possible to adjust the voltage level on these
supplies.
When a SERDES Dual in a 2-Dual device is not used, the power VCCA power supply for that Dual should be connected. It
is advised to connect the VCCA of unused channel to core if you will not use the Dual at all, or it should be connected to
a different regulated supply, if that Dual may be used in the future.
For an unused channel in a Dual, it is advised to connect the V CCHTX to VCCA, and you can leave VCCHRX unconnected.
For information on how to use the SERDES/PCS blocks to support specific protocols, as well on how to combine
multiple protocols and baud rates within a device, refer to ECP5 and ECP5-5G SERDES/PCS Usage Guide (TN1261).
FPGA-DS-02012-2.1 41
Data Sheet
sysI/O Bank 0 sysI/O Bank 1
sysI/O Bank 2
sysI/O Bank 7
sysI/O Bank 3
sysI/O Bank 6
SERDES/ SERDES/
PCS PCS
Dual 0 Dual 1
CH0
CH0
CH1
CH1
sysI/O Bank 8 sysI/O Bank 4
Figure 2.27. SERDES/PCS Duals (LFE5UM/LFE5UM5G-85)
Table 2.13. LFE5UM/LFE5UM5G SERDES Standard Support

Standard Data Rate (Mb/s) Number of General/Link Width Encoding Style
PCI Express 1.1 and 2.0 2500 x1, x2, x4 8b10b
2.02 5000 2 x1, x2 8b10b
Gigabit Ethernet 1250 x1 8b10b
SGMII 1250 x1 8b10b
2500 x1 8b10b
XAUI 3125 x4 8b10b
CPRI-1 614.4 x1, x2, x4 8b10b
CPRI-2 1228.8
CPRI-3 2457.6
x1 8b10b
CPRI-4 3072.0
CPRI-5 4915.2 2
SD-SDI (259M, 344M) 1 270 x1 NRZI/Scrambled
1483.5
HD-SDI (292M) x1 NRZI/Scrambled
1485
2967
x1 NRZI/Scrambled
3G-SDI (424M) 2970
5000 — —
JESD204A/B 3125 x1 8b/10b
Notes:
1. For SD-SDI rate, the SERDES is bypassed and SERDES input signals are directly connected to the FPGA routing.
2. For ECP5-5G family devices only.
42 FPGA-DS-02012-2.1
Data Sheet
Table 2.14. Available SERDES Duals per LFE5UM/LFE5UM5G Devices

Package LFE5UM/LFE5UM5G-25 LFE5UM/LFE5UM5G-45 LFE5UM/LFE5UM5G-85
285 csfBGA 1 1 1
381 caBGA 1 2 2
554 caBGA — 2 2
756 caBGA — — 2
2.15.1. SERDES Block

A SERDES receiver channel may receive the serial differential data stream, equalize the signal, perform Clock and Data
Recovery (CDR) and de-serialize the data stream before passing the 8- or 10-bit data to the PCS logic. The SERDES
transmitter channel may receive the parallel 8- or 10-bit data, serialize the data and transmit the serial bit stream
through the differential drivers. Figure 2.28 shows a single-channel SERDES/PCS block. Each SERDES channel provides a
recovered clock and a SERDES transmit clock to the PCS block and to the FPGA core logic.
Each transmit channel, receiver channel, and SERDES PLL shares the same power supply (VCCA). The output and input
buffers of each channel have their own independent power supplies (V CCHTX and VCCHRX).
SERDES PCS FPGA Core

Recovered Clock*
RX_REFCLK Recovered Clock
HDINP Clock/Data Deserializer Polarity Word Alignment CTC Downsample

Equalizer Receive Data
HDINN Recovery 1:8/1:10 Adjust 8b/10b Decoder FIFO FIFO
Receiver Bypass Bypass

Bypass
Receive Clock
TX PLL
TX REFCLK SERDES Tx Clock
(Per Dual)
De-emphasis 8b/10b Upsample

Tx Driver Transmit Data
Polarity Encoder FIFO
HDOUTP Adjust
Serializer
HDOUTN 8:1/10:1 Bypass Transmit Clock
Bypass
* 1/8 or 1/10 line rate
Figure 2.28. Simplified Channel Block Diagram for SERDES/PCS Block
2.15.2. PCS
As shown in Figure 2.28, the PCS receives the parallel digital data from the deserializer and selects the polarity,
performs word alignment, decodes (8b/10b), provides Clock Tolerance Compensation and transfers the clock domain
from the recovered clock to the FPGA clock via the Down Sample FIFO.
For the transmit channel, the PCS block receives the parallel data from the FPGA core, encodes it with 8b/10b, selects
the polarity and passes the 8/10 bit data to the transmit SERDES channel.
The PCS also provides bypass modes that allow a direct 8-bit or 10-bit interface from the SERDES to the FPGA logic. The
PCS interface to the FPGA can also be programmed to run at 1/2 speed for a 16-bit or 20-bit interface to the FPGA logic.
Some of the enhancements in LFE5UM/LFE5UM5G SERDES/PCS include:
 Higher clock/channel granularity: Dual channel architecture provides more clock resource per channel.
 Enhanced Tx de-emphasis: Programmable pre- and post-cursors improves Tx output signaling
 Bit-slip function in PCS: Improves logic needed to perform Word Alignment function
Refer to ECP5 and ECP5-5G SERDES/PCS Usage Guide (TN1261) for more information.
FPGA-DS-02012-2.1 43
Data Sheet
2.15.3. SERDES Client Interface Bus

The SERDES Client Interface (SCI) is an IP interface that allows you to change the configuration thru this interface. This
is useful when you need to fine-tune some settings, such as input and output buffer that need to be optimized based
on the channel characteristics. It is a simple register configuration interface that allows SERDES/PCS configuration
without power cycling the device.
The Diamond design tools support all modes of the PCS. Most modes are dedicated to applications associated with a
specific industry standard data protocol. Other more general purpose modes allow you to define their own operation.
With these tools, you can define the mode for each dual in a design.
Popular standards such as 10 Gb Ethernet, x4 PCI Express and 4x Serial RapidIO can be implemented using IP (available
through Lattice), with two duals (Four SERDES channels and PCS) and some additional logic from the core.
The LFE5UM/LFE5UM5G devices support a wide range of protocols. Within the same dual, the LFE5UM/ LFE5UM5G
devices support mixed protocols with semi-independent clocking as long as the required clock frequencies are integer
x1, x2, or x11 multiples of each other. Table 2.15 lists the allowable combination of primary and secondary protocol
combinations.
2.16. Flexible Dual SERDES Architecture

The LFE5UM/LFE5UM5G SERDES architecture is a dual channel-based architecture. For most SERDES settings and
standards, the whole dual (consisting of two SERDES channels) is treated as a unit. This helps in silicon area savings,
better utilization, higher granularity on clock/SERDES channel and overall lower cost.
However, for some specific standards, the LFE5UM/LFE5UM5G dual-channel architecture provides flexibility; more
than one standard can be supported within the same dual.
Table 2.15 lists the standards that can be mixed and matched within the same dual. In general, the SERDES standards
whose nominal data rates are either the same or a defined subset of each other, can be supported within the same
dual. The two Protocol columns of the table define the different combinations of protocols that can be implemented
together within a Dual.
Table 2.15. LFE5UM/LFE5UM5G Mixed Protocol Support
Protocol Protocol
PCI Express 1.1 with SGMII
PCI Express 1.1 with Gigabit Ethernet
CPRI-3 with CPRI-2 and CPRI-1
3G-SDI with HD-SDI and SD-SDI
There are some restrictions to be aware of when using spread spectrum clocking. When a dual shares a PCI Express x1
channel with a non-PCI Express channel, ensure that the reference clock for the dual is compatible with all protocols
within the dual. For example, a PCI Express spread spectrum reference clock is not compatible with most Gigabit
Ethernet applications because of tight CTC ppm requirements.
While the LFE5UM/LFE5UM5G architecture allows the mixing of a PCI Express channel and a Gigabit Ethernet, or SGMII
channel within the same dual, using a PCI Express spread spectrum clocking as the transmit reference clock causes a
violation of the Gigabit Ethernet, and SGMII transmit jitter specifications.
For further information on SERDES, refer to ECP5 and ECP5-5G SERDES/PCS Usage Guide (TN1261).
2.17. IEEE 1149.1-Compliant Boundary Scan Testability

All ECP5/ECP5-5G devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test Access
Port (TAP). This allows functional testing of the circuit board on which the device is mounted through a serial scan path
that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and
loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port
consists of dedicated I/O: TDI, TDO, TCK, and TMS. The test access port uses VCCIO8 for power supply.
For more information, refer to ECP5 and ECP5-5G sysCONFIG Usage Guide (FPGA-TN-02039).
44 FPGA-DS-02012-2.1
Data Sheet
2.18. Device Configuration

All ECP5/ECP5-5G devices contain two ports that can be used for device configuration. The Test Access Port (TAP),
which supports bit-wide configuration, and the sysCONFIG port, support dual-byte, byte and serial configuration. The
TAP supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standard 1532 In-System
Configuration specification. There are 11 dedicated pins for TAP and sysConfig supports (TDI, TDO, TCK, TMS, CFG[2:0],
PROGRAMN, DONE, INITN, and CCLK). The remaining sysCONFIG pins are used as dual function pins. Refer to ECP5 and
ECP5-5G sysCONFIG Usage Guide (FPGA-TN-02039) for more information about using the dual-use pins as general
purpose I/O.
There are various ways to configure an ECP5/ECP5-5G device:
 JTAG
 Standard Serial Peripheral Interface (SPI) – Interface to boot PROM Support x1, x2, x4 wide SPI memory interfaces.
 System microprocessor to drive a x8 CPU port SPCM mode
 System microprocessor to drive a serial slave SPI port (SSPI mode)
 Slave Serial model (SCM)
On power-up, the FPGA SRAM is ready to be configured using the selected sysCONFIG port. Once a configuration port is
selected, it remains active throughout that configuration cycle. The IEEE 1149.1 port can be activated any time after
power-up by sending the appropriate command through the TAP port.
ECP5/ECP5-5G devices also support the Slave SPI Interface. In this mode, the FPGA behaves like a SPI Flash device (slave
mode) with the SPI port of the FPGA to perform read-write operations.
2.18.1. Enhanced Configuration Options

ECP5/ECP5-5G devices have enhanced configuration features such as: decryption support, decompression support,
TransFR™ I/O and dual-boot and multi-boot image support.
2.18.1.1. TransFR (Transparent Field Reconfiguration)

TransFR I/O (TFR) is a unique Lattice technology that allows you to update their logic in the field without interrupting
system operation using a single ispVM command. TransFR I/O allows I/O states to be frozen during device
configuration. This allows the device to be field updated with a minimum of system disruption and downtime. Refer to
Minimizing System Interruption During Configuration Using TransFR Technology (TN1087) for details.
2.18.1.2. Dual-Boot and Multi-Boot Image Support

Dual-boot and multi-boot images are supported for applications requiring reliable remote updates of configuration
data for the system FPGA. After the system is running with a basic configuration, a new boot image can be downloaded
remotely and stored in a separate location in the configuration storage device. Any time after the update the
ECP5/ECP5-5G devices can be re-booted from this new configuration file. If there is a problem, such as corrupt data
during download or incorrect version number with this new boot image, the ECP5/ECP5-5G device can revert back to
the original backup golden configuration and try again. This all can be done without power cycling the system. For more
information, refer to ECP5 and ECP5-5G sysCONFIG Usage Guide (FPGA-TN-02039).
2.18.2. Single Event Upset (SEU) Support

ECP5/ECP5-5G devices support SEU mitigation with three supporting functions:
 SED – Soft Error Detect
 SEC – Soft Error Correction
 SEI – Soft Error Injection
ECP5/ECP5-5G devices have dedicated logic to perform Cycle Redundancy Code (CRC) checks. During configuration, the
configuration data bitstream can be checked with the CRC logic block. In addition, the ECP5/ECP5-5G device can also be
programmed to utilize a Soft Error Detect (SED) mode that checks for soft errors in configuration SRAM. The SED
operation can be run in the background during user mode. If a soft error occurs, during user mode (normal operation)
the device can be programmed to generate an error signal.
FPGA-DS-02012-2.1 45
Data Sheet
When an error is detected, and your error handling software determines the error did not create any risk to the system
operation, the SEC tool allows the device to be re-configured in the background to correct the affected bit. This
operation allows the user functions to continue to operate without stopping the system function.
Additional SEI tool is also available in the Diamond Software, by creating a frame of data to be programmed into the
device in the background with one bit changed, without stopping the user functions on the device. This emulates an
SEU situation, allowing you to test and monitor its error handling software.
For further information on SED support, refer to LatticeECP3, ECP5 and ECP5-5G Soft Error Detection (SED)/Correction
(SEC) Usage Guide (TN1184).
2.18.3. On-Chip Oscillator

Every ECP5/ECP5-5G device has an internal CMOS oscillator which is used to derive a Master Clock (MCLK) for
configuration. The oscillator and the MCLK run continuously and are available to user logic after configuration is
completed. The software default value of the MCLK is nominally 2.4 MHz. Table 2.16 lists all the available MCLK
frequencies. When a different Master Clock is selected during the design process, the following sequence takes place:
Device powers up with a nominal Master Clock frequency of 2.4 MHz.
During configuration, you can select a different master clock frequency.
The Master Clock frequency changes to the selected frequency once the clock configuration bits are received.
If you do not select a master clock frequency, then the configuration bitstream defaults to the MCLK frequency of
2.4 MHz.
This internal oscillator is available to you by routing it as an input clock to the clock tree. For further information on the
use of this oscillator for configuration or user mode, refer to ECP5 and ECP5-5G sysCONFIG Usage Guide (FPGA-TN-
02039) and ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide (TN1263).
Table 2.16. Selectable Master Clock (MCLK) Frequencies during Configuration (Nominal)
MCLK Frequency (MHz)
2.4
4.8
9.7
19.4
38.8
62
2.19. Density Shifting

The ECP5/ECP5-5G family is designed to ensure that different density devices in the same family and in the same
package have the same pinout. Furthermore, the architecture ensures a high success rate when performing design
migration from lower density devices to higher density devices. In many cases, it is also possible to shift a lower
utilization design targeted for a high-density device to a lower density device. However, the exact details of the final
resource utilization impacts the likelihood of success in each case. An example is that some user I/O may become No
Connects in smaller devices in the same package. Refer to the ECP5/ECP5-5G Pin Migration Tables and Diamond
software for specific restrictions and limitations.
46 FPGA-DS-02012-2.1
Data Sheet
3. DC and Switching Characteristics

3.1. Absolute Maximum Ratings
Table 3.1. Absolute Maximum Ratings
Symbol Parameter Min Max Unit
VCC Supply Voltage –0.5 1.32 V
VCCA Supply Voltage –0.5 1.32 V
VCCAUX, VCCAUXA Supply Voltage –0.5 2.75 V
VCCIO Supply Voltage –0.5 3.63 V
— Input or I/O Transient Voltage Applied –0.5 3.63 V
VCCHRX, VCCHTX SERDES RX/TX Buffer Supply Voltages –0.5 1.32 V
— Voltage Applied on SERDES Pins –0.5 1.80 V
TA Storage Temperature (Ambient) –65 150 °C
TJ Junction Temperature — +125 °C
Notes:
1. Stress above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is
not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
3.2. Recommended Operating Conditions

Table 3.2. Recommended Operating Conditions
ECP5 1.045 1.155 V
VCC2 Core Supply Voltage
ECP5-5G 1.14 1.26 V
VCCAUX2, 4 Auxiliary Supply Voltage — 2.375 2.625 V
VCCIO 2, 3 I/O Driver Supply Voltage — 1.14 3.465 V
VREF1 Input Reference Voltage — 0.5 1.0 V
tJCOM Junction Temperature, Commercial Operation — 0 85 °C
tJIND Junction Temperature, Industrial Operation — –40 100 °C
SERDES External Power Supply5
ECP5UM 1.045 1.155 V
VCCA SERDES Analog Power Supply
ECP5-5G 1.164 1.236 V
VCCAUXA SERDES Auxiliary Supply Voltage — 2.374 2.625 V
ECP5UM 0.30 1.155 V
VCCHRX6 SERDES Input Buffer Power Supply
ECP5-5G 0.30 1.26 V
ECP5UM 1.045 1.155 V
VCCHTX SERDES Output Buffer Power Supply
ECP5-5G 1.14 1.26 V
Notes:
1. For correct operation, all supplies except VREF must be held in their valid operation range. This is true independent of feature
usage.
2. All supplies with same voltage, except SERDES Power Supplies, should be connected together.
3. See recommended voltages by I/O standard in Table 3.4.
4. VCCAUX ramp rate must not exceed 30 mV/µs during power-up when transitioning between 0 V and 3 V.
5. Refer to ECP5 and ECP5-5G SERDES/PCS Usage Guide (TN1261) for information on board considerations for SERDES power
supplies.
6. VCCHRX is used for Rx termination. It can be biased to Vcm if external AC coupling is used. This voltage needs to meet all the HDin
input voltage level requirements specified in the Rx section of this Data Sheet.
FPGA-DS-02012-2.1 47
Data Sheet
3.3. Power Supply Ramp Rates

Table 3.3. Power Supply Ramp Rates
Symbol Parameter Min Typ Max Unit
tRAMP Power Supply ramp rates for all supplies 0.01 — 10 V/ms
Note: Assumes monotonic ramp rates.
3.4. Power-On-Reset Voltage Levels

Table 3.4. Power-On-Reset Voltage Levels
Symbol Parameter Min Typ Max Unit
Power-On-Reset ramp-up VCC 0.90 — 1.00 V

VPORUP All Devices trip point (Monitoring VCC, VCCAUX 2.00 — 2.20 V
VCCAUX, and VCCIO8) VCCIO8 0.95 — 1.06 V
Power-On-Reset ramp- VCC 0.77 — 0.87 V
VPORDN All Devices down trip point (Monitoring
VCC, and VCCAUX VCCAUX 1.80 — 2.00 V
Notes:
 These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified
under recommended operating conditions.
 Only VCCIO8 has a Power-On-Reset ramp up trip point. All other VCCIOs do not have Power-On-Reset ramp up detection.
 VCCIO8 does not have a Power-On-Reset ramp down detection. VCCIO8 must remain within the Recommended Operating
Conditions to ensure proper operation.
3.5. Power up Sequence

Power-On-Reset (POR) puts the ECP5/ECP5-5G device in a reset state. POR is released when VCC, VCCAUX, and VCCIO8 are
ramped above the VPORUP voltage, as specified above.
VCCIO8 controls the voltage on the configuration I/O pins. If the ECP5/ECP5-5G device is using Master SPI mode to
download configuration data from external SPI Flash, it is required to ramp VCCIO8 above VIH of the external SPI Flash,
before at least one of the other two supplies (VCC and/or VCCAUX) is ramped to VPORUP voltage level. If the system cannot
meet this power up sequence requirement, and requires the VCCIO8 to be ramped last, then the system must keep either
PROGRAMN or INITN pin LOW during power up, until VCCIO8 reaches VIH of the external SPI Flash. This ensures the
signals driven out on the configuration pins to the external SPI Flash meet the VIH voltage requirement of the SPI Flash.
For LFE5UM/LFE5UM5G devices, it is required to power up VCCA, before VCCAUXA is powered up.
3.6. Hot Socketing Specifications

Table 3.5. Hot Socketing Specifications
Symbol Parameter Condition Min Typ Max Unit
Input or I/O Leakage Current
IDK_HS for Top and Bottom Banks 0 VIN VIH (Max) — — ±1 mA
Only
Input or I/O Leakage Current 0 VIN < VCCIO — — ±1 mA
IDK
for Left and Right Banks Only VCCIO VIN VCCIO + 0.5 V — 18 — mA
Notes:
1. VCC, VCCAUX and VCCIO should rise/fall monotonically.
2. IDK is additive to IPU, IPW or IBH.
3. LVCMOS and LVTTL only.
4. Hot socket specification defines when the hot socketed device's junction temperature is at 85 oC or below. When the hot
socketed device's junction temperature is above 85 oC, the IDK current can exceed ±1 mA.
48 FPGA-DS-02012-2.1
Data Sheet
3.7. Hot Socketing Requirements

Table 3.6. Hot Socketing Requirements
Description Min Typ Max Unit
Input current per SERDES I/O pin when device is powered down and inputs
— — 8 mA
driven.
Input current per HDIN pin when device power supply is off, inputs driven1, 2 — — 15 mA
Current per HDIN pin when device power ramps up, input driven3 — — 50 mA
Current per HDOUT pin when device power supply is off, outputs pulled up4 — — 30 mA
Notes:
1. Device is powered down with all supplies grounded, both HDINP and HDINN inputs driven by a CML driver with maximum
allowed output VCCHTX, 8b/10b data, no external AC coupling.
2. Each P and N input must have less than the specified maximum input current during hot plug. For a device with 2 DCU, the total
input current would be 15 mA * 4 channels * 2 input pins per channel = 120 mA.
3. Device power supplies are ramping up (VCCA and VCCAUX), both HDINP and HDINN inputs are driven by a CML driver with
maximum allowed output VCCHTX, 8b/10b data, internal AC coupling.
4. Device is powered down with all supplies grounded. Both HDOUTP and HDOUN outputs are pulled up to V CCHTX by the far end
receiver termination of 50 Ω single ended.
3.8. ESD Performance

Refer to the ECP5 and ECP5-5G Product Family Qualification Summary for complete qualification data, including ESD
performance.
3.9. DC Electrical Characteristics

Over Recommended Operating Conditions
Table 3.7. DC Electrical Characteristics
Symbol Parameter Condition Min Typ Max Unit
IIL, IIH1, 4 Input or I/O Low Leakage 0 VIN VCCIO — — 10 µA
IIH1, 3 Input or I/O High Leakage VCCIO < VIN VIH(MAX) — — 100 µA
I/O Active Pull-up Current,
0.7 VCCIO VIN VCCIO –30 — — µA
sustaining logic HIGH state
IPU
I/O Active Pull-up Current, pulling
0 VIN 0.7 VCCIO — — –150 µA
down from logic HIGH state
I/O Active Pull-down Current,
0 VIN  VIL (MAX) 30 — — µA
sustaining logic LOW state
IPD
I/O Active Pull-down Current, — —
0 VIN VCCIO 150 µA
pulling up from logic LOW state
VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,
C1 I/O Capacitance2 — 5 8 pf
VCC = 1.2 V, VIO = 0 to VIH(MAX)
VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,
C2 Dedicated Input Capacitance2 — 5 7 pf
VCC = 1.2 V, VIO = 0 to VIH(MAX)
Hysteresis for Single-Ended VCCIO = 3.3 V — 300 — mV
VHYST
Inputs VCCIO = 2.5 V — 250 — mV
Notes:
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is
not measured with the output driver active. Bus maintenance circuits are disabled.
2. TA 25 oC, f = 1.0 MHz.
3. Applicable to general purpose I/O in top and bottom banks.
4. When used as VREF, maximum leakage= 25 µA.
FPGA-DS-02012-2.1 49
Data Sheet
3.10. Supply Current (Standby)

Over recommended operating conditions.
Table 3.8. ECP5/ECP5-5G Supply Current (Standby)
Symbol Parameter Device Typical Unit
LFE5U-12F/ LFE5U-25F/ LFE5UM-25F 77 mA
LFE5UM5G-25F 77 mA
LFE5U-45F/ LFE5UM-45F 116 mA
ICC Core Power Supply Current
LFE5UM5G-45F 116 mA
LFE5U-85F/ LFE5UM-85F 212 mA
LFE5UM5G-85F 212 mA
LFE5U-12F/ LFE5U-25F/ LFE5UM-25F/
16 mA
LFE5UM5G-25F
ICCAUX Auxiliary Power Supply Current
LFE5U-45F/ LFE5UM-45F/ LFE5UM5G-45F 17 mA
LFE5U-85F/ LFE5UM-85F/ LFE5UM5G-85F 26 mA
LFE5U-12F/ LFE5U-25F/ LFE5UM-25F/
0.5 mA
LFE5UM5G-25F
ICCIO Bank Power Supply Current (Per Bank)
LFE5U-45F/ LFE5UM-45F/ LFE5UM5G-45F 0.5 mA
LFE5U-85F/ LFE5UM-85F/ LFE5UM5G-85F 0.5 mA
LFE5UM-25F 11 mA
LFE5UM5G-25F 12 mA
SERDES Power Supply Current (Per LFE5UM-45F 9.5 mA
ICCA
Dual) LFE5UM5G-45F 11 mA
LFE5UM-85F 9.5 mA
LFE5UM5G-85F 11 mA
Notes:
 For further information on supply current, see the list of technical documentation in Supplemental Information section.
 Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND.
 Frequency 0 Hz.
 Pattern represents a blank configuration data file.
 TJ = 85 °C, power supplies at nominal voltage.
 To determine the ECP5/ECP5-5G peak start-up current, use the Power Calculator tool in the Lattice Diamond Design Software.
50 FPGA-DS-02012-2.1
Data Sheet
3.11. SERDES Power Supply Requirements1, 2, 3

Table 3.9. ECP5UM
Symbol Description Typ Max Unit
Standby (Power Down)
ICCA-SB VCCA Power Supply Current (Per Channel) 4 9.5 mA
ICCHRX-SB4 VCCHRX, Input Buffer Current (Per Channel) — 0.1 mA
ICCHTX-SB VCCHTX, Output Buffer Current (Per Channel) — 0.9 mA
Operating (Data Rate = 3.125 Gb/s)
ICCA-OP VCCA Power Supply Current (Per Channel) 43 54 mA
ICCHRX-OP 5 VCCHRX, Input Buffer Current (Per Channel) 0.4 0.5 mA
ICCHTX-OP VCCHTX, Output Buffer Current (Per Channel) 10 13 mA
Operating (Data Rate = 270 Mb/s)
Notes:
1. Rx Equalization enabled, Tx De-emphasis (pre-cursor and post-cursor) disabled
2. Per Channel current is calculated with both channels on in a Dual, and divide current by two. If only one channel is on, current is
higher.
3. To calculate with Tx De-emphasis enabled, use the Diamond Power Calculator tool.
4. For ICCHRX-SB, during Standby, input termination on Rx are disabled.
5. For ICCHRX-OP, during operational, the max specified when external AC coupling is used. If externally DC coupled, the power is
based on current pulled down by external driver when the input is driven to LOW.
FPGA-DS-02012-2.1 51
Data Sheet
Table 3.10. ECP5-5G

Symbol Description Typ Max Unit
Standby (Power Down)
ICCA-SB VCCA Power Supply Current (Per Channel) 4 9.5 mA
ICCHRX-SB4 VCCHRX, Input Buffer Current (Per Channel) — 0.1 mA
ICCHTX-SB VCCHTX, Output Buffer Current (Per Channel) — 0.9 mA
Operating (Data Rate = 5 Gb/s)
Operating (Data Rate = 270 Mb/s)
ICCHRX-OP5 VCCHRX, Input Buffer Current (Per Channel) 0.4 0.5 mA
Notes:
1. Rx Equalization enabled, Tx De-emphasis (pre-cursor and post-cursor) disabled
2. Per Channel current is calculated with both channels on in a Dual, and divide current by two. If only one channel is on, current is
higher.
3. To calculate with Tx De-emphasis enabled, use the Diamond Power Calculator tool.
4. For ICCHRX-SB, during Standby, input termination on Rx are disabled.
5. For ICCHRX-OP, during operational, the max specified when external AC coupling is used. If externally DC coupled, the power is
based on current pulled down by external driver when the input is driven to LOW.
52 FPGA-DS-02012-2.1
Data Sheet
3.12. sysI/O Recommended Operating Conditions

Table 3.11. sysI/O Recommended Operating Conditions
VCCIO VREF (V)
Standard
Min Typ Max Min Typ Max
LVCMOS331 3.135 3.3 3.465 — — —
LVCMOS33D Output 3.135 3.3 3.465 — — —
LVCMOS25D Output 2.375 2.5 2.625 — — —
LVCMOS251 2.375 2.5 2.625 — — —
LVCMOS18 1.71 1.8 1.89 — — —
LVCMOS15 1.425 1.5 1.575 — — —
LVCMOS121 1.14 1.2 1.26 — — —
LVTTL331 3.135 3.3 3.465 — — —
SSTL15_I, _II2 1.43 1.5 1.57 0.68 0.75 0.9
SSTL18_I, _II2 1.71 1.8 1.89 0.833 0.9 0.969
SSTL135_I, _II2 1.28 1.35 1.42 0.6 0.675 0.75
HSUL122 1.14 1.2 1.26 0.588 0.6 0.612
MIPI D-PHY LP Input3, 5 1.425 1.5 1.575 — — —
LVDS251, 3 2.375 2.5 2.625 — — —
subLVS3 (Input only) — — — — — —
SLVS3 (Input only) — — — — — —
LVDS25E Output 2.375 2.5 2.625 — — —
MLVDS251, 3 2.375 2.5 2.625 — — —
MLVDS25E Output 2.375 2.5 2.625 — — —
LVPECL331, 3 3.135 3.3 3.465 — — —
LVPECL33E Output 3.135 3.3 3.465 — — —
BLVDS251, 3 2.375 2.5 2.625 — — —
BLVDS25E Output 2.375 2.5 2.625 — — —
HSULD12D2, 3 1.14 1.2 1.26 — — —
SSTL135D_I, II2, 3 1.28 1.35 1.42 — — —
SSTL15D_I, II2, 3 1.43 1.5 1.57 — — —
SSTL18D_I1, 2, 3, II1, 2, 3 1.71 1.8 1.89 — — —
Notes:
1. For input voltage compatibility, refer to ECP5 and ECP5-5G sysI/O Usage Guide (FPGA-TN-02032).
2. VREF is required when using Differential SSTL and HSUL to interface to DDR/LPDDR memories.
3. These differential inputs use LVDS input comparator, which uses VCCAUX power
4. All differential inputs and LVDS25 output are supported in the Left and Right banks only. Refer to ECP5 and ECP5-5G sysI/O
Usage Guide (FPGA-TN-02032) for details.
5. MIPI D-PHY LP input can be implemented by powering VCCIO to 1.5 V, and select MIPI LP primitive to meet MIPI Alliance spec on
VIH and VIL. It can also be implemented as LVCMOS12 with VCCIO at 1.2 V, which would meet VIH/VIL spec on LVCMOS12.
FPGA-DS-02012-2.1 53
Data Sheet
3.13. sysI/O Single-Ended DC Electrical Characteristics

Table 3.12. Single-Ended DC Characteristics
Input/Output VIL VIH VOL Max VOH Min
IOL1 (mA) IOH1 (mA)
Standard Min (V) Max (V) Min (V) Max (V) (V) (V)
VCCIO – 0.4 –16, –12,

LVCMOS33 –0.3 0.8 2.0 3.465 0.4 16, 12, 8, 4
–8, –4
LVCMOS25 –0.3 0.7 1.7 3.465 0.4 VCCIO – 0.4 12, 8, 4 –12, –8, –4
LVCMOS18 –0.3 0.35 VCCIO 0.65 VCCIO 3.465 0.4 VCCIO – 0.4 12, 8, 4 –12, –8, –4
LVCMOS15 –0.3 0.35 VCCIO 0.65 VCCIO 3.465 0.4 VCCIO – 0.4 8, 4 –8, –4
LVCMOS12 –0.3 0.35 VCCIO 0.65 VCCIO 3.465 0.4 VCCIO – 0.4 8, 4 –8, –4
–16, –12,
LVTTL33 –0.3 0.8 2.0 3.465 0.4 VCCIO – 0.4 16, 12, 8, 4
–8, –4
SSTL18_I VREF –
–0.3 VREF + 0.125 3.465 0.4 VCCIO – 0.4 6.7 –6.7
(DDR2 Memory) 0.125
SSTL18_II –0.3 VREF – VREF + 0.125 3.465 0.28 VCCIO – 0.28 13.4 –13.4
SSTL15 _I 0.125
–0.3 VREF – 0.1
VREF + 0.1 3.465 0.31 VCCIO – 0.31 7.5 –7.5
(DDR3 Memory)
SSTL15_II
–0.3 VREF – 0.1 VREF + 0.1 3.465 0.31 VCCIO – 0.31 8.8 –8.8
(DDR3 Memory)
SSTL135_I
–0.3 VREF – 0.09 VREF + 0.09 3.465 0.27 VCCIO – 0.27 7 –7
(DDR3L Memory)
SSTL135_II
–0.3 VREF – 0.09 VREF + 0.09 3.465 0.27 VCCIO – 0.27 8 –8
(DDR3L Memory)
MIPI D-PHY (LP)3 –0.3 0.55 0.88 3.465 — — — —
HSUL12
(LPDDR2/3 –0.3 VREF – 0.1 VREF + 0.1 3.465 0.3 VCCIO – 0.3 4 –4
Memory)
Notes:
1. For electromigration, the average DC current drawn by the I/O pads within a bank of I/O shall not exceed 10 mA per I/O (All I/O
used in the same VCCIO).
2. Not all I/O types are supported in all banks. Refer to ECP5 and ECP5-5G sysI/O Usage Guide (FPGA-TN-02032) for details.
3. MIPI D-PHY LP input can be implemented by powering VCCIO to 1.5 V, and select MIPI LP primitive to meet MIPI Alliance spec on
VIH and VIL. It can also be implemented as LVCMOS12 with VCCIO at 1.2 V, which would meet VIH/VIL spec on LVCMOS12.
54 FPGA-DS-02012-2.1
Data Sheet
3.14. sysI/O Differential Electrical Characteristics

3.14.1. LVDS
Table 3.13. LVDS
Parameter Description Test Conditions Min Typ Max Unit
VINP, VINM Input Voltage — 0 — 2.4 V
VCM Input Common Mode Voltage Half the sum of the two Inputs 0.05 — 2.35 V
VTHD Differential Input Threshold Difference between the two Inputs ±100 — — mV
IIN Input Current Power On or Power Off — — ±10 µA
VOH Output High Voltage for VOP or VOM RT = 100 Ω — 1.38 1.60 V
VOL Output Low Voltage for VOP or VOM RT = 100 Ω 0.9 V 1.03 — V
VOD Output Voltage Differential (VOP - VOM), RT = 100 Ω 250 350 450 mV
Change in VOD Between High and
VOD — — — 50 mV
Low
VOS Output Voltage Offset (VOP + VOM)/2, RT = 100 Ω 1.125 1.25 1.375 V
VOS Change in VOS Between H and L — — — 50 mV
VOD = 0 V Driver outputs shorted to
ISAB Output Short Circuit Current — — 12 mA
each other
Note: On the left and right sides of the device, this specification is valid only for VCCIO = 2.5 V or 3.3 V.
3.14.2. SSTLD
All differential SSTL outputs are implemented as a pair of complementary single-ended outputs. All allowable
single-ended output classes (class I and class II) are supported in this mode.
3.14.3. LVCMOS33D
All I/O banks support emulated differential I/O using the LVCMOS33D I/O type. This option, along with the external
resistor network, provides the system designer the flexibility to place differential outputs on an I/O bank with 3.3 V
VCCIO. The default drive current for LVCMOS33D output is 12 mA with the option to change the device strength to 4 mA,
8 mA, 12 mA, or 16 mA. Follow the LVCMOS33 specifications for the DC characteristics of the LVCMOS33D.
FPGA-DS-02012-2.1 55
Data Sheet
3.14.4. LVDS25E
The top and bottom sides of ECP5/ECP5-5G devices support LVDS outputs via emulated complementary LVCMOS
outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3.1 is one possible
solution for point-to-point signals.
VCCIO = 2.5 V (±5%)

RS = 158
(±1%)
8 mA
RS = 140 RS = 100
VCCIO = 2.5 V (±5%) (±1%) (±1%)
RS = 158
(±1%)
8 mA
Transmission line, Zo = 100 differential

ON-chip OFF-chip ON-chip OFF-chip
Figure 3.1. LVDS25E Output Termination Example
Table 3.14. LVDS25E DC Conditions

Parameter Description Typical Unit
VCCIO Output Driver Supply (±5%) 2.50 V
ZOUT Driver Impedance 20 
RS Driver Series Resistor (±1%) 158 
RP Driver Parallel Resistor (±1%) 140 
RT Receiver Termination (±1%) 100 
VOH Output High Voltage 1.43 V
VOL Output Low Voltage 1.07 V
VOD Output Differential Voltage 0.35 V
VCM Output Common Mode Voltage 1.25 V
ZBACK Back Impedance 100.5 
IDC DC Output Current 6.03 mA
Note: For input buffer, see Table 3.13.
56 FPGA-DS-02012-2.1
Data Sheet
3.14.5. BLVDS25
The ECP5/ECP5-5G devices support the BLVDS standard. This standard is emulated using complementary LVCMOS
outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when
multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3.2 is one
possible solution for bi-directional multi-point differential signals.
Heavily loaded backplane, effective Zo ~ 45 Ω to 90 Ω differential

2.5 V 2.5 V
R S = 90 Ω R S = 90 Ω
16 mA 16 mA
45 Ω – 90 Ω R TL 45 Ω – 90 Ω R TR
2.5 V 2.5 V
16 mA 16 mA
R S = 90 Ω R S = 90 Ω
R S = 90 Ω R S = 90 Ω
. R. =.90 Ω
S
R S = 90 Ω
+ +
– –
– –
+
+
2.5 V 2.5 V 2.5 V 2.5 V
16 mA 16 mA 16 mA 16 mA
Figure 3.2. BLVDS25 Multi-point Output Example

Table 3.15. BLVDS25 DC Conditions
Typical
Parameter Description Unit
Zo = 45  Zo = 90 
VCCIO Output Driver Supply (±5%) 2.50 2.50 V
ZOUT Driver Impedance 10.00 10.00 
RS Driver Series Resistor (±1%) 90.00 90.00 
RTL Driver Parallel Resistor (±1%) 45.00 90.00 
RTR Receiver Termination (±1%) 45.00 90.00 
VOH Output High Voltage 1.38 1.48 V
VOL Output Low Voltage 1.12 1.02 V
VOD Output Differential Voltage 0.25 0.46 V
VCM Output Common Mode Voltage 1.25 1.25 V
IDC DC Output Current 11.24 10.20 mA
FPGA-DS-02012-2.1 57
Data Sheet
3.14.6. LVPECL33
The ECP5/ECP5-5G devices support the differential LVPECL standard. This standard is emulated using complementary
LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard is
supported by the LVDS differential input buffer. The scheme shown in Figure 3.3 is one possible solution for
point-to-point signals.
VCCIO = 3.3 V
(±5%)
RS = 93.1 Ω
(±1%)
16 mA
VCCIO = 3.3 V RP = 196 Ω RT = 100 Ω +

(±5%) RS = 93.1 Ω (±1%) (±1%) –
(±1%)
16 mA
Transmission line,
Zo = 100 Ω differential
On-chip Off-chip Off-chip On-chip
Figure 3.3. Differential LVPECL33

Table 3.16. LVPECL33 DC Conditions
Parameter Description Typical Unit
VCCIO Output Driver Supply (±5%) 3.30 V
ZOUT Driver Impedance 10 
RS Driver Series Resistor (±1%) 93 
RP Driver Parallel Resistor (±1%) 196 
RT Receiver Termination (±1%) 100 
VOH Output High Voltage 2.05 V
VOL Output Low Voltage 1.25 V
VOD Output Differential Voltage 0.80 V
VCM Output Common Mode Voltage 1.65 V
ZBACK Back Impedance 100.5 
IDC DC Output Current 12.11 mA
58 FPGA-DS-02012-2.1
Data Sheet
3.14.7. MLVDS25
The ECP5/ECP5-5G devices support the differential MLVDS standard. This standard is emulated using complementary
LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The MLVDS input standard is
supported by the LVDS differential input buffer. The scheme shown in Figure 3.4 is one possible solution for MLVDS
standard implementation. Resistor values in the figure are industry standard values for 1% resistors.
Heavily loaded backplace, effective Zo~50 Ω to 70 Ω differential

2.5 V
2.5 V
R S = 35 Ω R S = 35 Ω
16 mA 16 mA
OE R TL OE
50 Ω to 70 Ω ±1%
50 Ω to 70 Ω ±1% R TR
2.5 V
2.5 V
16 mA 16 mA
R S = 35 Ω R S = 35 Ω
OE R S = 35 Ω R S = 35 Ω R S = 35 Ω R S = 35 Ω OE
+ +
–- –
+
–
+
–
2.5 V OE 2.5 V OE 2.5 V OE 2.5 V OE
16 mA 16 mA 16 mA 1 6 mA
Figure 3.4. MLVDS25 (Multipoint Low Voltage Differential Signaling)
Table 3.17. MLVDS25 DC Conditions

Typical
Parameter Description Unit
Zo=50  Zo=70 
VCCIO Output Driver Supply (±5%) 2.50 2.50 V
ZOUT Driver Impedance 10.00 10.00 
RS Driver Series Resistor (±1%) 35.00 35.00 
RTL Driver Parallel Resistor (±1%) 50.00 70.00 
RTR Receiver Termination (±1%) 50.00 70.00 
VOH Output High Voltage 1.52 1.60 V
VOL Output Low Voltage 0.98 0.90 V
VOD Output Differential Voltage 0.54 0.70 V
VCM Output Common Mode Voltage 1.25 1.25 V
IDC DC Output Current 21.74 20.00 mA
FPGA-DS-02012-2.1 59
Data Sheet
3.14.8. SLVS
Scalable Low-Voltage Signaling (SLVS) is based on a point-to-point signaling method defined in the JEDEC JESD8-13
(SLVS-400) standard. This standard evolved from the traditional LVDS standard and relies on the advantage of its use of
smaller voltage swings and a lower common-mode voltage. The 200 mV (400 mV p-p) SLVS swing contributes to a
reduction in power.
The ECP5/ECP5-5G devices can receive differential input up to 800 Mb/s with its LVDS input buffer. This LVDS input
buffer is used to meet the SLVS input standard specified by the JEDEC standard. The SLVS output parameters are
compared to ECP5/ECP5-5G LVDS input parameters, as listed in Table 3.18.
Table 3.18. Input to SLVS
Parameter ECP5/ECP5-5G LVDS Input SLVS Output Unit
Vcm (min) 50 150 mV
Vcm (max) 2350 250 mV
Differential Voltage (min) 100 140 mV
Differential Voltage (max) — 270 mV
ECP5/ECP5-5G does not support SLVS output. However, SLVS output can be created using ECP5/ECP5-5G LVDS outputs
by level shift to meet the low Vcm/Vod levels required by SLVS. Figure 3.5 shows how the LVDS output can be shifted
external to meet SLVS levels.
2.5 V Typical
R3=15 SLVDS
R1=220
R2=47 100 Ω Diff
+ +
LVDS Z0=50
- –
R2=47
R1=220 R3=15
ECP5/ECP5-5G 2.5 V Typical

On Chip On Chip
SLVDS Peer
+ +
LVDS Z0=50
–- –-
Figure 3.5. SLVS Interface
60 FPGA-DS-02012-2.1
Data Sheet
3.15. Typical Building Block Function Performance

Table 3.19. Pin-to-Pin Performance
Function –8 Timing Unit
Basic Functions
16-Bit Decoder 5.06 ns
4:1 Mux 4.45 ns
8:1 Mux 4.63 ns
16:1 Mux 4.81 ns
32:1 Mux 4.85 ns
Notes:
1. I/O are configured with LVCMOS25 with VCCIO=2.5, 12 mA drive.
2. These functions were generated using Lattice Diamond design software tool. Exact performance may vary with the device and
the design software tool version. The design software tool uses internal parameters that have been characterized but are not
tested on every device.
3. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from Lattice Diamond
design software tool.
FPGA-DS-02012-2.1 61
Data Sheet
Table 3.20. Register-to-Register Performance

Function –8 Timing Unit
Basic Functions
16-Bit Decoder 441 MHz
4:1 Mux 441 MHz
8:1 Mux 441 MHz
16:1 Mux 441 MHz
32:1 Mux 441 MHz
8-Bit Adder 441 MHz
16-Bit Adder 441 MHz
64-Bit Adder 441 MHz
16-Bit Counter 384 MHz
64-Bit Accumulator 288 MHz
Embedded Memory Functions
1024x18 True-Dual Port RAM (Write Through or Normal), with EBR Output Registers 272 MHz
1024x18 True-Dual Port RAM (Read-Before-Write), with EBR Output Registers 214 MHz
Distributed Memory Functions
16 x 2 Pseudo-Dual Port or 16 x 4 Single Port RAM (One PFU) 441 MHz
16 x 4 Pseudo-Dual Port (Two PFUs) 441 MHz
DSP Functions
9 x 9 Multiplier (All Registers) 225 MHz
18 x 18 Multiply-Add/Sub (All Registers) 225 MHz
18 x 18 Multiply/Accumulate (Input and Output Registers) 225 MHz
Notes:
 These functions were generated using Lattice Diamond design software tool. Exact performance may vary with the device and
the design software tool version. The design software tool uses internal parameters that have been characterized but are not
tested on every device.
 Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from Lattice Diamond
design software tool.
3.16. Derating Timing Tables

Logic timing provided in the following sections of this data sheet and the Diamond design tools are worst case numbers
in the operating range. Actual delays at nominal temperature and voltage for best case process, can be much better
than the values given in the tables. The Diamond design tool can provide logic timing numbers at a particular
temperature and voltage.
62 FPGA-DS-02012-2.1
Data Sheet
3.17. Maximum I/O Buffer Speed

Table 3.21. ECP5/ECP5-5G Maximum I/O Buffer Speed
Buffer Description Max Unit
Maximum Input Frequency
LVDS25 LVDS, VCCIO = 2.5 V 400 MHz
MLVDS25 MLVDS, Emulated, VCCIO = 2.5 V 400 MHz
BLVDS25 BLVDS, Emulated, VCCIO = 2.5 V 400 MHz
MIPI D-PHY (HS Mode) MIPI Video 400 MHz
SLVS SLVS similar to MIPI 400 MHz
Mini LVDS Mini LVDS 400 MHz
LVPECL33 LVPECL, Emulated, VCCIO = 3.3 V 400 MHz
SSTL18 (all supported classes) SSTL_18 class I, II, VCCIO = 1.8 V 400 MHz
HSUL12 (all supported classes) HSUL_12 class I, II, VCCIO = 1.2 V 400 MHz
LVTTL33 LVTTL, VCCIO = 3.3 V 200 MHz
LVCMOS33 LVCMOS, VCCIO = 3.3 V 200 MHz
LVCMOS15 LVCMOS 1.5, VCCIO = 1.5 V 200 MHz
LVCMOS12 LVCMOS 1.2, VCCIO = 1.2 V 200 MHz
Maximum Output Frequency
LVDS25E LVDS, Emulated, VCCIO = 2.5 V 150 MHz
LVDS25 LVDS, VCCIO = 2.5 V 400 MHz
MLVDS25 MLVDS, Emulated, VCCIO = 2.5 V 150 MHz
BLVDS25 BLVDS, Emulated, VCCIO = 2.5 V 150 MHz
LVPECL33 LVPECL, Emulated, VCCIO = 3.3 V 150 MHz
HSUL12 (all supported classes) HSUL12 class I, II, VCCIO = 1.2 V 400 MHz
LVTTL33 LVTTL, VCCIO = 3.3 V 150 MHz
LVCMOS33 (For all drives) LVCMOS, 3.3 V 150 MHz
Notes:
 These maximum speeds are characterized but not tested on every device.
 Maximum I/O speed for differential output standards emulated with resistors depends on the layout.
 LVCMOS timing is measured with the load specified in Switching Test Conditions, Table 3.44.
 All speeds are measured at fast slew.
 Actual system operation may vary depending on user logic implementation.
 Maximum data rate equals 2 times the clock rate when utilizing DDR.
 MIPI D-PHY HS mode receiver runs 400 MHz as LVDS25. It may exceed ±0.15 UI setup/hold budget at data rate of ≤1 Gbps MIPI
Alliance Specification.
FPGA-DS-02012-2.1 63
Data Sheet
3.18. External Switching Characteristics

Over recommended commercial operating conditions.
Table 3.22. ECP5/ECP5-5G External Switching Characteristics
–8 –7 –6
Parameter Description Device Unit
Min Max Min Max Min Max
Clocks
Primary Clock
fMAX_PRI Frequency for Primary Clock Tree — — 370 — 303 — 257 MHz
Clock Pulse Width for Primary
tW_PRI — 0.8 — 0.9 — 1.0 — ns
Clock
Primary Clock Skew within a
tSKEW_PRI — — 420 — 462 — 505 ps
Device
Edge Clock
fMAX_EDGE Frequency for Edge Clock Tree — — 400 — 350 — 312 MHz
tW_EDGE Clock Pulse Width for Edge Clock — 1.175 — 1.344 — 1.50 — ns
tSKEW_EDGE Edge Clock Skew within a Bank — — 160 — 180 — 200 ps
Generic SDR Input
General I/O Pin Parameters Using Dedicated Primary Clock Input without PLL
Clock to Output - PIO Output All
tCO — 5.4 — 6.1 — 6.8 ns
Register Devices
Clock to Data Setup - PIO Input All
tSU 0 — 0 — 0 — ns
Register Devices
Clock to Data Hold - PIO Input All
tH 2.7 — 3 — 3.3 — ns
Register Devices
tSU_DEL 1.2 — 1.33 — 1.46 — ns
Register with Data Input Delay Devices
tH_DEL 0 — 0 — 0 — ns
Clock Frequency of I/O and PFU All
fMAX_IO — 400 — 350 — 312 MHz
Register Devices
General I/O Pin Parameters Using Dedicated Primary Clock Input with PLL
Clock to Output - PIO Output All
tCOPLL — 3.5 — 3.8 — 4.1 ns
Register Devices
tSUPLL 0.7 — 0.78 — 0.85 — ns
Register Devices
tHPLL 0.8 — 0.89 — 0.98 — ns
Register Devices
tSU_DELPLL 1.6 — 1.78 — 1.95 — ns
64 FPGA-DS-02012-2.1
Data Sheet

–8 –7 –6
Clock to Data Hold - PIO Input
tH_DELPLL All Devices 0 — 0 — 0 — ns
Register with Data Input Delay
Generic DDR Input
Generic DDRX1 Inputs With Clock and Data Centered at Pin (GDDRX1_RX.SCLK.Centered) Using PCLK Clock Input - Figure 3.6
tSU_GDDRX1_centered Data Setup Before CLK Input All Devices 0.52 — 0.52 — 0.52 — ns
tHD_GDDRX1_centered Data Hold After CLK Input All Devices 0.52 — 0.52 — 0.52 — ns
fDATA_GDDRX1_centered GDDRX1 Data Rate All Devices — 500 — 500 — 500 Mb/s
fMAX_GDDRX1_centered GDDRX1 CLK Frequency (SCLK) All Devices — 250 — 250 — 250 MHz
Generic DDRX1 Inputs With Clock and Data Aligned at Pin (GDDRX1_RX.SCLK.Aligned) Using PCLK Clock Input - Figure 3.7
ns +
tSU_GDDRX1_aligned Data Setup from CLK Input All Devices — –0.55 — –0.55 — –0.55
1/2 UI
ns +
tHD_GDDRX1_aligned Data Hold from CLK Input All Devices 0.55 — 0.55 — 0.55 —
1/2 UI
fDATA_GDDRX1_aligned GDDRX1 Data Rate All Devices — 500 — 500 — 500 Mb/s
fMAX_GDDRX1_aligned GDDRX1 CLK Frequency (SCLK) All Devices — 250 — 250 — 250 MHz
Generic DDRX2 Inputs With Clock and Data Centered at Pin (GDDRX2_RX.ECLK.Centered) Using PCLK Clock Input, Left and
Right sides Only - Figure 3.6
tSU_GDDRX2_centered Data Setup before CLK Input All Devices 0.321 — 0.403 — 0.471 — ns
tHD_GDDRX2_centered Data Hold after CLK Input All Devices 0.321 — 0.403 — 0.471 — ns
fMAX_GDDRX2_centered GDDRX2 CLK Frequency (ECLK) All Devices — 400 — 350 — 312 MHz
Generic DDRX2 Inputs With Clock and Data Aligned at Pin (GDDRX2_RX.ECLK.Aligned) Using PCLK Clock Input, Left and Right
sides Only - Figure 3.7
ns + 1/2
tSU_GDDRX2_aligned Data Setup from CLK Input All Devices — –0.344 — –0.42 — -0.495
UI
ns + 1/2
tHD_GDDRX2_aligned Data Hold from CLK Input All Devices 0.344 — 0.42 — 0.495 —
UI
fMAX_GDDRX2_alignedGDDRX2 CLK Frequency All Devices — 400 — 350 — 312 MHz
(ECLK)
Video DDRX71 Inputs With Clock and Data Aligned at Pin (GDDRX71_RX.ECLK) Using PLL Clock Input, Left and Right sides Only
Figure 3.11
Data Setup from CLK Input ns+(1/2+i)
tSU_LVDS71_i All Devices — –0.271 — –0.39 — –0.41
(bit i) * UI
Data Hold from CLK Input ns+(1/2+i)
tHD_LVDS71_i All Devices 0.271 — 0.39 — 0.41 —
(bit i) * UI
fDATA_LVDS71 DDR71 Data Rate All Devices — 756 — 620 — 525 Mb/s
fMAX_LVDS71 DDR71 CLK Frequency (ECLK) All Devices — 378 — 310 — 262.5 MHz
FPGA-DS-02012-2.1 65
Data Sheet

–8 –7 –6
Generic DDR Output
Generic DDRX1 Outputs With Clock and Data Centered at Pin (GDDRX1_TX.SCLK.Centered) Using PCLK Clock Input - Figure 3.6
Data Output Valid before CLK ns +
tDVB_GDDRX1_centered All Devices –0.67 — –0.67 — –0.67 —
Output 1/2 UI
Data Output Valid after CLK ns +
tDVA_GDDRX1_centered All Devices –0.67 — –0.67 — –0.67 —
Output 1/2 UI
fMAX_GDDRX1_centered GDDRX1 CLK Frequency (SCLK) All Devices — 250 — 250 — 250 MHz
Generic DDRX1 Outputs With Clock and Data Aligned at Pin (GDDRX1_TX.SCLK.Aligned) Using PCLK Clock Input - Figure 3.9
Data Output Invalid before
tDIB_GDDRX1_aligned All Devices –0.3 — –0.3 — –0.3 — ns
CLK Output
Data Output Invalid after CLK
tDIA_GDDRX1_aligned All Devices — 0.3 — 0.3 — 0.3 ns
Output
fMAX_GDDRX1_aligned GDDRX1 CLK Frequency (SCLK) All Devices — 250 — 250 — 250 MHz
Generic DDRX2 Outputs With Clock and Data Centered at Pin (GDDRX2_TX.ECLK.Centered) Using PCLK Clock Input, Left and
Right sides Only - Figure 3.8
Data Output Valid Before CLK – – ns +
tDVB_GDDRX2_centered All Devices — –0.56 — —
Output 0.442 0.676 1/2 UI
Data Output Valid After CLK ns +
tDVA_GDDRX2_centered All Devices — 0.442 — 0.56 — 0.676
Output 1/2 UI
fMAX_GDDRX2_centered GDDRX2 CLK Frequency (ECLK) All Devices — 400 — 350 — 312 MHz
Generic DDRX2 Outputs With Clock and Data Aligned at Pin (GDDRX2_TX.ECLK.Aligned) Using PCLK Clock Input, Left and Right
sides Only - Figure 3.9
Data Output Invalid before
tDIB_GDDRX2_aligned All Devices –0.16 — –0.18 — –0.2 — ns
CLK Output
Data Output Invalid after CLK
tDIA_GDDRX2_aligned All Devices — 0.16 — 0.18 — 0.2 ns
Output
fMAX_GDDRX2_aligned GDDRX2 CLK Frequency (ECLK) All Devices — 400 — 350 — 312 MHz
Video DDRX71 Outputs With Clock and Data Aligned at Pin (GDDRX71_TX.ECLK) Using PLL Clock Input, Left and Right sides Only
- Figure 3.12
Data Output Invalid before ns +
tDIB_LVDS71_i All Devices –0.16 — –0.18 — –0.2 —
CLK Output (i) * UI
Data Output Invalid after CLK ns +
tDIA_LVDS71_i All Devices — 0.16 — 0.18 — 0.2
Output (i) * UI
fDATA_LVDS71 DDR71 Data Rate All Devices — 756 — 620 — 525 Mb/s
fMAX_LVDS71 DDR71 CLK Frequency (ECLK) All Devices — 378 — 310 — 262.5 MHz
Memory Interface
DDR2/DDR3/DDR3L/LPDDR2/LPDDR3 READ (DQ Input Data are Aligned to DQS)
tDVBDQ_DDR2
tDVBDQ_DDR3
Data Output Valid before DQS – – ns + 1/2
tDVBDQ_DDR3L All Devices — –0.26 — —
Input 0.317 0.374 UI
tDVBDQ_LPDDR2
tDVBDQ_LPDDR3
tDVADQ_DDR2
tDVADQ_DDR3
Data Output Valid after DQS ns + 1/2
tDVADQ_DDR3L All Devices 0.26 — 0.317 — 0.374 —
Input UI
tDVADQ_LPDDR2
tDVADQ_LPDDR3
66 FPGA-DS-02012-2.1
Data Sheet

–8 –7 –6
fDATA_DDR2
fDATA_DDR3
fDATA_DDR3L DDR Memory Data Rate All Devices — 800 — 700 — 624 Mb/s
fDATA_LPDDR2
fDATA_LPDDR3
fMAX_DDR2
fMAX_DDR3
DDR Memory CLK
fMAX_DDR3L All Devices — 400 — 350 — 312 MHz
Frequency (ECLK)
fMAX_LPDDR2
fMAX_LPDDR3
DDR2/DDR3/DDR3L/LPDDR2/LPDDR3 WRITE (DQ Output Data are Centered to DQS)
tDQVBS_DDR2
tDQVBS_DDR3
Data Output Valid before
tDQVBS_DDR3L All Devices — –0.25 — –0.25 — -0.25 UI
DQS Output
tDQVBS_LPDDR2
tDQVBS_LPDDR3
tDQVAS_DDR2
tDQVAS_DDR3
Data Output Valid after DQS
tDQVAS_DDR3L All Devices 0.25 — 0.25 — 0.25 — UI
Output
tDQVAS_LPDDR2
tDQVAS_LPDDR3
fDATA_DDR2
fDATA_DDR3
fDATA_DDR3L DDR Memory Data Rate All Devices — 800 — 700 — 624 Mb/s
fDATA_LPDDR2
fDATA_LPDDR3
fMAX_DDR2
fMAX_DDR3
DDR Memory CLK
fMAX_DDR3L All Devices — 400 — 350 — 312 MHz
Frequency (ECLK)
fMAX_LPDDR2
fMAX_LPDDR3
Notes:
 Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the Diamond
software.
 General I/O timing numbers are based on LVCMOS 2.5, 12 mA, Fast Slew Rate, 0pf load.
 Generic DDR timing are numbers based on LVDS I/O.
 DDR2 timing numbers are based on SSTL18.
 DDR3 timing numbers are based on SSTL15.
 LPDDR2 and LPDDR3 timing numbers are based on HSUL12.
 Uses LVDS I/O standard for measurements.
 Maximum clock frequencies are tested under best case conditions. System performance may vary upon the user environment.
 All numbers are generated with the Diamond software.
FPGA-DS-02012-2.1 67
Data Sheet
Rx CLK (in)
Rx DATA (in)
tSU/tDVBDQ tSU/tDVBDQ
tHD/tDVADQ tHD/tDVADQ
Figure 3.6. Receiver RX.CLK.Centered Waveforms
1/2 UI 1/2 UI
Rx CLK (in)
1 UI
or DQS Input
Rx DATA (in)
or DQ Input
tSU
tSU
tHD
tHD
Figure 3.7. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms
1/2 UI 1/2 UI 1/2 UI 1/2 UI
Tx CLK (out)
or DQS Output
Tx DATA (out)
or DQ Output
tDVB/tDQVBS tDVB/tDQVBS
tDVA/tDQVA tDVA/tDQVAS
Figure 3.8. Transmit TX.CLK.Centered and DDR Memory Output Waveforms
68 FPGA-DS-02012-2.1
Data Sheet
1 UI
Tx CLK (out)
Tx DATA (out)
tDIB tDIB
tDIA tDIA
Figure 3.9. Transmit TX.CLK.Aligned Waveforms
Receiver – Shown for one LVDS Channel
# of Bits
Data In
756 Mb/s
Clock In
108 MHz
Bit # Bit # Bit # Bit #

0x 10 – 1 20 – 8 30 – 15 40 – 22
0x 11 – 2 21 – 9 31 – 16 41 – 23
For each Channel: 12 – 3
0x 22 – 10 32 – 17 42 – 24
7-bit Output Words 13 – 4 23 – 11 33 – 18
0x 43 – 25
to FPGA Fabric 0x 14 – 5 24 – 12 34 – 19 44 – 26
0x 15 – 6 25 – 13 35 – 20 45 – 27
0x 16 – 7 26 – 14 36 – 21 46 – 28
Transmitter – Shown for one LVDS Channel

# of Bits
Data Out
756 Mb/s
Clock Out
108 MHz
Bit # Bit # Bit # Bit #

For each Channel: 00 – 1 10 – 8 20 – 15 30 – 22
00 – 2 11 – 9 21 – 16 31 – 23
7-bit Output Words
00 – 3 12 – 10 22 – 17 32 – 24
to FPGA Fabric 00 – 4 13 – 11 33 – 25
23 – 18
00 – 5 14 – 12 24 – 19 34 – 26
00 – 6 15 – 13 25 – 20 35 – 27
00 – 7 16 – 14 26 – 21 36 – 28
Figure 3.10. DDRX71 Video Timing Waveforms
FPGA-DS-02012-2.1 69
Data Sheet
Bit 0 Bit 1 Bit i

1/2 UI 1/2 UI
CLK (in) 1 UI
DATA (in)
tSU_0
tHD_0
tSU_i
tHD_i
Figure 3.11. Receiver DDRX71_RX Waveforms
Bit 0 Bit 1 Bit i
1 UI
CLK (out)
DATA (out)
tDIB_0
tDIA_0
tDIB_i
tDIA_i
Figure 3.12. Transmitter DDRX71_TX Waveforms
70 FPGA-DS-02012-2.1
Data Sheet
3.19. sysCLOCK PLL Timing

Table 3.23. sysCLOCK PLL Timing
Parameter Descriptions Conditions Min Max Units
fIN Input Clock Frequency (CLKI, CLKFB) — 8 400 MHz
fOUT Output Clock Frequency (CLKOP, CLKOS) — 3.125 400 MHz
fVCO PLL VCO Frequency — 400 800 MHz
fPFD 3 Phase Detector Input Frequency — 10 400 MHz
AC Characteristics
tDT Output Clock Duty Cycle — 45 55 %
tPH4 Output Phase Accuracy — –5 5 %
fOUT ≥ 100 MHz — 100 ps p-p
Output Clock Period Jitter
fOUT < 100 MHz — 0.025 UIPP
fOUT ≥ 100 MHz — 200 ps p-p
tOPJIT1 Output Clock Cycle-to-Cycle Jitter
fOUT < 100 MHz — 0.050 UIPP
fPFD ≥ 100 MHz — 200 ps p-p
Output Clock Phase Jitter
fPFD < 100 MHz — 0.011 UIPP
tSPO Static Phase Offset Divider ratio = — 400 ps p-p

integer
tW Output Clock Pulse Width At 90% or 10% 0.9 — ns
tLOCK2 PLL Lock-in Time — — 15 ms
tUNLOCK PLL Unlock Time — — 50 ns
fPFD ≥ 20 MHz — 1,000 ps p-p
tIPJIT Input Clock Period Jitter
fPFD < 20 MHz — 0.02 UIPP
tHI Input Clock High Time 90% to 90% 0.5 — ns
tLO Input Clock Low Time 10% to 10% 0.5 — ns
tRST RST/ Pulse Width — 1 — ms
tRSTREC RST Recovery Time — 1 — ns
tLOAD_REG Min Pulse for CIB_LOAD_REG — 10 — ns
Min time for CIB dynamic phase controls to be stable
tROTATE-SETUP — 5 — ns
fore CIB_ROTATE
tROTATE-WD Min pulse width for CIB_ROTATE to maintain 0 or 1 — 4 — VCO cycles
Notes:
1. Jitter sample is taken over 10,000 samples for Periodic jitter, and 2,000 samples for Cycle-to-Cycle jitter of the primary PLL
output with clean reference clock with no additional I/O toggling.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. Period jitter and cycle-to-cycle jitter numbers are guaranteed for fPFD > 10 MHz. For fPFD < 10 MHz, the jitter numbers may not
be met in certain conditions.
FPGA-DS-02012-2.1 71
Data Sheet
3.20. SERDES High-Speed Data Transmitter

Table 3.24. Serial Output Timing and Levels
Symbol Description Min Typ Max Unit
VTX-DIFF-PP Peak-Peak Differential voltage on selected amplitude1, 2 –25% — 25% mV, p-p
VTX-CM-DC Output common mode voltage — VCCHTX / 2 — mV, p-p
TTX-R Rise time (20% to 80%) 50 — — ps
TTX-F Fall time (80% to 20%) 50 — — ps
TTX-CM-AC-P RMS AC peak common-mode output voltage — — 20 mV
Single ended output impedance for 50/75 Ω –20% 50/75 20% Ω
ZTX_SE
Single ended output impedance for 6K Ω –25% 6K 25% Ω
RLTX_DIFF Differential return loss (with package included) 3 — — –10 dB
RLTX_COM Common mode return loss (with package included) 3 — — –6 dB
Notes:
1. Measured with 50 Ω Tx Driver impedance at VCCHTX±5%.
2. Refer to ECP5 and ECP5-5G SERDES/PCS Usage Guide (TN1261) for settings of Tx amplitude.
3. Return los = −10 dB (differential), –6 dB (common mode) for 100 MHz ≤ f <= 1.6 GHz with 50 Ω output impedance configuration.
This includes degradation due to package effects.
Table 3.25. Channel Output Jitter

Description Frequency Min Typ Max Unit
Deterministic 5 Gb/s — — TBD UI, p-p
Random 5 Gb/s — — TBD UI, p-p
Total 5 Gb/s — — TBD UI, p-p
Deterministic 3.125 Gb/s — — 0.17 UI, p-p
Random 3.125 Gb/s — — 0.25 UI, p-p
Total 3.125 Gb/s — — 0.35 UI, p-p
Random 2.5 Gb/s — — 0.20 UI, p-p
Total 2.5 Gb/s — — 0.35 UI, p-p
Random 1.25 Gb/s — — 0.22 UI, p-p
Total 1.25 Gb/s — — 0.24 UI, p-p
Notes:
 Values are measured with PRBS 27-1, all channels operating, FPGA logic active, I/O around SERDES pins quiet, reference clock @
10X mode.
 For ECP5-5G family devices only.
72 FPGA-DS-02012-2.1
Data Sheet
3.21. SERDES/PCS Block Latency

Table 3.26 describes the latency of each functional block in the transmitter and receiver. Latency is given in parallel
clock cycles. Figure 3.13 shows the location of each block.
Table 3.26. SERDES/PCS Latency Breakdown
Item Description Min Avg Max Fixed Bypass Unit3
Transmit Data Latency1
FPGA Bridge - Gearing disabled with same clocks 3 — 4 — 1 byte clk
T1
FPGA Bridge - Gearing enabled 5 — 7 — — word clk
T2 8b10b Encoder — — — 2 1 byte clk
T3 SERDES Bridge transmit — — — 2 1 byte clk
Serializer: 8-bit mode — — — 15 + 1 — UI + ps
T4
Serializer: 10-bit mode — — — 18 + 1 — UI + ps
Pre-emphasis ON — — — 1 + 2 — UI + ps
T5
Pre-emphasis OFF — — — 0 + 3 — UI + ps
Receive Data Latency2
Equalization ON — — — 1 — UI + ps
R1
Equalization OFF — — — 2 — UI + ps
Deserializer: 8-bit mode — — — 10 + 3 — UI + ps
R2
Deserializer: 10-bit mode — — — 12 + 3 — UI + ps
R3 SERDES Bridge receive — — — 2 — byte clk
R4 Word alignment 3.1 — 4 — 1 byte clk
R5 8b10b decoder — — — 1 0 byte clk
R6 Clock Tolerance Compensation 7 15 23 — 1 byte clk
FPGA Bridge - Gearing disabled with same clocks 4 — 5 — 1 byte clk
R7
FPGA Bridge - Gearing enabled 7 — 9 — — word clk
Notes:
1. 1 = –245 ps, 2 = +88 ps, 3 = +112 ps.
2. 1 = +118 ps, 2 = +132 ps, 3 = +700 ps.
3. byte clk = 8 UI (8-bit mode), or 10 UI (10-bit mode); word clk = 16UI (8-bit mode), or 20 UI (10-bit mode).
SERDES SERDES Bridge PCS FPGA Bridge FPGA Core

REFCLK Recovered Clock FPGA
EBRD Clock
R4 R5 R6
R2 R3 R7
R1
WA DEC Elastic
HDINPi Deserializer Polarity Buffer Down Receive Data
EQ CDR FIFO Sample
1:8/1:10 Adjust
HDINNi FIFO
BYPASS BYPASS
Receiver BYPASS BYPASS
FPGA
Receive Clock
REFCLK Transmit Clock

TX PLL
FPGA
T2 T1 Transmit Clock
T3
T5 T4 Encoder Up
Polarity Sample Transmit Data
HDOUTPi Adjust FIFO
Serializer
HDOUTNi 8:1/10:1
BYPASS
BYPASS BYPASS
Transmitter
Figure 3.13. Transmitter and Receiver Latency Block Diagram
FPGA-DS-02012-2.1 73
Data Sheet
3.22. SERDES High-Speed Data Receiver

Table 3.27. Serial Input Data Specifications
VRX-DIFF-S Differential input sensitivity 150 — 1760 mV, p-p
VRX-IN Input levels 0 — VCCA +0.52 V
Input common mode range (internal DC coupled VCCA
VRX-CM-DCCM 0.6 — V
mode)
Input common mode range (internal AC coupled
VRX-CM-ACCM 0.1 — VCCA +0.2 V
mode)2
TRX-RELOCK SCDR re-lock time1 — 1000 — Bits
ZRX-TERM Input termination 50/75 Ω /High Z –20% 50/75/5 K +20% Ω
RLRX-RL Return loss (without package) — — –10 dB
Notes:
1. This is the typical number of bit times to re-lock to a new phase or frequency within ±300 ppm, assuming 8b10b encoded data.
2. Up to 1.655 for ECP5, and 1.76 for ECP5-5G.
3.23. Input Data Jitter Tolerance

A receiver’s ability to tolerate incoming signal jitter is very dependent on jitter type. High speed serial interface
standards have recognized the dependency on jitter type and have specifications to indicate tolerance levels for
different jitter types as they relate to specific protocols. Sinusoidal jitter is considered to be a worst case jitter type.
Table 3.28. Receiver Total Jitter Tolerance Specification
Description Frequency Condition Min Typ Max Unit
Deterministic 400 mV differential eye — — TBD UI, p-p
Random 5 Gb/s 400 mV differential eye — — TBD UI, p-p
Total 400 mV differential eye — — TBD UI, p-p
Deterministic 400 mV differential eye — — 0.37 UI, p-p
Random 3.125 Gb/s 400 mV differential eye — — 0.18 UI, p-p
Total 400 mV differential eye — — 0.65 UI, p-p
Notes:
 Jitter tolerance measurements are done with protocol compliance tests: 3.125 Gb/s - XAUI Standard, 2.5 Gb/s - PCIe Standard,
1.25 Gb/s - SGMII Standard.
 For ECP5-5G family devices only.
74 FPGA-DS-02012-2.1
Data Sheet
3.24. SERDES External Reference Clock

The external reference clock selection and its interface are a critical part of system applications for this product.
Table 3.29 specifies reference clock requirements, over the full range of operating conditions.
Table 3.29. External Reference Clock Specification (refclkp/refclkn)
FREF Frequency range 50 — 320 MHz
FREF-PPM Frequency tolerance1 –1000 — 1000 ppm
2, 4
VREF-IN-SE Input swing, single-ended clock 200 — VCCAUXA mV, p-p
2*VCCAUXA mV, p-p

VREF-IN-DIFF Input swing, differential clock 200 —
differential
VREF-IN Input levels 0 — VCCAUXA + 0.4 V
3
DREF Duty cycle 40 — 60 %
TREF-R Rise time (20% to 80%) 200 500 1000 ps
TREF-F Fall time (80% to 20%) 200 500 1000 ps
ZREF-IN-TERM-DIFF Differential input termination –30% 100/HiZ +30% Ω
CREF-IN-CAP Input capacitance — — 7 pF
Notes:
1. Depending on the application, the PLL_LOL_SET and CDR_LOL_SET control registers may be adjusted for other tolerance values
as described in ECP5 and ECP5-5G SERDES/PCS Usage Guide (TN1261).
2. The signal swing for a single-ended input clock must be as large as the p-p differential swing of a differential input clock to get
the same gain at the input receiver. With single-ended clock, a reference voltage needs to be externally connected to CLKREFN
pin, and the input voltage needs to be swung around this reference voltage.
3. Measured at 50% amplitude.
4. Single-ended clocking is achieved by applying a reference voltage VREF on REFCLKN input, with the clock applied to REFCLKP
input pin. VREF should be set to mid-point of the REFCLKP voltage swing.
V+
VREF-IN
MAX < 1.56 V
N
VREF_IN_DIFF
V+
Min=200 mV
Max=2xVCCA
0V
VREF_IN_DIFF=
IVp-VnI
V+
VREF-IN
MAX < 1.56 V
VREF_IN_SE
Min=200 mV
0 V Max=VCCA
Figure 3.14. SERDES External Reference Clock Waveforms
FPGA-DS-02012-2.1 75
Data Sheet
3.25. PCI Express Electrical and Timing Characteristics

3.25.1. PCIe (2.5 Gb/s) AC and DC Characteristics
Table 3.30. PCIe (2.5 Gb/s)
Symbol Description Test Conditions Min Typ Max Unit
Transmit1
UI Unit interval — 399.88 400 400.12 ps
VTX-DIFF_P-P Differential peak-to-peak output — 0.8 1.0 1.2 V
voltage
De-emphasis differential output
VTX-DE-RATIO — –3 –3.5 –4 dB
voltage ratio
VTX-CM-AC_P RMS AC peak common-mode output
— — — 20 mV
voltage
VTX-RCV-DETECT Amount of voltage change allowed
— — — 600 mV
during receiver detection
VTX-CM-DC Tx DC common mode voltage — 0 — VCCHTX V
VTX-D+=0.0 V + 5%
ITX-SHORT Output short circuit current — — 90 mA
VTX-D-=0.0 V
ZTX-DIFF-DC Differential output impedance — 80 100 120 Ω
RLTX-DIFF Differential return loss — 10 — — dB
RLTX-CM Common mode return loss — 6.0 — — dB
TTX-RISE Tx output rise time 20% to 80% 0.125 — — UI
TTX-FALL Tx output fall time 20% to 80% 0.125 — — UI
LTX-SKEW Lane-to-lane static output skew for all

— — — 1.3 ns
lanes in port/link
TTX-EYE Transmitter eye width — 0.75 — — UI
TTX-EYE-MEDIAN-TO-MAX- Maximum time between jitter median
— — — 0.125 UI
JITTER and maximum deviation from median
Receive1, 2
UI Unit Interval — 399.88 400 400.12 ps
Differential peak-to-peak input
VRX-DIFF_P-P — 0.343 — 1.2 V
voltage
VRX-IDLE-DET-DIFF_P-P Idle detect threshold voltage — 65 — 3403 mV
RMS AC peak common-mode input
VRX-CM-AC_P — — — 150 mV
voltage
ZRX-DIFF-DC DC differential input impedance — 80 100 120 Ω
ZRX-DC DC input impedance — 40 50 60 Ω
ZRX-HIGH-IMP-DC Power-down DC input impedance — 200K — — Ω
RLRX-DIFF Differential return loss — 10 — — dB
RLRX-CM Common mode return loss — 6.0 — — dB
Notes:
1. Values are measured at 2.5 Gb/s.
2. Measured with external AC-coupling on the receiver.
3. Not in compliance with PCI Express 1.1 standard.
76 FPGA-DS-02012-2.1
Data Sheet
3.25.2. PCIe (5 Gb/s) – Preliminary AC and DC Characteristics

Table 3.31. PCIe (5 Gb/s)
Transmit1
Tx PLL bandwidth corresponding to
BWTX-PKG-PLL2 — 5 — 16 MHz
PKGTX-PLL2
PKGTX-PLL2 Tx PLL Peaking — — — 1 dB
VTX-DIFF-PP Differential p-p Tx voltage swing — 0.8 — 1.2 V, p-p
Low power differential p-p Tx voltage
VTX-DIFF-PP-LOW — 0.4 — 1.2 V, p-p
swing
VTX-DE-RATIO-3.5dB Tx de-emphasis level ratio at 3.5dB — 3 — 4 dB
VTX-DE-RATIO-6dB Tx de-emphasis level ratio at 6dB — 5.5 — 6.5 dB
TMIN-PULSE Instantaneous lone pulse width — — — UI
TTX-RISE-FALL Transmitter rise and fall time — — — UI
Transmitter Eye, including all jitter
TTX-EYE — 0.75 — — UI
sources
TTX-DJ Tx deterministic jitter > 1.5 MHz — — — 0.15 UI
ps,
TTX-RJ Tx RMS jitter < 1.5 MHz — — — 3
RMS
TRF-MISMATCH Tx rise/fall time mismatch — — — UI
50 MHz < freq <
10 — — dB
Tx Differential Return Loss, including 1.25 GHz
RLTX-DIFF
package and silicon 1.25 GHz < freq
8 — — dB
< 2.5 GHz
Tx Common Mode Return Loss, 50 MHz < freq <
RLTX-CM 6 — — dB
including package and silicon 2.5 GHz
ZTX-DIFF-DC DC differential Impedance — — — 120 Ω
Tx AC peak common mode voltage, mV,
VTX-CM-AC-PP — — —
peak-peak p-p
ITX-SHORT Transmitter short-circuit current — — — 90 mA
Transmitter DC common-mode
VTX-DC-CM — 0 — 1.2 V
voltage
VTX-IDLE-DIFF-DC Electrical Idle Output DC voltage — 0 — 5 mV
Electrical Idle Differential Output
VTX-IDLE-DIFF-AC-p — — — mV
peak voltage
VTX-RCV-DETECT Voltage change allowed during
— — — 600 mV
Receiver Detect
TTX-IDLE-MIN Min. time in Electrical Idle — 20 — — ns
Max. time from EI Order Set to valid
TTX-IDLE-SET-TO-IDLE — — — 8 ns
Electrical Idle
Max. time from Electrical Idle to valid
TTX-IDLE-TO-DIFF-DATA — — — 8 ns
differential output
LTX-SKEW Lane-to-lane output skew — — — ps
FPGA-DS-02012-2.1 77
Data Sheet
Table 3.31. PCIe (5 Gb/s)

Receive1, 2
VRX-DIFF-PP Differential Rx peak-peak voltage — 0.343 — 1.2 V, p-p
1.5 MHz – 100
Receiver random jitter tolerance ps,
TRX-RJ-RMS MHz Random — — 4.2
(RMS) RMS
noise
TRX-DJ Receiver deterministic jitter tolerance — — — 88 ps
mV,
VRX-CM-AC Common mode noise from Rx — — —
p-p
50 MHz < freq <
10 — — dB
Receiver differential Return Loss, 1.25 GHz
RLRX-DIFF
package plus silicon 1.25 GHz < freq
8 — — dB
< 2.5 GHz
Receiver common mode Return Loss,
RLRX-CM — 6 — — dB
package plus silicon
ZRX-DC Receiver DC single ended impedance — 40 — 60 Ω
Receiver DC single ended impedance
ZRX-HIGH-IMP-DC — 200K — — Ω
when powered down
mV,
VRX-CM-AC-P Rx AC peak common mode voltage — — —
peak
mv,
VRX-IDLE-DET-DIFF-PP Electrical Idle Detect Threshold — 65 — 3403
pp
LRX-SKEW Receiver lane-lane skew — — — 8 ns
Notes:
1. Values are measured at 5 Gb/s.
2. Measured with external AC-coupling on the receiver.
3. Not in compliance with PCI Express standard.
78 FPGA-DS-02012-2.1
Data Sheet
3.26. CPRI LV2 E.48 Electrical and Timing Characteristics – Preliminary

Table 3.32. CPRI LV2 E.48 Electrical and Timing Characteristics
Transmit
UI Unit Interval — 203.43 203.45 203.47 ps
TDCD Duty Cycle Distortion — — — 0.05 UI
Uncorrelated Bounded High
JUBHPJ — — — 0.15 UI
Probability Jitter
JTOTAL Total Jitter — — — 0.3 UI
ZRX-DIFF-DC DC differential Impedance — 80 — 120 Ω
TSKEW Skew between differential signals — — — 9 ps
100 MHz < freq
— — –8 dB
Tx Differential Return Loss (S22), < 3.6864 GHz
RLTX-DIFF
including package and silicon 3.6864 GHz < freq –8 + 16.6 *log
— — dB
< 4.9152 GHz (freq/3.6864)
Tx Common Mode Return Loss, 100 MHz < freq
RLTX-CM 6 — — dB
including package and silicon < 3.6864 GHz
ITX-SHORT Transmitter short-circuit current — — — 100 mA
TRISE_FALL-DIFF Differential Rise and Fall Time — — — ps
LTX-SKEW Lane-to-lane output skew — — — ps
Receive
UI Unit Interval — 203.43 203.45 203.47 ps
VRX-DIFF-PP Differential Rx peak-peak voltage — — — 1.2 V, p-p
Receiver eye opening mask, Y1 and mV,
VRX-EYE_Y1_Y2 — 62.5 — 375
Y2 diff
VRX-EYE_X1 Receiver eye opening mask, X1 — — — 0.3 UI
Receiver total jitter tolerance (not
TRX-TJ — — — 0.6 UI
including sinusoidal)
100 MHz < freq
— — –8 dB
Receiver differential Return Loss, < 3.6864 GHz
RLRX-DIFF
package plus silicon 3.6864 GHz < freq –8 + 16.6 *log
— — dB
< 4.9152 GHz (freq/3.6864)
Receiver common mode Return
RLRX-CM — 6 — — dB
Loss, package plus silicon
ZRX-DIFF-DC Receiver DC differential impedance — 80 100 120 Ω
Note: Data is measured with PRBS7 data pattern, not with PRBS-31 pattern.
FPGA-DS-02012-2.1 79
Data Sheet
3.27. XAUI/CPRI LV E.30 Electrical and Timing Characteristics

3.27.1. AC and DC Characteristics
Table 3.33. Transmit
TRF Differential rise/fall time 20% to 80% — 80 — ps
ZTX_DIFF_DC Differential impedance — 80 100 120 Ω
JTX_DDJ2, 3 Output data deterministic jitter — — — 0.17 UI
JTX_TJ1, 2, 3 Total output data jitter — — — 0.35 UI
Notes:
1. Total jitter includes both deterministic jitter and random jitter.
2. Jitter values are measured with each CML output AC coupled into a 50 Ω impedance (100 Ω differential impedance).
3. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal.

Table 3.34. Receive and Jitter Tolerance
From 100 MHz
RLRX_DIFF Differential return loss 10 — — dB
to 3.125 GHz
From 100 MHz
RLRX_CM Common mode return loss 6 — — dB
to 3.125 GHz
ZRX_DIFF Differential termination resistance — 80 100 120 Ω
JRX_DJ1, 2, 3 Deterministic jitter tolerance (peak-to-peak) — — — 0.37 UI
JRX_RJ1, 2, 3 Random jitter tolerance (peak-to-peak) — — — 0.18 UI
JRX_SJ1, 2, 3 Sinusoidal jitter tolerance (peak-to-peak) — — — 0.10 UI
JRX_TJ1, 2, 3 Total jitter tolerance (peak-to-peak) — — — 0.65 UI
TRX_EYE Receiver eye opening — 0.35 — — UI
Notes:
1. Total jitter includes deterministic jitter, random jitter and sinusoidal jitter.
2. Jitter values are measured with each high-speed input AC coupled into a 50 Ω impedance.
3.28. CPRI LV E.24/SGMII(2.5 Gbps) Electrical and Timing Characteristics

TRF1 Differential rise/fall time 20% to 80% — 80 — ps
JTX_DDJ3, 4 Output data deterministic jitter — — — 0.17 UI
Notes:
1. Rise and Fall times measured with board trace, connector and approximately 2.5 pf load.
2. Total jitter includes both deterministic jitter and random jitter. The random jitter is the total jitter minus the actual
deterministic jitter.
80 FPGA-DS-02012-2.1
Data Sheet

RLRX_DIFF Differential return loss From 100 MHz to 2.5 GHz 10 — — dB
RLRX_CM Common mode return loss From 100 MHz to 2.5 GHz 6 — — dB
JRX_DJ2, 3, 4 Deterministic jitter tolerance (peak-to-peak) — — — 0.37 UI
JRX_RJ 2, 3, 4 Random jitter tolerance (peak-to-peak) — — — 0.18 UI
JRX_SJ2, 3, 4 Sinusoidal jitter tolerance (peak-to-peak) — — — 0.10 UI
JRX_TJ 1, 2, 3, 4 Total jitter tolerance (peak-to-peak) — — — 0.65 UI
Notes:
4. Jitter tolerance, Differential Input Sensitivity and Receiver Eye Opening parameters are characterized when Full Rx Equalization
is enabled.
3.29. Gigabit Ethernet/SGMII (1.25 Gbps)/CPRI LV E.12 Electrical and Timing

Characteristics
TRF Differential rise/fall time 20% to 80% — 80 — ps
JTX_DDJ 2, 3 Output data deterministic jitter — — — 0.10 UI
Notes:
1. Total jitter includes both deterministic jitter and random jitter. The random jitter is the total jitter minus the actual
deterministic jitter.
RLRX_DIFF Differential return loss From 100 MHz to 1.25 GHz 10 — — dB
RLRX_CM Common mode return loss From 100 MHz to 1.25 GHz 6 — — dB
JRX_DJ 1, 2, 3, 4 Deterministic jitter tolerance (peak-to-peak) — — — 0.34 UI
JRX_RJ1, 2, 3, 4 Random jitter tolerance (peak-to-peak) — — — 0.26 UI
JRX_SJ 1, 2, 3, 4 Sinusoidal jitter tolerance (peak-to-peak) — — — 0.11 UI
JRX_TJ1, 2, 3, 4 Total jitter tolerance (peak-to-peak) — — — 0.71 UI
Notes:
4. Jitter tolerance, Differential Input Sensitivity and Receiver Eye Opening parameters are characterized when Full Rx Equalization
is enabled.
FPGA-DS-02012-2.1 81
Data Sheet
3.30. SMPTE SD/HD-SDI/3G-SDI (Serial Digital Interface) Electrical and Timing

Characteristics
BRSDO Serial data rate — 270 — 2975 Mb/s
TJALIGNMENT2 Serial output jitter, alignment 270 Mb/s6 — — 0.2 UI
TJALIGNMENT2 Serial output jitter, alignment 1485 Mb/s — — 0.2 UI
TJALIGNMENT1, 2 Serial output jitter, alignment 2970 Mb/s — — 0.3 UI
TJTIMING Serial output jitter, timing 270 Mb/s6 — — 0.2 UI
TJTIMING Serial output jitter, timing 1485 Mb/s — — 1 UI
TJTIMING Serial output jitter, timing 2970 Mb/s — — 2 UI
Notes:
1. Timing jitter is measured in accordance with SMPTE serial data transmission standards.
2. Jitter is defined in accordance with SMPTE RP1 184-1996 as: jitter at an equipment output in the absence of input jitter.
3. All Tx jitter are measured at the output of an industry standard cable driver, with the Lattice SERDES device configured to 50 Ω
output impedance connecting to the external cable driver with differential signaling.
4. The cable driver drives: RL=75 Ω, AC-coupled at 270, 1485, or 2970 Mb/s.
5. All LFE5UM/LFE5UM5G devices are compliant with all SMPTE compliance tests, except 3G-SDI Level-A pathological compliance
pattern test.
6. 270 Mb/s is supported with Rate Divider only.
Table 3.40. Receive

BRSDI Serial input data rate — 270 — 2970 Mb/s
Table 3.41. Reference Clock

FVCLK Video output clock frequency — 54 — 148.5 MHz
DCV Duty cycle, video clock — 45 50 55 %
Note: SD-SDI (270 Mb/s) is supported with Rate Divider only. For Single Rate: Reference Clock = 54 MHz and Rate Divider = /2. For
Tri-Rate: Reference Clock = 148.5 MHz and Rate Divider = /11.
82 FPGA-DS-02012-2.1
Data Sheet
3.31. sysCONFIG Port Timing Specifications

Table 3.42. ECP5/ECP5-5G sysCONFIG Port Timing Specifications
POR, Configuration Initialization, and Wakeup
Time from the Application of VCC, VCCAUX or VCCIO8
tICFG — — 33 ms
(whichever is the last) to the rising edge of INITN
tVMC Time from tICFG to the valid Master CCLK — — 5 us
tCZ CCLK from Active to High-Z — — 300 ns
Master CCLK
All selected
fMCLK Frequency –20 20 %
frequencies
All selected
tMCLK-DC Duty Cycle 40 60 %
frequencies
All Configuration Modes
tPRGM PROGRAMN LOW pulse accepted — 110 — ns
tPRGMRJ PROGRAMN LOW pulse rejected — — 50 ns
tINITL INITN LOW time — — 55 ns
tDPPINT PROGRAMN LOW to INITN LOW — — 70 ns
tDPPDONE PROGRAMN LOW to DONE LOW — — 80 ns
tIODISS PROGRAMN LOW to I/O Disabled — — 150 ns
Slave SPI
fCCLK CCLK input clock frequency — — 60 MHz
tCCLKH CCLK input clock pulsewidth HIGH — 6 — ns
tCCLKL CCLK input clock pulsewidth LOW — 6 — ns
tSTSU CCLK setup time — 1 — ns
tSTH CCLK hold time — 1 — ns
tSTCO CCLK falling edge to valid output — — 10 ns
tSTOZ CCLK falling edge to valid disable — — 10 ns
tSTOV CCLK falling edge to valid enable — — 10 ns
tSCS Chip Select HIGH time — 25 — ns
tSCSS Chip Select setup time — 3 — ns
tSCSH Chip Select hold time — 3 — ns
Master SPI
fCCLK Max selected CCLK output frequency — — 62 MHz
tCCLKH CCLK output clock pulse width HIGH — 3.5 — ns
tCCLKL CCLK output clock pulse width LOW — 3.5 — ns
tSTSU CCLK setup time — 5 — ns
tSTH CCLK hold time — 1 — ns
tCSSPI INITN HIGH to Chip Select LOW — 100 200 ns
tCFGX INITN HIGH to first CCLK edge — — 150 ns
Slave Serial
tSSCH CCLK input clock pulse width HIGH — 5 — ns
tSSCL CCLK input clock pulse width LOW — 5 — ns
tSUSCDI CCLK setup time — 0.5 — ns
tHSCDI CCLK hold time — 1.5 — ns
FPGA-DS-02012-2.1 83
Data Sheet
Table 3.42. ECP5/ECP5-5G sysCONFIG Port Timing Specifications

Slave Parallel
tBSCH CCLK input clock pulsewidth HIGH — 6 — ns
tBSCL CCLK input clock pulsewidth LOW — 6 — ns
tCORD CCLK to DOUT for Read Data — — 12 ns
tSUCBDI Data Setup Time to CCLK — 1.5 — ns
tHCBDI Data Hold Time to CCLK — 1.5 — ns
tSUCS CSN, CSN1 Setup Time to CCLK — 2.5 — ns
tHCS CSN, CSN1 Hold Time to CCLK — 1.5 — ns
tSUWD WRITEN Setup Time to CCLK — 45 — ns
tHCWD WRITEN Hold Time to CCLK — 2 — ns
tDCB CCLK to BUSY Delay Time — — 12 ns
t BSCYC
t BSCL
t BSCH
CCLK
t SUCS t HCS
CS1N
CSN
tSUWD t HWD
WRITEN
t DCB
BUSY
tCORD
D[0:7] Byte 0 Byte 1 Byte 2 Byte n*
*n = last byte of read cycle.
Figure 3.15. sysCONFIG Parallel Port Read Cycle
84 FPGA-DS-02012-2.1
Data Sheet
tBSCYC
tBSCL
t BSCH
CCLK*
tSUCS tHCS
CS1N
CSN
tSUWD tHWD
WRITEN
tDCB
BUSY
t SUCBDI tHCBDI
D[0:7] Byte 0 Byte 1 Byte 2 Byte n
*In Master Parallel Mode the FPGA provides CCLK (MCLK). In Slave Parallel Mode the external device provides CCLK.
Figure 3.16. sysCONFIG Parallel Port Write Cycle
tSSCL tSSCH
CCLK (input)
tHSCDI
tSUSCDI
DIN
tCODO
DOUT
Figure 3.17. sysCONFIG Slave Serial Port Timing
FPGA-DS-02012-2.1 85
Data Sheet
VCC/VCCAUX/
VCCIO8 1 tICFG
INITN
DONE
t VMC
CCLK 2
CFG[2:0]3 Valid
1. Time taken from VCC, VCCAUX or VCCIO8, whichever is the last to cross the POR trip point.
2. Device is in a Master Mode (SPI, SPIm).
3. The CFG pins are normally static (hardwired).
Figure 3.18. Power-On-Reset (POR) Timing
Wake Up Clocks
tICFG tSSCH
tVMC tSSCL
VCC
tPRGM
tPRGMRJ
CCLK
PROGRAMN
tDPPINIT
INITN
tHSCDI (tHMCDI )
tSUSCDI (tSUMCDI) tCODO
DONE
tDPPDONE
DI
GOE Release
DOUT
tIOENSS
sysI/O
tIODISS
Figure 3.19. sysCONFIG Port Timing
86 FPGA-DS-02012-2.1
Data Sheet
t PRGMRJ
PROGRAMN
INITN t DPPI NIT
DONE t DI NITD
CCLK
CFG[2:0]* Valid
t IODISS
USER I/O
*The CFG pins are normally static (hardwired).
Figure 3.20. Configuration from PROGRAMN Timing
PROGRAMN
INITN
DONE Wake-Up
tMWC
CCLK
tIOENSS
USER I/O
Figure 3.21. Wake-Up Timing
FPGA-DS-02012-2.1 87
Data Sheet
Capture CR0 Capture CFGx
VCC
PROGRAMN
DONE
INITN
CSSPIN
0 1 2 3 … 7 8 9 10 … 31 32 33 34 … 127 128
CCLK
SISPI Opcode Address
SOSPI Ignore Valid Bitstream
Figure 3.22. Master SPI Configuration Waveforms
3.32. JTAG Port Timing Specifications

Table 3.43. JTAG Port Timing Specifications
Symbol Parameter Min Max Units
fMAX TCK clock frequency — 25 MHz
tBTCPH TCK [BSCAN] clock pulse width high 20 — ns
tBTCPL TCK [BSCAN] clock pulse width low 20 — ns
tBTS TCK [BSCAN] setup time 10 — ns
tBTH TCK [BSCAN] hold time 8 — ns
tBTRF TCK [BSCAN] rise/fall time 50 — mV/ns
tBTCO TAP controller falling edge of clock to valid output — 10 ns
tBTCODIS TAP controller falling edge of clock to valid disable — 10 ns
tBTCOEN TAP controller falling edge of clock to valid enable — 10 ns
tBTCRS BSCAN test capture register setup time 8 — ns
tBTCRH BSCAN test capture register hold time 25 — ns
tBUTCO BSCAN test update register, falling edge of clock to valid output — 25 ns
tBTUODIS BSCAN test update register, falling edge of clock to valid disable — 25 ns
tBTUPOEN BSCAN test update register, falling edge of clock to valid enable — 25 ns
88 FPGA-DS-02012-2.1
Data Sheet
TMS
TDI
tBTS tBTH
tBTCPH tBTCPL tBTCP
TCK
tBTCOEN tBTCO tBTCODIS
TDO V a lid D a ta V a lid D a ta
tBTCRH
tBTCRS
Data to be
Captured Data Captured
from I/O
tBTUPOEN tBUTCO tBTUODIS

Data to be
driven out V a lid D a ta V a lid D a ta
to I/O
Figure 3.23. JTAG Port Timing Waveforms
3.33. Switching Test Conditions

Figure 3.24 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are listed in Table 3.44.
VT
R1
DUT Test Point
R2 CL*
*CL Includes Test Fixture and Probe Capacitance
Figure 3.24. Output Test Load, LVTTL and LVCMOS Standards
FPGA-DS-02012-2.1 89
Data Sheet
Table 3.44. Test Fixture Required Components, Non-Terminated Interfaces

Test Condition R1 R2 CL Timing Ref. VT
LVCMOS 3.3 = 1.5 V —
LVCMOS 2.5 = VCCIO/2 —
LVTTL and other LVCMOS settings (L ≥ H, H ≥ L)   0 pF LVCMOS 1.8 = VCCIO/2 —
LVCMOS 2.5 I/O (Z ≥ H)  1 MΩ 0 pF VCCIO/2 —
LVCMOS 2.5 I/O (Z ≥ L) 1 MΩ  0 pF VCCIO/2 VCCIO
LVCMOS 2.5 I/O (H ≥ Z)  100 0 pF VOH – 0.10 —
LVCMOS 2.5 I/O (L ≥ Z)  0 pF100 VOL + 0.10 VCCIO
Note: Output test conditions for all other interfaces are determined by the respective standards.
90 FPGA-DS-02012-2.1
Data Sheet
4. Pinout Information
4.1. Signal Descriptions

Signal Name I/O Description
General Purpose
[L/R] indicates the L (Left), or R (Right) edge of the device. [Group Number]
indicates the PIO [A/B/C/D] group.
[A/B/C/D] indicates the PIO within the PIC to which the pad is connected.
Some of these user-programmable pins are shared with special function pins.
These pins, when not used as special purpose pins, can be programmed as I/O
for user logic. During configuration the user-programmable I/O are tristated with
an internal pull-down resistor enabled. If any pin is not used (or not bonded to a
P[L/R] [Group Number]_[A/B/C/D] I/O
package pin), it is tristated and default to have pull-down enabled after
configuration.
PIO A and B are grouped as a pair, and PIO C and D are group as a pair. Each pair
supports true LVDS differential input buffer. Only PIO A and B pair supports true
LVDS differential output buffer.
Each A/B and C/D pair supports programmable on/off differential input
termination of 100 Ω.
[T/B] indicates the T (top) or B (bottom) edge of the device. [Group Number]
indicates the PIO [A/B] group.
[A/B] indicates the PIO within the PIC to which the pad is connected. Some of
these user-programmable pins are shared with sysConfig pins. These pins, when
not used as configuration pins, can be programmed as I/O for user logic. During
P[T/B][Group Number]_[A/B] I/O configuration, the pins not used in configuration are tristated with an internal
pull-down resistor enabled. If any pin is not used (or not bonded to a package
pin), it is tristated and default to have pull-down enabled after configuration.
PIOs on top and bottom do not support differential input signaling or true LVDS
output signaling, but it can support emulated differential output buffer.
PIO A/B forms a pair of emulated differential output buffer.
GSRN I Global RESET signal (active low). Any I/O pin can be GSRN.
NC — No connect.
RESERVED — This pin is reserved and should not be connected to anything on the board.
GND — Ground. Dedicated pins.
Power supply pins for core logic. Dedicated pins. VCC = 1.1 V (ECP5), 1.2 V
VCC —
(ECP5UM5G)
Auxiliary power supply pin. This dedicated pin powers all the differential and
VCCAUX —
referenced input buffers. VCCAUX = 2.5 V.
Dedicated power supply pins for I/O bank x. VCCIO8 is used for configuration and
VCCIOx —
JTAG.
Reference supply pins for I/O bank x. Pre-determined shared pin in each bank
VREF1_x —
are assigned as VREF1 input. When not used, they may be used as I/O pins.
PLL, DLL and Clock Functions
General Purpose PLL (GPLL) input pads: [LOC] = ULC, LLC, URC and LRC, T = true
[LOC][_GPLL[T, C]_IN I and C = complement. These pins are shared I/O pins. When not configured as
GPLL input pads, they can be used as general purpose I/O pins.
General Routing Signals in Banks 0, 1, 2, 3, 4, 6 and 7. There are two in each bank
([num] = 0, 1). Refer to ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage
GR_PCLK[Bank][num] I
Guide (TN1263). These pins are shared I/O pins. When not configured as GR pins,
they can be used as general purpose I/O pins.
General Purpose Primary CLK pads: [T/C] = True/Complement, [Bank] = (0, 1, 2,
PCLK[T/C][Bank]_[num] I/O 3, 6 and 7). There are two in each bank ([num] = 0, 1). These are shared I/ O pins.
When not configured as PCLK pins, they can be used as general purpose I/O pins.
FPGA-DS-02012-2.1 91
Data Sheet

PLL, DLL and Clock Functions
DQS input/output pads: T (top), R (right), group_ num = ball number associated
[L/R]DQS[group_num] I/O
with DQS[T] pin.
DQ input/output pads: T (top), R (right), group_ num = ball number associated
[T/R]]DQ[group_num] I/O
with DQS[T] pin.
Test and Programming (Dedicated Pins)
Test Mode Select input, used to control the 1149.1 state machine. Pull-up is
TMS I
enabled during configuration. This is a dedicated input pin.
Test Clock input pin, used to clock the 1149.1 state machine. No pull-up enabled.
TCK I
This is a dedicated input pin.
Test Data in pin. Used to load data into device using 1149.1 state machine. After
power-up, this TAP port can be activated for configuration by sending
TDI I appropriate command. (Note: once a configuration port is selected it is locked.
Another configuration port cannot be selected until the power-up sequence).
Pull-up is enabled during configuration. This is a dedicated input pin.
Output pin. Test Data Out pin used to shift data out of a device using 1149.1.
TDO O
This is a dedicated output pin.
Configuration Pads (Used during sysCONFIG)
Mode pins used to specify configuration mode values latched on rising edge of
CFG[2:0] I INITN. During configuration, a pull-up is enabled.
These are dedicated pins.
Open Drain pin. Indicates the FPGA is ready to be configured. During
INITN I/O configuration, a pull-up is enabled.
This is a dedicated pin.
Initiates configuration sequence when asserted low. This pin always has an
PROGRAMN I active pull-up.
Open Drain pin. Indicates that the configuration sequence is complete, and the
DONE I/O startup sequence is in progress.
Input Configuration Clock for configuring an FPGA in Slave SPI, Serial, and CPU
modes. Output Configuration Clock for configuring an FPGA in Master
CCLK I/O
configuration modes (Master SPI, Master Serial).
Parallel configuration mode busy indicator. SPI/SPIm mode data output.
HOLDN/DI/BUSY/CSSPIN/CEN I/O This is a shared I/O pin. This is a shared I/O pin. When not in configuration, it can
be used as general purpose I/O pin.
Parallel configuration mode active-low chip select. Slave SPI chip select. This is a
CSN/SN I/O shared I/O pin. When not in configuration, it can be used as general purpose I/O
pin.
Parallel configuration mode active-low chip select.
CS1N I This is a shared I/O pin. When not in configuration, it can be used as general
purpose I/O pin.
Write enable for parallel configuration modes.
WRITEN I This is a shared I/O pin. When not in configuration, it can be used as general
purpose I/O pin.
Serial data output. Chip select output. SPI/SPIm mode chip select. This is a
DOUT/CSON O
shared I/O pin. When not in configuration, it can be used as general purpose I/O
pin.
Parallel configuration I/O. Open drain during configuration. When in SPI modes,
it is an output in Master mode, and input in Slave mode.
D0/MOSI/IO0 I/O
This is a shared I/O pin. When not in configuration, it can be used as general
purpose I/O pin.
92 FPGA-DS-02012-2.1
Data Sheet

Configuration Pads (Used during sysCONFIG)
Parallel configuration I/O. Open drain during configuration. When in SPI
modes, it is an input in Master mode, and output in Slave mode.
D1/MISO/IO1 I/O
purpose I/O pin.
D2/IO2 I/O
purpose I/O pin.
D3/IO3 I/O
purpose I/O pin.
Parallel configuration I/O. Open drain during configuration. This is a shared
D4/IO4 I/O I/O pin. When not in configuration, it can be used as general purpose I/O
pin.
pin.

pin.
Parallel configuration I/O. Open drain during configuration.

D7/IO7 I/O This is a shared I/O pin. When not in configuration, it can be used as general
purpose I/O pin
SERDES Function
SERDES, transmit, receive, PLL and reference clock buffer power supply for
SERDES Dual x. All VCCA supply pins must always be powered to the
VCCAx —
recommended operating voltage range. If no SERDES channels are used,
connect VCCA to VCC. VCCAx = 1.1 V for ECP5, VCCAx = 1.2 V for ECP5-5G.
VCCAUXAx — SERDES Aux Power Supply pin for SERDES Dual x. VCCAUXAx = 2.5 V.
High-speed SERDES inputs, P = Positive, N = Negative, dual_num = [0, 1],
HDRX[P/N]_D[dual_num]CH[chan_num] I
chan_num = [0, 1]. These are dedicated SERDES input pins.
High-speed SERDES outputs, P = Positive, N = Negative, dual_num = [0, 1],
HDTX[P/N]_D[dual_num]CH[chan_num] O
chan_num = [0, 1]. These are dedicated SERDES output pins.
SERDES Reference Clock inputs, P = Positive, N = Negative, dual_num = [0, 1].
REFCLK[P/N]_D[dual_num] I
These are dedicated SERDES input pins.
SERDES High-Speed Inputs Termination Voltage Supplies, dual_num = [0, 1],
VCCHRX_D[dual_num]CH[chan_num] — chan_num = [0, 1]. These pins should be powered to 1.1 V on ECP5, or
1.2 V on ECP5-5G.
SERDES High-Speed Outputs Buffer Voltage Supplies, dual_num = [0, 1],
VCCHTX_D[dual_num]CH[chan_num] — chan_num = [0, 1]. These pins should be powered to 1.1 V on ECP5, or 1.2 V
on ECP5-5G.
Notes:
 When placing switching I/O around these critical pins that are designed to supply the device with the proper reference or
supply voltage, care must be given.
 These pins are dedicated inputs or can be used as general purpose I/O.
FPGA-DS-02012-2.1 93
Data Sheet
4.2. PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin
PICs Associated with DQS Strobe PIO within PIC DDR Strobe (DQS) and Data (DQ) Pins
For Left and Right Edges of the Device Only
A DQ
B DQ
P[L/R] [n−6]
C DQ
D DQ
A DQ
B DQ
P[L/R] [n−3]
C DQ
D DQ
A DQS (P)
B DQS (N)
P[L/R] [n]
C DQ
D DQ
A DQ
B DQ
P[L/R] [n+3]
C DQ
D DQ
Note: n is a row PIC number.
4.3. Pin Information Summary

4.3.1. LFE5UM/LFE5UM5G
LFE5UM/
Pin Information Summary LFE5UM/LFE5UM5G-45 LFE5UM/LFE5UM5G-85
LFE5UM5G-25
285 381 285 381 554 285 381 554 756
Pin Type csfBGA
csfBGA caBGA caBG caBGA csfBGA caBG caBGA caBGA
Bank 0 6 24 6 A
27 32 6 A
27 32 56
Bank 1 6 32 6 33 40 6 33 40 48
Bank 2 21 32 21 32 32 21 34 32 48
General Purpose Bank 3 28 32 28 33 48 28 33 48 64
Inputs/Outputs per Bank Bank 4 0 0 0 0 0 0 0 14 24
Bank 6 26 32 26 33 48 26 33 48 64
Bank 7 18 32 18 32 32 18 32 32 48
Bank 8 13 13 13 13 13 13 13 13 13
Total Single-Ended User I/O 118 197 118 203 245 118 205 259 365
VCC 13 20 13 20 24 13 20 24 36
VCCAUX (Core) 3 4 3 4 9 3 4 9 8
Bank 0 1 2 1 2 3 1 2 3 4
Bank 1 1 2 1 2 3 1 2 3 4
Bank 2 2 3 2 3 4 2 3 4 4
Bank 3 2 3 2 3 3 2 3 3 4
VCCIO
Bank 4 0 0 0 0 0 0 0 2 2
Bank 6 2 3 2 3 4 2 3 4 4
Bank 7 2 3 2 3 3 2 3 3 4
Bank 8 2 2 2 2 2 2 2 2 2
94 FPGA-DS-02012-2.1
Data Sheet
LFE5UM/
Pin Information Summary LFE5UM/LFE5UM5G-45 LFE5UM/LFE5UM5G-85
LFE5UM5G-25
285 381 285 381 554 285 381 554 756
Pin Type csfBGA
csfBGA caBGA caBG caBGA csfBGA caBG caBGA caBGA
TAP 4 4 4 A
4 4 4 A
4 4 4
Miscellaneous Dedicated Pins 7 7 7 7 7 7 7 7 7
GND 83 59 83 59 113 83 59 113 166
NC 1 8 1 2 33 1 0 17 29
Reserved 0 2 0 2 4 0 2 4 4
SERDES 14 28 14 28 28 14 28 28 28
VCCA0 2 2 2 2 6 2 2 6 8
VCCA (SERDES)
VCCA1 0 2 0 2 6 0 2 6 9
VCCAU 2 2 2 2 2 2 2 2 2
VCCAUX (SERDES) XA0
VCCAU 0 2 0 2 2 0 2 2 2
GNDA (SERDES) XA1 26 26 26 26 49 26 26 49 60
Total Balls 285 381 285 381 554 285 381 554 756
Bank 0 0 0 0 0 0 0 0 0 0
Bank 1 0 0 0 0 0 0 0 0 0
Bank 2 10/8 16/8 10/8 16/8 16/8 10/8 17/9 16/8 24/12
High Speed Differential Input Bank 3 14/7 16/8 14/7 16/8 24/12 14/7 16/8 24/12 32/16
/ Output Pairs Bank 4 0 0 0 0 0 0 0 0 0
Bank 6 13/6 16/8 13/6 16/8 24/12 13/6 16/8 24/12 32/16
Bank 7 8/6 16/8 8/6 16/8 16/8 8/6 16/8 16/8 24/12
Bank 8 0 0 0 0 0 0 0 0 0
Total High Speed Differential I/O Pairs 45/27 64/32 45/27 64/32 80/40 45/27 65/33 80/40 112/56
Bank 0 0 0 0 0 0 0 0 0 0
Bank 1 0 0 0 0 0 0 0 0 0
DQS Groups Bank 2 1 2 1 2 2 1 2 2 3

(> 11 pins in group) Bank 3 2 2 2 2 3 2 2 3 4
Bank 4 0 0 0 0 0 0 0 0 0
Bank 6 2 2 2 2 3 2 2 3 4
Bank 7 1 2 1 2 2 1 2 2 3
Bank 8 0 0 0 0 0 0 0 0 0
Total DQS Groups 6 8 6 8 10 6 8 10 14
FPGA-DS-02012-2.1 95
Data Sheet
4.3.2. LFE5U
Pin Information Summary LFE5U-12 LFE5U-25 LFE5U-45 LFE5U-85
256 285 381 256 285 381 256 285 381 554 285 381 554 756
Pin Type
caBGA csfBGA caBGA caBGA csfBGA caBGA caBGA csfBGA caBGA caBGA csfBGA caBGA caBGA caBGA
Bank 0 24 6 24 24 6 24 24 6 27 32 6 27 32 56
Bank 1 32 6 32 32 6 32 32 6 33 40 6 33 40 48
Bank 2 32 21 32 32 21 32 32 21 32 32 21 34 32 48
General Purpose Bank 3 32 28 32 32 28 32 32 28 33 48 28 33 48 64
Inputs/Outputs
per Bank Bank 4 0 0 0 0 0 0 0 0 0 0 0 0 14 24
Bank 6 32 26 32 32 26 32 32 26 33 48 26 33 48 64
Bank 7 32 18 32 32 18 32 32 18 32 32 18 32 32 48
Bank 8 13 13 13 13 13 13 13 13 13 13 13 13 13 13
Total Single-Ended User I/O 197 118 197 197 118 197 197 118 203 245 118 205 259 365
VCC 6 13 20 6 13 20 6 13 20 24 13 20 24 36
VCCAUX (Core) 2 3 4 2 3 4 2 3 4 9 3 4 9 8
Bank 0 2 1 2 2 1 2 2 1 2 3 1 2 3 4
Bank 1 2 1 2 2 1 2 2 1 2 3 1 2 3 4
Bank 2 2 2 3 2 2 3 2 2 3 4 2 3 4 4
Bank 3 2 2 3 2 2 3 2 2 3 3 2 3 3 4
VCCIO
Bank 4 0 0 0 0 0 0 0 0 0 0 0 0 2 2
Bank 6 2 2 3 2 2 3 2 2 3 4 2 3 4 4
Bank 7 2 2 3 2 2 3 2 2 3 3 2 3 3 4
Bank 8 1 2 2 1 2 2 1 2 2 2 2 2 2 2
TAP 4 4 4 4 4 4 4 4 4 4 4 4 4 4
Miscellaneous Dedicated Pins 7 7 7 7 7 7 7 7 7 7 7 7 7 7
GND 27 123 99 27 123 99 27 123 99 198 123 99 198 267
NC 0 1 26 0 1 26 0 1 26 33 1 26 33 29
Reserved 0 4 6 0 4 6 0 4 6 12 4 6 12 12
Total Balls 256 285 381 256 285 381 256 285 381 554 285 381 554 756
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bank 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bank 2 16/8 10/8 16/8 16/8 10/8 16/8 16/8 10/8 16/8 16/8 10/8 17/9 16/8 24/1
High Speed Bank 3 16/8 14/7 16/8 16/8 14/7 16/8 16/8 14/7 16/8 24/12 14/7 16/8 24/12 32/1
Differential Input
/Output Pairs Bank 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bank 6 16/8 13/6 16/8 16/8 13/6 16/8 16/8 13/6 16/8 24/12 13/6 16/8 24/12 32/1
Bank 7 16/8 8/6 16/8 16/8 8/6 16/8 16/8 8/6 16/8 16/8 8/6 16/8 16/8 24/1
Bank 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Total High Speed Differential 64/32 45/27 64/32 64/32 45/27 64/32 64/32 45/27 64/32 80/40 45/27 65/33 80/40 112/56
I/O Pairs
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bank 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bank 2 2 1 2 2 1 2 2 1 2 2 1 2 2 3
DQS Groups (> 11 Bank 3 2 2 2 2 2 2 2 2 2 3 2 2 3 4
pins in group) Bank 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bank 6 2 2 2 2 2 2 2 2 2 3 2 2 3 4
Bank 7 2 1 2 2 1 2 2 1 2 2 1 2 2 3
Bank 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Total DQS Groups 8 6 8 8 6 8 8 6 8 10 6 8 10 14
96 FPGA-DS-02012-2.1
Data Sheet
5. Ordering Information
5.1. ECP5/ECP5-5G Part Number Description
LFE5U - XX - X XXXXX X
Device Family Grade
LFE5U (ECP5 FPGA) C = Commercial
I = Industrial
Logic Capacity
12F = 12K LUTs Package
25F = 25K LUTs BG256 = 256-ball caBGA
45F = 45K LUTs MG285 = 285-ball csfBGA
Speed BG554 = 554-ball caBGA
6 = Slowest BG756 = 756-ball caBGA
7
8 = Fastest
LFE5UM - XX - X XXXXX X
Device Family Grade
LFE5UM (ECP5 FPGA C = Commercial
with SERDES) I = Industrial
Logic Capacity
BG554 = 554-ball caBGA
6 = Slowest
7
8 = Fastest
FPGA-DS-02012-2.1 97
Data Sheet
LFE5UM5G - XX - X XXXXX X
Device Family Grade
LFE5UM5G (ECP5-5G FPGA C = Commercial
with SERDES) I = Industrial
Logic Capacity
BG554 = 554-ball caBGA
8 = Fastest
5.2. Ordering Part Numbers

5.2.1. Commercial
Part number Grade Package Pins Temp. LUTs (K) SERDES
LFE5U-12F-6BG256C –6 Lead free caBGA 256 Commercial 12 No
LFE5U-12F-6MG285C –6 Lead free csfBGA 285 Commercial 12 No
98 FPGA-DS-02012-2.1
Data Sheet

LFE5UM-25F-6MG285C –6 Lead free csfBGA 285 Commercial 24 Yes
LFE5UM-25F-6BG381C –6 Lead free caBGA 381 Commercial 24 Yes
LFE5UM5G-25F-8MG285C –8 Lead free csfBGA 285 Commercial 24 Yes
LFE5UM5G-25F-8BG381C –8 Lead free caBGA 381 Commercial 24 Yes
FPGA-DS-02012-2.1 99
Data Sheet

5.2.2. Industrial
LFE5U-12F-6BG256I –6 Lead free caBGA 256 Industrial 12 No
LFE5U-12F-6MG285I –6 Lead free csfBGA 285 Industrial 12 No
100 FPGA-DS-02012-2.1
Data Sheet

LFE5UM-25F-6MG285I –6 Lead free csfBGA 285 Industrial 24 Yes
LFE5UM-25F-6BG381I –6 Lead free caBGA 381 Industrial 24 Yes
LFE5UM5G-25F-8MG285I –8 Lead free csfBGA 285 Industrial 24 Yes
LFE5UM5G-25F-8BG381I –8 Lead free caBGA 381 Industrial 24 Yes
FPGA-DS-02012-2.1 101
Data Sheet
Supplemental Information
For Further Information

A variety of technical notes for the ECP5/ECP5-5G family are available.
 High-Speed PCB Design Considerations (TN1033)
 Transmission of High-Speed Serial Signals Over Common Cable Media (TN1066)
 PCB Layout Recommendations for BGA Packages (FPGA-TN-02024)
 Minimizing System Interruption During Configuration Using TransFR Technology (TN1087)
 Electrical Recommendations for Lattice SERDES (FPGA-TN-02077)
 LatticeECP3, ECP5 and ECP5-5G Soft Error Detection (SED)/Correction (SEC) Usage Guide (TN1184)
 Using TraceID (TN1207)
 Sub-LVDS Signaling Using Lattice Devices (TN1210)
 Advanced Security Encryption Key Programming Guide for ECP5, ECP5-5G, LatticeECP3, and LatticeECP2/MS
Devices (TN1215)
 LatticeECP3, LatticeECP2/M, ECP5 and ECP5-5G Dual Boot and Multiple Boot Feature (TN1216)
 ECP5 and ECP5-5G sysCONFIG Usage Guide (FPGA-TN-02039)
 ECP5 and ECP5-5G SERDES/PCS Usage Guide (TN1261)
 ECP5 and ECP5-5G sysI/O Usage Guide (FPGA-TN-02032)
 ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide (TN1263)
 ECP5 and ECP5-5G Memory Usage Guide (TN1264)
 ECP5 and ECP5-5G High-Speed I/O Interface (FPGA-TN-02035)
 Power Consumption and Management for ECP5 and ECP5-5G Devices (TN1266)
 ECP5 and ECP5-5G sysDSP Usage Guide (TN1267)
 ECP5 and ECP5-5G Hardware Checklist (FPGA-TN-02038)
 Solder Reflow Guide for Surface Mount Devices (FPGA-TN-02041)
 ECP5 and ECP5-5G PCI Express Soft IP Ease of Use Guidelines (FPGA-TN-02045)
 Programming External SPI Flash through JTAG for ECP5/ECP5-5G (FPGA-TN-02050)
 Adding Scalable Power and Thermal Management to ECP5 Using L-ASC10 (AN6095)
 MIPI D-PHY Bandwidth Matrix and Implementation (FPGA-TN-02090)
For further information on interface standards, refer to the following websites:
 JEDEC Standards (LVTTL, LVCMOS, SSTL): www.jedec.org
 PCI: www.pcisig.com
102 FPGA-DS-02012-2.1
Data Sheet
Revision History
Revision 2.1, April 2019
Section Change Summary
General Description In the Features section, changed feature to subLVDS and SLVS, SoftIP MIPI D-PHY
receiver/transmitter interfaces under Programmable sysI/O™ Buffer Supports Wide Range of
Interfaces.
Architecture Updated the Supported sysI/O Standards section.
DC and Switching Characteristics  Updated Table 3.11. sysI/O Recommended Operating Conditions.
Added/revised standards and values.
Corrected typo from LVCOM to LVCMOS.
 Updated Table 3.12. Single-Ended DC Characteristics.
Corrected typo from LVCOM to LVCMOS.
Pinout Information  Updated Configuration Pads (Used during sysCONFIG) in Signal Descriptions table.
 Removed note 3.
Supplemental Information  Updated document numbers of:
 PCB Layout Recommendations for BGA Packages to FPGA-TN-02024
 ECP5 and ECP5-5G sysI/O Usage Guide to FPGA-TN-02032
 ECP5 and ECP5-5G High-Speed I/O Interface to FPGA-TN-02035
 Added MIPI D-PHY Bandwidth Matrix and Implementation Technical Note.
All Minor editorial changes.

Pin Information Summary Adjusted tables in the LFE5UM/LFE5UM5G and the LFE5U sections.
Supplemental Information Updated document number of ECP5 and ECP5-5G sysCONFIG Usage Guide to FPGA-TN-
02039.
Revision 1.9, March 2018

All Updated formatting and page referencing.
General Description Updated Table 1.1. ECP5 and ECP5-5G Family Selection Guide. Added caBGA256 package in
LFE5U-45.
Architecture Added a row for SGMII in Table 2.13. LFE5UM/LFE5UM5G SERDES Standard Support.
Updated footnote #1.
DC and Switching Characteristics  Updated Table 3.2. Recommended Operating Conditions.
 Added 2 rows and updated values in Table 3.7. DC Electrical Characteristics.
 Updated Table 3.8. ECP5/ECP5-5G Supply Current (Standby).
 Updated Table 3.11. sysI/O Recommended Operating Conditions.
 Updated Table 3.12. Single-Ended DC Characteristics.
 Updated Table 3.13. LVDS.
 Updated Table 3.14. LVDS25E DC Conditions.
 Updated Table 3.21. ECP5/ECP5-5G Maximum I/O Buffer Speed.
 Updated Table 3.28. Receiver Total Jitter Tolerance Specification.
 Updated header name of section 3.28 CPRI LV E.24/SGMII(2.5 Gbps) Electrical and
Timing Characteristics.
 Updated header name of section 3.29 Gigabit Ethernet/SGMII (1.25 Gbps)/CPRI LV E.12
Electrical and Timing Characteristics.
Pinout Information Updated table in section 4.3.2 LFE5U.
FPGA-DS-02012-2.1 103
Data Sheet

Ordering Information  Added table rows in 5.2.1 Commercial.
 Added table rows in 5.2.2 Industrial.
Supplemental Information Updated For Further Information section.
Revision 1.8, November 2017

General Description Updated Table 1.1. ECP5 and ECP5-5G Family Selection Guide. Added caBGA256 package in
LFE5U-12 and LFE5U-25.

All Changed document number from DS1044 to FPGA-DS-02012.
General Description Updated Features section. Changed 1.1 V core power supply to 1.1 V core power supply for
ECP5, 1.2 V core power supply for ECP5UM5G.
Architecture Updated Overview section.
Change The ECP5/ECP5-5G devices use 1.1 V as their core voltage to The ECP5 devices use 1.1
V, ECP5UM5G devices use 1.2 V as their core voltage.
DC and Switching Characteristics  Updated Table 3.2. Recommended Operating Conditions.
 Added ECP5-5G on VCC to be 1.2V +/- 5%.
 Added ECP5-5G on VCCA to be 1.2V +/- 3%.
 Updated Table 3.8. ECP5/ECP5-5G Supply Current (Standby).
 Changed Core Power Supply Current for ICC on LFE5UM5G devices.
 Changed SERDES Power Supply Current (Per Dual) for ICCA on LFE5UM5G devices.
 Updated Table 3.20. Register-to-Register Performance.
 Remove (DDR/SDR) from DSP Function.
 Changed DSP functions to 225 MHz.
Pinout Information Update Section 4.1 Signal Description. Revised Vcc Description to Power supply pins for core
logic. Dedicated pins. VCC = 1.1 V (ECP5), 1.2 V (ECP5UM5G).
104 FPGA-DS-02012-2.1
Data Sheet
Revision 1.6, February 2016

All Changed document status from Preliminary to Final.
General Description  Updated Features section. Changed 24K to 84K LUTs to 12K to 84K LUTs.
 Added LFE5U-12 column to Table 1.1. ECP5 and ECP5-5G Family Selection Guide.
DC and Switching Characteristics  Updated Power up Sequence section.
 Identified typical ICC current for specific devices in Table 3.8. ECP5/ECP5-5G Supply
Current (Standby).
 Updated values in Table 3.9. ECP5.
 Updated values in Table 3.10. ECP5-5G.
 Added values to –8 Timing column of Table 3.19. Pin-to-Pin Performance.
 Added values to –8 Timing column of Table 3.20. Register-to-Register Performance.
 Changed LFE5-45 to All Devices in Table 3.22. ECP5/ECP5-5G External Switching
Characteristics.
 Added table notes to Table 3.31. PCIe (5 Gb/s).
 Added table note to Table 3.32. CPRI LV2 E.48 Electrical and Timing Characteristics.
 Added values to Max column of Table 3.39. Transmit.
Pinout Information Added LFE5U-12 column to the table in LFE5U section.
Ordering Information Updated LFE5U in ECP5/ECP5-5G Part Number Description section: added 12 F = 12K LUTs to
Logic Capacity.
Added LFE5U-12F information to Ordering Part Numbers section.

All  Added ECP5-5G device family.
 Changed document title to ECP5 and ECP5-5G Family Data Sheet.

General Description Updated Features section. Added support for eDP in RDR and HDR.
Architecture  Updated Overview section.
 Revised Figure 2.1. Simplified Block Diagram, LFE5UM/LFE5UM5G-85 Device (Top
Level). Modified Flexible sysI/O description and Note.
 Updated SERDES and Physical Coding Sublayer section.
 Changed E.24.V in CPRI protocol to E.24.LV.
 Removed 1.1 V from paragraph on unused Dual.
DC and Switching Characteristics  Updated Hot Socketing Requirements section. Revised VCCHTX in table notes 1 and 3.
Indicated VCCHTX in table note 4.
 Updated SERDES High-Speed Data Transmitter section. Revised VCCHTX in table note 1.
Ordering Information Updated ECP5/ECP5-5G Part Number Description section. Changed LFE5 FPGA under Device
Family to ECP5 FPGA.
FPGA-DS-02012-2.1 105
Data Sheet
Revision 1.3, August 2015

General Description Updated Features section.
 Removed SMPTE3G under Embedded SERDES.
 Added Single Event Upset (SEU) Mitigation Support.
 Removed SMPTE protocol in fifth paragraph.
Architecture General update.
DC and Switching Characteristics General update.
Pinout Information Updated Signal Descriptions section. Revised the descriptions of the following signals:
 P[L/R] [Group Number]_[A/B/C/D]
 P[T/B][Group Number]_[A/B]
 D4/IO4 (Previously named D4/MOSI2/IO4)
 D5/IO5 (Previously named D5/MISO/IO5)
 VCCHRX_D[dual_num]CH[chan_num]
VCCHTX_D[dual_num]CH[chan_num]
Supplemental Information Added TN1184 reference.
106 FPGA-DS-02012-2.1
Data Sheet
Revision 1.2, August 2014

All Changed document status from Advance to Preliminary.
General Description  Updated Features section.
 Deleted Serial Rapid I/O protocol under Embedded SERDES.
 Corrected data rate under Pre-Engineered Source Synchronous I/O.
 Changed DD3. LPDDR3 to DDR2/3, LPDDR2/3.
 Mentioned transmit de-emphasis pre- and post-cursors.
Architecture  Updated Overview section.
 Revised description of PFU blocks.
 Specified SRAM cell settings in describing the control of SERDES/PCS duals.
 Updated SERDES and Physical Coding Sublayer section.
 Changed PCI Express 2.0 to PCI Express Gen1 and Gen2.
 Deleted Serial RapidIO protocol.
 Updated Table 2.13. LFE5UM/LFE5UM5G SERDES Standard Support.
 Updated Table 2.15. LFE5UM/LFE5UM5G Mixed Protocol Support.
 Updated On-Chip Oscillator section.
 Deleted 130 MHz ±15% CMOS oscillator.
 Updated Table 2.16. Selectable Master Clock (MCLK) Frequencies during
Configuration (Nominal)
DC and Switching Characteristics  Updated Absolute Maximum Ratings section. Added supply voltages VCCA and VCCAUXA.
 Updated sysI/O Recommended Operating Conditions section. Revised HSULD12D VCCIO
values and removed table note.
 Updated sysI/O Single-Ended DC Electrical Characteristics section. Revised some values
for SSTL15 _I, SSTL15 _II, SSTL135_I, SSTL15_II, and HSUL12.
 Updated External Switching Characteristics section. Changed parameters to tSKEW_PR VCCA
and tSKEW_EDGE and added LFE5-85 as device.
 Updated ECP5 Family Timing Adders section. Added SSTL135_II buffer type data.
Removed LVCMOS33_20mA, LVCMOS25_20mA, LVCMOS25_16mA,
LVCMOS25D_16mA, and LVCMOS18_16mA buffer types. Changed buffer type to
LVCMOS12_4mA and LVCMOS12_8mA.
 Updated Maximum I/O Buffer Speed section. Revised Max values.
 Updated sysCLOCK PLL Timing section. Revised tDT Min and Max values. Revised tOPJIT
Max value. Revised number of samples in table note 1.
 Updated SERDES High-Speed Data Transmitter section. Updated Table 3.24. Serial
Output Timing and Levels and Table 3.25. Channel Output Jitter.
 In SERDES High-Speed Data Receiver section, updated Table 3.26. Serial Input Data
Specifications, Table 3.28. Receiver Total Jitter Tolerance Specification, and Table 3.29.
External Reference Clock Specification (refclkp/refclkn).
 Modified section heading to XXAUI/CPRI LV E.30 Electrical and Timing Characteristics.
Updated Table 3.33 Transmit and Table 3.34. Receive and Jitter Tolerance.
 Modified section heading to CPRI LV E.24 Electrical and Timing Characteristics. Updated
Table 3.35. Transmit and Table 3.36. Receive and Jitter Tolerance.
 Modified section heading to Gigabit Ethernet/SGMII/CPRI LV E.12 Electrical and Timing
Characteristics. Updated Table 3.37. Transmit and Table 3.38. Receive and Jitter
Tolerance.
FPGA-DS-02012-2.1 107
Data Sheet
Revision 1.1, June 2014

Ordering Information Updated ECP5/ECP5-5G Part Number Description and Ordering Part Numbers sections.
Revision 1.0, March 2014

All Initial release.
108 FPGA-DS-02012-2.1
www.latticesemi.com

FPGA DS 02012 2 1 ECP5 ECP5G Family Data Sheet

Uploaded by

Copyright:

Available Formats

You might also like

FPGA DS 02012 2 1 ECP5 ECP5G Family Data Sheet

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

FPGA DS 02012 2 1 ECP5 ECP5G Family Data Sheet

Uploaded by

Copyright:

Available Formats

ECP5 and ECP5-5G Family

2.17. IEEE 1149.1-Compliant Boundary Scan Testability ........................................................................................... 44

3.32. JTAG Port Timing Specifications ........................................................................................................................88

Table 3.36. Receive and Jitter Tolerance ............................................................................................................................ 81

Acronyms in This Document

The Lattice Diamond™ design software allows large

 sysCLOCK Analog PLLs and DLLs  Flexible Device Configuration

Figure 2.1. Simplified Block Diagram, LFE5UM/LFE5UM5G-85 Device (Top Level)

2.2. PFU Blocks

Figure 2.2. PFU Diagram

FCI From Different Slice/PFU

Figure 2.3. Slice Diagram

PFU Col(n-1) PFU Col(n) PFU Col(n+1)

Figure 2.4. Connectivity Supporting LUT5, LUT6, LUT7, and LUT8

Table 2.2. Slice Signal Descriptions

2.2.2. Modes of Operation

2.2.2.1. Logic Mode

2.2.2.2. Ripple Mode

2.2.2.3. RAM Mode

2.2.2.4. ROM Mode

2.4. Clocking Structure

2.4.1. sysCLOCK PLL

Figure 2.5. General Purpose PLL Diagram

Table 2.4 provides a description of the signals in the PLL blocks.

2.5. Clock Distribution Network

PIO PIO PIO PIO

Quadrant TL 12 Primary Sources Quadrant TR

DLL PCSCLKDIV PCSCLKDIV DLL

Figure 2.6. LFE5UM/LFE5UM5G-85 Clocking

2.5.1. Primary Clocks

2.5.1.1. Dynamic Clock Control

2.5.1.2. Dynamic Clock Select

Figure 2.7. DCS Waveforms

2.5.2. Edge Clock

Top Left / Right PCLK Pin From ECLK of

Top Right / Left PLL CLKOP

Bottom Right / Left PLL CLKOS

Bottom Left / Right PCLK Pin

Figure 2.8. Edge Clock Sources per Bank

2.6. Clock Dividers

Primary Clock Pin OR

PLL clock output CLKDIV To Primary Clock Tree

Figure 2.9. ECP5/ECP5-5G Clock Divider Sources

Figure 2.10. DDRDLL Functional Diagram

Table 2.5. DDRDLL Ports List

2.8. sysMEM Memory

2.8.1. sysMEM Memory Block

Table 2.6. sysMEM Block Configurations

2.8.2. Bus Size Matching

2.8.3. RAM Initialization and ROM Operation

2.8.4. Memory Cascading

2.8.5. Single, Dual and Pseudo-Dual Port Modes

2.8.6. Memory Core Reset

Figure 2.12. Memory Core Reset

2.9. sysDSP™ Slice

2.9.1. sysDSP Slice Approach Compared to General DSP

Operand Operand Operand

Function Implemented in ECP5/ECP5-5G