Presented by,

Narendra Kuppili,
Analog IC Layout Engineer

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 Agenda

• Introduction
• Why we need 3D Transistor?
• History and Intro to Fin FET
• Making of Fin FET
• Process challenges of Fin FET
• Future Scope
• Conclusion

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 Introduction

• Moore’s Law

• Past technology

• Present technology

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Why we need 3D Transistor?

Cross sectional view

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 Why we need 3D Transistor?

For a Good MOS Transistor :

• More ON current (ION).
To increase Performance.

• Less OFF current (IOFF).

To minimize power usage.

• More Switching speed between ON and OFF

states. Again for performance.

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 Why we need 3D Transistor?

For a Long channel MOS Transistor :

Same variation in both ON and OFF currents

Long Channel

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 Why we need 3D Transistor?

For a Short channel MOS Transistor :

Short Channel More Variation in OFF current than ON current

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 Why we need 3D Transistor?

• Gate cannot control the

leakage current paths that
are far from the gate.
• So Planar transistor loses
control of leakage, as Lg
scales downward
• Gate regains control on
thin body Semi conductor
Substrate

Any Idea
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 Why we need 3D Transistor?

Semi conductor
Substrate

• If we replace Semiconductor substrate

with Insulator, What happens?

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 Why we need 3D Transistor?

Thin Substrate

• Ultra Thin Body

Silicon On Insulator.
• No leakage through
SiO2.
• High ON current,
Lower leakage.
• Lower Vdd and Low
Power consumption.
• Low cost.

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 Why we need 3D Transistor?

• Gate wrapped on the

Thin Fin.
• Gate control the channel
from two sides.
• Double or Dual gate
Transistor.
• Fin width is a key
parameter in FinFET

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 History and Intro to Fin FET?

• Chemning Hu (Co-Inventor of
FinFET).
• Modeled a Transistor channel as A
green hose lying on a soggy lawn in 1990
IEEE interview.
• Control of channel on more than
one side will increases
performance.
2011

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History and Intro to Fin FET?

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History and Intro to Fin FET?
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 History and Intro to Fin FET?

Important Dimensions :

• W = 2Hfin+Wfin
• LG = Lg
• Multi gate devices
Electrostatics depends
on ratio of Leff/Weff
• Weff = Wsi+2(єsi/єox).Tox
• Leff = Lg-2.XUD

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 Making of Fin FET

Fin FET Fabrication

Subtractive Replacement
Fin Fin

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 Making of Fin FET

S
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F
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 Making of Fin FET

R
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F
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 Making of Fin FET

W = Anything W = n x (2*Hfin + Wfin)

Where n = no.of Fins

• Multiple widths are needed for Analog and SOC.

• We can make any width using Planar transistor.
• But when we coming to FinFET we can make width
as W = n x (2*Hfin + Wfin).

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 Making of Fin FET

• We can enable this process

for Multiple widths with
out making different height
Fins.
• For that we need to control
different oxide depths.
• This is good see in cartoon, but practically more
complex to maintain different etch packs to
remove oxide.
• If Fin is taller and thinner , it will give good
performance. Video
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 Process Challenges of Fin FET
Spacer S/D
Corner effect
Stringers Implantations

Difficult to maintain Shadowing Effect

H2 annealing SiNo3
spacers for Fin Difficult to make S/D junctions

Tapered

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 Process Challenges of Fin FET
Theoretical Practical

Challenge Theoretical Practical

Electrostatics Pass Fail
Mobility Pass Fail
Corner Effect Fail Pass
Implants Fail Pass

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Future Scope

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 Future Scope
• Intel Trigate transistor {22nm}.
• Made with 50% power reduction at constant performance.
• And 37% performance increase at low voltage.
• New transistor design after 5 decades of Intel history.
• Intel 3rd generation Microprocessors made up of Trigate
transistors.

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 Conclusion

• We cannot move forward to <32nm using Traditional

Planar transistor.
• Fin FET is a radical change in transistor design over 5
Decades.
• This will make More than 50% power reduction at
constant performance.
• Improved performance and Energy efficiency.
• Enables a new generation computing technology
from Fastest super computers to smallest Hand held
devices.

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