DLD

Lab Assignment-04

Name Misbah Batool

Registration
number 026

Class EEE-2
Instructor’s
Name Nayab Gogosh
Post Lab Module (Gate Lavel):

module lab04(F,x,y,z);

output F;

input x,y,z;

wire w1,w2,w3,w4;

and G1(w1,x,y,z);

not G2(w2,x);

not G3(w3,y);

and G4(w4,x,w3,z);

or G5(F,w1,w2,w4);

endmodule
Post-Lab Test Bench (Gate level and Data Flow):
module TB_lab04;

// Inputs

reg x;

reg y;

reg z;

// Outputs

wire F;

// Instantiate the Unit Under Test (UUT)

lab04 uut (

.F(F),
 .x(x),

.y(y),

.z(z)

);

initial begin

// Initialize Inputs

x = 0;

y = 0;

z = 0;

// Wait 100 ns for global reset to finish

#100;

x = 0;

y = 0;

z = 1;

#100;

x = 0;

y = 1;

z = 0;

#100;

x = 0;

y = 1;

z = 1;

#100;

x = 1;
 y = 0;

z = 0;

#100;

x = 1;

y = 0;

z = 1;

#100;

x = 1;

y = 1;

z = 0;

#100;

x = 1;

y = 1;

z = 1;

#100 $finish;

// Add stimulus here

end

endmodule
Post-Lab Module (Data Flow):
module PG(F,x,y,z);
output F;

input x,y,z;

assign F = (x & y & z) | ~x | (x & ~y & z);

endmodule