1.

(a) (a)
A = 11111010
1
(22),(101), (20), =
(),+ (4), 1 hence
42
4 2x4 1 3 0+ 1 3-15 2 0 Since MSB Is mber is negative
= 4 r + (r-1)x4 (00000110)

8291-[10] = 4 (00000110)
10 10 10 +4 A 6
10 =
+4 B 00001010
6 There is number 2 s Complement representaton
tor positive number B = + 10
2 (d) AxB 10x(6)
(28) = (37), 60
2xI+8x = 3 x y+ 7 x y
Binary representation of 60 = 00111 100
2 8 3y+ 7
Now take 2s complement 1 1000100
3y 2x = 1

Now check the option inoption (d) 5. (c)

=13, y =9 Sincein 1scomplete every bits get compiemer-
3 9 2x 13 1
so, no such number exist whose complemer
27 26 - 1
same while in 2's complement 8 and 0 aree

(d) 6 (a)
n bits binary number require d-decimal digits:
Decimal number 3.248x 104
So. 10 2 So sign bit should be 0 since number is pos
Take log both side
3.248x 104 = 32480
log 10> log,2" =111111011100000
d nlog2 =111111011100000x 2
 Digital Logi Advance tevel 243
eg resernting tvay

00111101X101
katna t regoreserMaton s as tollows

Fwpwre Martia

1001101 0011110
0100 1t01 10

atssa

12.
W sANa t

will be 4 and wll be 3

d
Number of bits needed 1 0
e011 1m 1000 000 0000 0000
0000 o000
(log 10) o g 2)
S s enent s 25
(log 2)

83bits =n
So decima value s
14 t
Smallest number stored in 8 bit 2's compiem

anthmeticis
1 00011111 000000000100 000

Sig Based Mantissa (Nomaized)

eponent 15 a
So number is will represents i, 1
So-1)2*1 2
16 a)
10.
the oper ation n
computer
AB A8C ABC. ABC)4
Sgn extension s
arithmetic of increas1ng the number ot bits ot a 4 A-CAB. Ae4
number s sign
Dinary number while preserving the
(DOsitive/negative) and value

11. d) CAe.CABS]aA
is 0 239 x2 Ce4ep)e 4
he decimal number
hexadecimal
representation
We have to find
Without normalization AA =0
Biased exponent=13 64 0 A =A
77
 Multiple

AB

A
244 tf
=

o t h s e r v e
1fhat

e
AB
s h o u l d
can
we

17. the
given
k map

be
p a r e d
than
it
take (
AB
AD D
4 s to to
T O m

f o r e e t

Aiso
a l w a y s
there
is DIC+ A)
s e l e c t e d

1s
11 4
1 C 0
ption

1 -
4 -
c o r r e c t

Hence correct
( b )is
option
(d) 1S H e n c e

Hence

e x p r e s S I o n
is
b O o l e a n

18. B)= ( 4B ) 22. the

required
F(4 Hence (ABC ABC. ABCE
f(fr y
Z) w
So
flry 2 w)
y z w

ABC

19
The output of A B
And Gate 1 ABC
And Gate 2 ABC ABC
ABC
And Gate 3 ABC
And Gate 4 ABC
1
C, O and
=
C, =
C= required option
Putting C Hence (b) is the
AB AB
We have

Correct
AaB
option
23 (c)
Hence (c) is the DE DE
DE DE DE D A DE DE
20 BC
have
BC
Constructing the table
we
BC X
BC
Y

O0 BC 1 BC

BC
 MRDE E R S Y

(d)
Digital Logic Advance Level
5.
245
=yz Fyz
26
(a)
Constructing tneK-map we have
CD
AB CD CDD CD
-Kx ,.
AB
AB ,

,
AB 12O
AB 0
Which is true
A B C Hence (d) is correct option

29
By using NOT gate output is complement of
input

30. (a)
NAND gate work as NOT If inputs are connected
0
togetherie

31. (b)
a =a tÐb

0 b =
a b
a bea
Let a = 1. b = 0
a =1 0 = 1 4
Hence the required output is
b 1 0= 1 b 1
f = ABeCODD
a = 1 1 =0 a = 0
a = 0. b = 1
27 (b) Hence the given set of instructions swaps a

Y= A® (A A)9 (A D A)e(A A) (A®A) and b.

A A= 0
Note: 32. (a)
AA =1 The S.OP and PO S are logically equivalent
because don't care are used in the same way
Y = A 090900 =A 0
0
Hence Y = A EXOR 34. (c)
output is 1 = ABC+ AD = A(BC + D)
28 (d)
35. (b)
Y 1
F = (+)(2+ w
1

D
.D D ( y )(z+w)

be
implemented
by making D
h e JK flip-flop
can
So 4 NAND gates required
J = y. K =x
 246
Multiple Choice Questions: CS
36. DE ERSS4
Buib
43. b
On when both switch S1
is
and S2
same state either off or
on
are in
A A A AA when nis even
1 with out

s2 Bulb
knowing what A contain
reuns
On 44 (d)
Off From thegiven diagram we can
see that
Off

On
A+BD D
Above truth table derives Ex
NOR Operation
37.
Boolean expression
D
Property CC = C C= 1
A (A B) A B
45. Id)
If input is 1010 it generate 1101 which is Same
ae
gray to binary code converter

Gray code

39. (a) Binary code b

(A+C)(AB AC) (A'C" +B')
(AB AC+ ABC AC) (A'C" 46. (a)
+ B')
(AB ABC +ABC +ABC)
(AB ABC) = AB A

40. c Ae B-ABB =0
ASB
AB AC+BC B

AB
AB AB AB AB
Hence (b) is the correct
option.
47 0b)
Here BC Is an redundant expression.

41. (b)
Expression A+ BC
D
Ao
A+

D -f(AB)-AB

AB
C AB AB AB AB AS we can see
clearly output must be A+5
C which can be obtained only by mak1ng=
andI = 1
So, that J+ A=1 andf= (A+B)1- A+B
Five min terms are Hence (b) is correct option.
present i1.e 5 1's in
K-map
42. (c 48. t
BeB. B® Expression for sum in half adder is
B, when nis odd number output
B only AB+ AB A9B and minimum number ot
NAND gates required for EX-OR Gate are 4
 D E ERSY

Digital Logic Advance Level 247

ev Circ 53. (b)

aoc abC abc abc

ABC ABC AB(CC) AB

aoc-abc abc abc 21 2x1 A B - AB

oac a) blac ac)

MUX MUX

bias c)- bla c) B

blasc b(aec) S4. b

To 16 bits number 1 half and 15 full address or
aC
16 full address are required
aDeC
o r wnich only 1 and 3 satisty
55. c)
ence correct option is (d) o implement 6 to 64
38 h n e decoder 93-t0-8

ine decrer are used

50
The give circuit represents the
implementation 64 output
oftour varnable function using8 1MUX here D B 3x8
as taken as the tourth /p and A. B C act as
seect lines

14

11
13 150 56. (a)
1 D0 a
0D00 a

m (389 10) b 0
Hence correct option is (a)

(a) we found that

By checking option
51 (c n bit full adder
circuit c a n f X b , =0. r,
= a

AS we know that
Then output of first MUX
is
sum. In order
to represent
e p r e s e n t (n - 1) bits
we require
addition of two 17
bits numbers
ab+bb = ab 0 = an
half adder second MUX gves
adder and 1 Which when passes to
unimum of 16 full FA
use either HA or
Note: For the
first bit we can

numbers inspire aba 0.a = aba =ab

oftwo 17
bit
Hence for
addition
task Hence (a) Is correct option
same
can
perform the
adders we
of 17 full
FA and
1 HA 57. c) 11 5

using 16 words are 0, 4 4 8

correct option Invalid code
Hence (C) is the
CD CO CD
AB
CD

$2 (d oD412 8
ABD+
ABD CD ABD+ AB 9
ABD
ABD+ ABD
CD
AB 31 715 D1
ABD+ ABD
261410

CDAD+
ADCU
-
AD AD be a'c'd'+ b ' c ' d + bcd+
acd

f = [A@DjCD-|A®DjCD Socode will

gatesS
NAND
10
required
t
 Multiple Choiee Questions:CS MADE
EUS
AD C
D A (1 C

D D Ah
ARey
A (AB BC)C

D DD ABC

D A
67. b
tathehe uiver1 Al
t oesernts lall ader dicgital cktan be realized using
multioi
bit not with EX OR, Halt or OR gates plexers
ie
tautoogy) 68. (c)
hoh hust he
NANI gale rying eachoption
(a) Given 0, y= 1,2=0and w =0
D (0) V Z= 0 1 0 = 1

() y01= 0
(1) W = 00+ 0 = 0
However given rZ+ W= 1
Therefore, option (a) is not the
solution
(b) Given= 1, y= 1,2= 0 and w = 1

D ()
()y
y Z = 1 +10 = 1
11
However given y = 0
1

Therefore, option (b) is not the solution

(c) Given = 1, y= 0, z = 1 and w = 1
60. (d)
()+y+2=1+ 0+ 1 =1I
tV ( ) () = 10 = 0
(11) 2+ W= 11+ 1 1
(Iv) y 2'W =10 +00 0
(d) Given = 1, y 0, z =0 and
=
w =0
sOP POS
(0)+V+ Z= 1 +0+0 1

() ay 10 =0
POS (y )(
(1) Z+ W = 10 +0 = 0
However given iz + W= 1
61. a
The given CKT
Theretore, option (d) is not the solution
Is ull adder where
Depresent
and t represert carry
sum
69 (a)
Number of NAND gate for tull adder = 9
63. (c
Number of NOR gate for full adder =9
The full adder adds the K" bits of
two numbersS
to the (h 1 bit (generated carry 70. (a)
64 (a) GIven size multiplexer = 64 to 1
Constructed multiplexer = 2 x1
D= AB
64x1
# mux needed at 1st level =E
2x1
G A. H = 32 at 1st level

CF= D+E 32
#mux needed at 2nd level = 16
2
 ERS
MADE
Digital Logic | Advance Level 249

at 3d level 6 8 4
Uxneeded 2 75. b)
Q/1 1/0
O/0
at last level =

catotal needed 32
1
a 11-0
16 +8 +4+2+1= 63
=
+
Here, for state
r e r n a n s in state
0output is O aid it
When input is

71.
(a)
When input is 1 output
is 1and goes to state (
For state Q,
0 is 1 outpu
When input is O output is 1, wtier input

(1) IS O
there
Q to O, when
Here state changes fron
1 1 0
(2)
In state Q. every
input
IS a 1 as input.
Complenented
computes 2s cormpiermernt
72. d) Hence, the given circuit
of the input number
answer
(b) is correct
A Hence

0
76 (d)
- (1)

1 1 0
FFO FF1
(2) Clock
D O D, Q
1
Initialstate
1 0
0
73. (a 1

1 0

1 is
The state transitions sequence

1 (1) 0011-0110

0 1 (2)
(3)
77. (c)
(4) both inputs
S-R flip flop gives invalid output when
(5) the previous output
0
1 are 1 while JK flip-flop toggle
it accepts both
when both inputs are 1. Hence
So 5-mod counter inputs 1

74. (6 78 (c for modulo N

The number of flip-flops required
D% (, Q) =

D ( ) D, =(9g) 0 0 1( counter is log,()

Clock Initially 0 1 0 (2)

0 1 (5) 79. b)
0 1 1 (3)

1 0 (6) 0 0
1st
10 0 (4) 0 2nd
0 0 1 (1)
3rd
4th
0

of the circuit
state
sequence
So 4 clock pulses are needed
correct
iherefore the

7 64
is 1,2.5. 3
 250 Multiple Choice Questions:CS MAD ERS
80. 88. c)
it input initialy are Q,0,Q = O00 Initial

So atter 1st clock puise Q,Q,Q 100 After 1 dock

Since values is ncremented so a binary up After I clock 0 1
COunter synchronous since clock provIded to all After I1 clock 0
a same time

81. td 89. d
To make flip-flop working both preset = apart = 1 J = Q =K =1
Since J = K= 0 so it does not change its state Q
.e remains in same state 0 1St
12d
82 0 3
1 4
0 5
1 6th
D, must be Q, Q Sequence will be 010101
D must be O, Q
.D, must be Q, E Q 90.
In block diagram allFF are cleared when Q, ang
Q, becomes 1 ie. it can count from 0. 1, 2, 456
So mod-7 ripple counter

83 (c 91. (a)
n-flip-flop divide the clock frequency by a factor The given circuit is a oscillating ckt and outputis
of 2
Square wave

84. (d)
3T 37 3T
Binary representation of 12 is 1 10 D
S (G
)- (g,
+4,) 92 a
= (01)-(0 1)
We can replace the positions of counters as shown
in figure.

is divisible by 3 so true
mod M mod N mod MN
85. 0b)
N stage shift register will take (n - 1) clock 93. a
time to show the output of final For nbit synchronous counter maximum possible
stage
time required for change of state will be
86 (d) tor
propagation delay of FF ie 25 nsec. but
A master J-K flip-flop consists of S-R
an
flip-flop asynchronous nx 25 nsec ie
and T-fip-fiop 4x 25 nsec =100 nsec
87. (b) 95 (a)
The condition to avoid race Flip-flops are having setup time 20 ns and hold
condition will be
TAt time is 0 ns
T= Ciock tirne At bit
=
repetition tirme. Flip-flops are positive edgeu trignered
propagation delay The input X' and clock C waveform are given
 251
n A D E E R s y

Digital Logic | Advance Level

Output wavetorm Yi.e the output o fflip-flop

identified
100. (c) 16 K byte
1., I S to be Size of memory
Chips si7e 42 byte
FFO FF1
Clock Q
DXD,-XQ its2
Initial state 0
So # chips needed 2 4 Dits

1
1 0 101. (d) device
bipolar
MOS device over
The advantage of
6 0
eftective
and cost
bit density
IS, It allows higher impedance a n c
to fabricate and have higher
easy

Clock operational speed

102. (c)

97. (b)
The retreshing
rate of dynamic RAMs is
V,o
sec.
approximately 2 m

98. (a) stored on

that are typically
The number of bits not gate
disk is usually
same Represents the
each track of a magnetic
into disk is
same.

because of storing data

density