Dataflow Modelling

1) Logic Gates
Aim: To design, and implement LOGIC GATES using Verilog HDL and verify the operation by writing a testbench.

Program:
module logicgates_data(Y1,Y2,Y3,Y4,Y5,Y6,Y7,Y8,A,B);
input A,B;
output Y1,Y2,Y3,Y5,Y4,Y6,Y7,Y8;
assign Y1=A & B;
assign Y2=A | B;
assign Y3=~(A & B);
assign Y4=~(A | B);
assign Y5=A ^ B;
assign Y6=~(A ^ B);
assign Y7=~A;
assign Y8=A;
endmodule
Testbench:
‘timescale 1ns / 1ps
module test_logicgates;
reg A; // Inputs
reg B;
wire Y1; //Outputs
wire Y2;
wire Y3;
wire Y4;
wire Y5;
wire Y6;
wire Y7;
wire Y8;
logicgates uut ( //UUT Instantiation
.A(A),
.B(B),
.Y1(Y1),
.Y2(Y2),
.Y3(Y3),
.Y4(Y4),
 .Y5(Y5),
.Y6(Y6),
.Y7(Y7),
.Y8(Y8)
);
initial //Input Stimulus
begin
#3 A= 1'b0; B = 1'b0;
#3 A = 1'b0; B = 1'b1;
#3 A = 1'b1; B = 1'b0;
#3 A = 1'b1; B = 1'b1;
#3 $stop;
end
initial
begin
$monitor ($time, "A=%b, B=%b, Y1=%b, Y2=%b, Y3=%b, Y4=%b, Y5=%b, Y6=%b, Y7=%b,
Y8=%b",A,B,Y1,Y2,Y3,Y4,Y5,Y6,Y7,Y8);
end
endmodule
Result: Logic gates(and,or,nor,nand,not,xor,xnor,buffer) has been designed using Verilog HDL and the operation is verified by
observing the timing diagram generated by the testbench.
Timing Diagram:
2) 2x4 DECODER WITH ENABLE INPUT
Aim: To design, and implement 2X4 DECODERWITH ENABLE INPUT using Verilog HDL and verify the operation by writing a
testbench.
Program:
`timescale 1ns / 1ps
module decoder2x4_data(D,I,En);
input[1:0]I;
input En;
output [3:0]D;
assign D[0]=~I[0]&~I[1]&En;
assign D[1]=I[0]&~I[1]&En;
assign D[2]=I[1]&~I[0]&En;
assign D[3]=I[1]&I[0]&En;
endmodule

Testbench:
‘timescale 1ns / 1ps
module decoder2x4_testdata;
reg [1:0]I; // Inputs
reg En;
 wire [3:0]D; // Outputs
decoder2x4_data uut ( // Instantiate the Unit Under Test (UUT)

.D(D),
.I(I),
.En(En)
);

initial begin
#2 En=0;I=2'b00;
#2 En=0;I=2'b01;
#2 En=0;I=2'b10;
#2 En=0;I=2'b11;
#2 En=1;I=2'b00;
#2 En=1;I=2'b01;
#2 En=1;I=2'b10;
#2 En=1;I=2'b11;
#2 $stop;
end
initial
 begin
$monitor ($time, "I=%b, Enable=%b, D=%b",I,En,D);
end
endmodule
Results:2x4 decoder with enable input has been designed using Verilog HDL and the operation is verified by observing the timing
diagram generated by the testbench.
Timing Diagram:
3)8x3 ENCODER
Aim: To design, and implement 8x3 encoder using Verilog HDL and verify the operation by writing a testbench.

Program:
module encoder8x3_data(A,D);
input [7:0]D;
output [2:0]A;
assign A[0]=D[1]|D[3]|D[5]|D[7];
assign A[1]=D[2]|D[3]|D[6]|D[7];
assign A[2]=D[4]|D[5]|D[6]|D[7];

endmodule
Testbench:
module test_encoder_8x3;
reg [7:0] D; // Inputs
wire [2:0] A; // Outputs
encoder_8x3 uut ( //UUT Instantiation
.A(A),
.D(D)
);
 initial //Input Stimulus
begin
#2 D=8'b00000001;
#2 D=8'b00000010;
#2 D=8'b00000100;
#2 D=8'b00001000;
#2 D=8'b00010000;
#2 D=8'b00100000;
#2 D=8'b01000000;
#2 D=8'b10000000;
#2 $stop;
end
initial
begin
$monitor ($time, "D=%b, A=%b",D,A);
end

endmodule

Results:8x3 encoder with enable input has been designed using Verilog HDL and the operation is verified by observing the timing
diagram generated by the testbench.
Timing Diagram:
4) 8x1 multiplexer
Aim: To design, and implement 8x1 multiplexer using Verilog HDL and verify the operation by writing a testbench.

Program:
`timescale 1ns / 1ps
module mux8x1_data(Y,IN,S);
input [7:0]IN;
input [2:0]S;
output Y;

assign Y=(S==3'b000)?IN:1'bz;
assign Y=(S==3'b001)?IN:1'bz;
assign Y=(S==3'b010)?IN:1'bz;
assign Y=(S==3'b011)?IN:1'bz;
assign Y=(S==3'b100)?IN:1'bz;
assign Y=(S==3'b101)?IN:1'bz;
assign Y=(S==3'b110)?IN:1'bz;
assign Y=(S==3'b111)?IN:1'bz;

endmodule
TestBench:
`timescale 1ns / 1ps
module multiplexer_testdata;

reg [7:0]IN; // Inputs

reg [2:0] S;
wire Y; // Outputs
mux8x1_data uut ( // Instantiate the Unit Under Test (UUT)

.Y(Y),
.IN(IN),
.S(S)
);

initial begin
#2 S=3'b111;IN=8'b10000000;
#2 S=3'b110;IN=8'b01000000;
#2 S=3'b101;IN=8'b00100000;
#2 S=3'b100;IN=8'b00010000;
 #2 S=3'b011;IN=8'b00001000;
#2 S=3'b010;IN=8'b00000100;
#2 S=3'b001;IN=8'b00000010;
#2 S=3'b000;IN=8'b00000001;
#2 $stop;
end
initial begin
$monitor($time ,"Y=%b,S=%b,IN=%b",Y,IN,S);
end
endmodule

Results:8x1 multiplexer using has been designed using Verilog HDL and the operation is verified by observing the timing diagram
generated by the testbench.
Timing Diagram:
5)1x8Demultiplexer:
Aim: To design, and implement 1x8 demultiplexer using Verilog HDL and verify the operation by writing a testbench.

Program:
`timescale 1ns / 1ps

module demux1x8_data(Y,v,S);
input v;
input [2:0]S;
output[7:0]Y;
assign Y[0]=v&~S[2]&~S[1]&~S[0];
assign Y[1]=v&~S[2]&~S[1]&S[0];
assign Y[2]=v&~S[2]&S[1]&~S[0];
assign Y[3]=v&~S[2]&S[1]&S[0];
assign Y[4]=v&S[2]&~S[1]&~S[0];
assign Y[5]=v&S[2]&~S[1]&S[0];
assign Y[6]=v&S[2]&S[1]&~S[0];
assign Y[7]=v&S[2]&S[1]&S[0];
endmodule
Testbench:
‘timescale 1ns / 1ps
module demux_8x1_test;
reg v; // Inputs
reg S0;
reg S1;
reg S2;
wire [7:0]Y; // Outputs
demux_1x8 uut ( // Instantiate the Unit Under Test (UUT)

.Y(Y),
.v(v),
.S0(S0),
.S1(S1),
.S2(S2)
);

initial begin
#2 v=1;S2=0;S1=0;S0=0;
#2 v=1;S2=0;S1=0;S0=1;
 #2 v=1;S2=0;S1=1;S0=0;
#2 v=1;S2=0;S1=1;S0=1;
#2 v=1;S2=1;S1=0;S0=0;
#2 v=1;S2=1;S1=0;S0=1;
#2 v=1;S2=1;S1=1;S0=0;
#2 v=1;S2=1;S1=1;S0=1;
#3 $stop;
end
initial begin
$monitor($time ,"The v=%b,S0=%b,S1=%b,S2=%b,Y=%b",Y,v,S0,S1,S2);
end

endmodule

Results:1x8demultiplexer with enable input has been designed using Verilog HDL and the operation is verified by observing the
timing diagram generated by the testbench.
Timing Diagram:
6)Fulladder AND HalfAdder:
6a)HallfAdder:
Aim: To design, and implement halfadder using Verilog HDL and verify the operation by writing a testbench.
Program:
module halfadder_data(Cout,S,A,B);
input A,B,S;
output Cout;
assign {Cout,S}=A+B;
endmodule

Testbench:
module hafladder_testdata;
reg A; //Inputs
reg B;
wire S; // Outputs
wire Cout;
halfadder_data uut ( // Instantiate the Unit Under Test (UUT)

.S(S),
.Cout(Cout),
.A(A),
 .B(B)

);

initial begin
#2 A=0;B=0;
#2 A=0;B=1;
#2 A=1;B=0;
#2 A=1;B=1;
#2 $stop;

end
initial begin
$monitor($time ,"The S=%b,Cout=%b,A=%b,B=%b",S,Cout,A,B);
end

endmodule

Results:Halfadder has been designed using Verilog HDL and the operation is verified by observing the timing diagram generated by
the testbench.
Timimg Daigram:
6b)Aim: To design, and implement halfadder using Verilog HDL and verify the operation by writing a testbench.
Program:
module fulladder_data(S,Cout,A,B,C);
input A,B,C;
output S,Cout;
assign {Cout,S}=A+B+C;
endmodule
Testbench:
module test_fulladder;
reg A; //Inputs
reg B;
reg C;
wire S; //Outputs
wire Cout;
fulladder_data uut ( // Instantiate the Unit Under Test (UUT)

.S(S),
.Cout(Cout),
.A(A),
.B(B),
.C(C)
 );

initial begin
#2 A=0;B=0;C=0;
#2 A=0;B=0;C=1;
#2 A=0;B=1;C=0;
#2 A=0;B=1;C=1;
#2 A=1;B=0;C=0;
#2 A=1;B=0;C=1;
#2 A=1;B=1;C=0;
#2 A=1;B=1;C=1;
#2 $stop;
end
initial begin
$monitor($time ,"The S=%b,Cout=%b,A=%b,B=%b,C=%b",S,Cout,A,B,C);

end
endmodule

Results:Fulladder has been designed using Verilog HDL and the operation is verified by observing the timing diagram generated by
the testbench.
Timing Diagram:
7)4-bit Binary to Gray:
Aim: To design, and implement 4-bit Binary to Gray using Verilog HDL and verify the operation by writing a testbench.
Program:
module bin2gray_data(G,B);
input [3:0]B;
output [3:0]G;
assign G[3]=B[3];
assign G[2]=B[3]^B[2];
assign G[1]=B[2]^B[1];
assign G[0]=B[1]^B[0];
endmodule
Testbench:
module bin2gray_test;
reg [3:0]B; // Inputs
wire [3:0]G; // Outputs
bin2gray uut ( // Instantiate the Unit Under Test (UUT)

.G(G),
.B(B)
);
initial begin
#2 B=4'b0000;
#2 B=4'b0001;
#2 B=4'b0011;
#2 B=4'b0010;
#2 B=4'b0111;
#2 B=4'b0110;
#2 B=4'b0100;
#2 B=4'b0101;
#2 B=4'b1111;
#2 B=4'b1110;
#2 B=4'b1100;
#2 B=4'b1101;
#2 B=4'b1000;
#2 B=4'b1001;
#2 B=4'b1011;
#2 B=4'b1010;
#2 $stop;

end
initial begin
 $monitor($time ," G=%b,B=%b",G,B);
end
endmodule

Results:4-bit Binary to gray code converter has been designed using Verilog HDL and the operation is verified by observing the
timing diagram generated by the testbench.
Timing Diagram:
7)4-bit Gray to Binary:
Aim: To design, and implement 4-bit Gray to Binary using Verilog HDL and verify the operation by writing a testbench.
Program:
module gray2bin_data(B,G);
input [3:0]G;
output [3:0]B;
assign B[3]=G[3];
assign B[2]=G[3]^G[2];
assign B[1]=G[3]^G[2]^G[1];
assign B[0]=G[3]^G[2]^G[1]^G[0];
endmodule
Testbench:
module gray2bin_test;
reg [3:0]G; //Inputs
wire [3:0]B; // Outputs
gray2bin uut ( // Instantiate the Unit Under Test (UUT)

.B(B),
.G(G)
);
initial begin
#2 G=4'b0000;
#2 G=4'b0001;
#2 G=4'b0010;
#2 G=4'b0011;
#2 G=4'b0100;
#2 G=4'b0101;
#2 G=4'b0110;
#2 G=4'b0111;
#2 G=4'b1000;
#2 G=4'b1001;
#2 G=4'b1010;
#2 G=4'b1011;
#2 G=4'b1100;
#2 G=4'b1101;
#2 G=4'b1110;
#2 G=4'b1111;
#2 $stop;

end
 initial begin
$monitor($time ," B=%b,G=%b",B,G);
end

endmodule

Results:4-bit Gray to Binary code converter has been designed using Verilog HDL and the operation is verified by observing the
timing diagram generated by the testbench.
Timing Diagram:
7)4-bit Comparator:
Aim: To design, and implement 4-bit Comparator using Verilog HDL and verify the operation by writing a testbench.
Program:
module bit_4comp_data(a_gt_b,a_lt_b,a_eq_b,a,b);
input [3:0]a;
input [3:0]b;
output a_gt_b,a_eq_b,a_lt_b;

assign a_gt_b=(a>b);
assign a_lt_b=(a<b);
assign a_eq_b=(a==b);

endmodule
Testbench:
module test_datacomp;

reg [3:0]a;
reg [3:0]b;

// Outputs
wire a_eq_b;
wire a_lt_b;
wire a_gt_b;

// Instantiate the Unit Under Test (UUT)

bit_4comp_data uut (
.a_eq_b(a_eq_b),
.a_lt_b(a_lt_b),
.a_gt_b(a_gt_b),
.a(a),
.b(b)
);

initial begin
a=4'b1100;
b=4'b1100;
#4;
a=4'b0100;
b=4'b1100;
#4;
a=4'b1111;
b=4'b1100;
 #4;
a=4'b0000;
b=4'b0000;
#4;
#4$stop;
end
initial begin
$monitor ($time, "a=%b, b=%b, a_eq_b=%b,a_lt_b=%b,a_gt_b=%b",a,b,a_eq_b,a_lt_b,a_gt_b);
end

endmodule
Results: Halfadder and Fulladder has been designed using Verilog HDL and the operation is verified by observing the timing
diagram generated by the testbench.
Timing Diagram: