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10 November 2019 1441 ‫ ربيع األول‬13

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Analog IC Design

Lecture 12
The Five-Transistor (5T) OTA

Dr. Hesham A. Omran

Integrated Circuits Laboratory (ICL)
Electronics and Communications Eng. Dept.
Faculty of Engineering
Ain Shams University
 Outline
❑ Recapping previous key results
❑ Op-amp vs OTA
❑ Differential to single-ended conversion
❑ Five-transistor OTA Analysis
A. Small signal analysis
1. Diff small signal analysis
2. CM small signal analysis
B. Large signal analysis
1. Diff large signal analysis
2. CM large signal analysis
❑ Effect of mismatch
❑ 5T OTA frequency response

12: 5T OTA 2
 Outline
❑ Recapping previous key results
❑ Op-amp vs OTA
❑ Differential to single-ended conversion
❑ Five-transistor OTA Analysis
A. Small signal analysis
1. Diff small signal analysis
2. CM small signal analysis
B. Large signal analysis
1. Diff large signal analysis
2. CM large signal analysis
❑ Effect of mismatch
❑ 5T OTA frequency response

12: 5T OTA 3
 MOSFET in Saturation
❑ The channel is pinched off if the difference between the gate and
drain voltages is not sufficient to create an inversion layer
𝑉𝐺𝐷 ≤ 𝑉𝑇𝐻 𝑂𝑅 𝑉𝐷𝑆 ≥ 𝑉𝑜𝑣
❑ Square-law (long channel MOS)
𝜇𝑛 𝐶𝑜𝑥 𝑊 2 1 + 𝜆𝑉
𝐼𝐷 = ⋅ 𝑉𝑜𝑣 𝐷𝑆 VSG > |VTH|
2 𝐿

𝑉𝑆𝐵 ↑ ⇒ 𝑉𝑇𝐻 ↑ VSD > |Vov|

VDG < |VTH|
VGS>VTH VGD<VTH
VSB G
B S D VGD < VTH

VDS > Vov

p+ n+ n+
p-sub VGS > VTH
VDS>Vov
Recapping Key Results 4
 Regions of Operation Summary
OFF
ON
(Subthreshold)
𝑉𝐺𝑆 > 𝑉𝑇𝐻
𝑉𝐺𝑆 < 𝑉𝑇𝐻

Triode Pinch-Off
(Saturation)
𝑉𝐷𝑆 < 𝑉𝑜𝑣
𝑉𝐷𝑆 ≥ 𝑉𝑜𝑣
Or
Or
𝑉𝐺𝐷 > 𝑉𝑇𝐻
𝑉𝐺𝐷 ≤ 𝑉𝑇𝐻

𝑊 2
𝑉𝐷𝑆 𝜇𝐶𝑜𝑥 𝑊 2
𝐼𝐷 = 𝜇𝐶𝑜𝑥 𝑉 𝑉 − 𝐼𝐷 = 𝑉 1 + 𝜆𝑉𝐷𝑆
𝐿 𝑜𝑣 𝐷𝑆 2 2 𝐿 𝑜𝑣

Recapping Key Results 5

 High Frequency Small Signal Model
𝜕𝐼𝐷 𝑊 𝑊 2𝐼𝐷
𝑔𝑚 = = 𝜇𝐶𝑜𝑥 𝑉 = 𝜇𝐶𝑜𝑥 ⋅ 2𝐼𝐷 =
𝜕𝑉𝐺𝑆 𝐿 𝑜𝑣 𝐿 𝑉𝑜𝑣

𝑔𝑚𝑏 = 𝜂𝑔𝑚 𝜂 ≈ 0.1 − 0.25

1 𝑉𝐴 1 1
𝑟𝑜 = = = 𝑉𝐴 ∝ 𝐿 ↔ 𝜆 ∝ 𝑉𝐷𝑆 ↑ 𝑉𝐴 ↑
𝜕𝐼𝐷 /𝜕𝑉𝐷𝑆 𝐼𝐷 𝜆𝐼𝐷 𝐿

𝐶𝑔𝑏 ≈ 0 𝐶𝑔𝑠 ≫ 𝐶𝑔𝑑 𝐶𝑠𝑏 > 𝐶𝑑𝑏

Cgd
G D

Cgb Cgs gmvgs gmbvbs ro Cdb

Csb
S
B
Recapping Key Results 6
 Rin/out Shortcuts Summary

𝑟𝑜 1 + 𝑔𝑚 + 𝑔𝑚𝑏 𝑅𝑆
H.I.N.

1 𝑅𝐷
∞ 1+
𝑔𝑚 + 𝑔𝑚𝑏 𝑟𝑜
At low
frequencies ONLY L.I.N.

Recapping Key Results 7

 Summary of Basic Topologies
CS CG CD (SF)

RD RD RD
vout vout
vin vin
vin vout
RS RS RS

Voltage & current amplifier Voltage amplifier Voltage buffer

Current buffer Current amplifier
1 𝑅𝐷
Rin ∞ 𝑅𝑆 || 1+ ∞
𝑔𝑚 + 𝑔𝑚𝑏 𝑟𝑜
1 𝑅𝐷
Rout 𝑅𝐷 ||𝑟𝑜 1 + 𝑔𝑚 + 𝑔𝑚𝑏 𝑅𝑆 𝑅𝐷 ||𝑟𝑜 𝑅𝑆 || 1+
𝑔𝑚 + 𝑔𝑚𝑏 𝑟𝑜
−𝒈𝒎 𝒈𝒎
Gm 𝒈𝒎 + 𝒈𝒎𝒃
𝟏 + 𝒈𝒎 + 𝒈𝒎𝒃 𝑹𝑺 𝟏 + 𝑹𝑫 /𝒓𝒐
Recapping Key Results 8
 Differential Amplifier
Pseudo Diff Amp Diff Pair (w/ ideal CS) Diff Pair (w/ 𝑹𝑺𝑺 )

𝑨𝒗𝒅 −𝑔𝑚 𝑅𝐷 −𝑔𝑚 𝑅𝐷 −𝑔𝑚 𝑅𝐷

−𝑔𝑚 𝑅𝐷
𝑨𝒗𝑪𝑴 −𝑔𝑚 𝑅𝐷 0
1 + 2 𝑔𝑚 + 𝑔𝑚𝑏 𝑅𝑆𝑆

2 𝑔𝑚 + 𝑔𝑚𝑏 𝑅𝑆𝑆
𝑨𝒗𝒅 /𝑨𝒗𝑪𝑴 1 ∞
≫1

𝑣𝑜𝑑 Δ𝑅𝐷 Δ𝑔𝑚 𝑅𝐷

𝐴𝑣𝐶𝑀2𝑑 = ≈ +
𝑣𝑖𝐶𝑀 2𝑅𝑆𝑆 2𝑔𝑚1,2 𝑅𝑆𝑆
𝐴𝑣𝑑
𝐶𝑀𝑅𝑅 =
𝐴𝑣𝐶𝑀2𝑑

Recapping Key Results 9

 Outline
❑ Recapping previous key results
❑ Op-amp vs OTA
❑ Differential to single-ended conversion
❑ Five-transistor OTA Analysis
A. Small signal analysis
1. Diff small signal analysis
2. CM small signal analysis
B. Large signal analysis
1. Diff large signal analysis
2. CM large signal analysis
❑ Effect of mismatch
❑ 5T OTA frequency response

12: 5T OTA 10
 Op-Amp
❑ An op-amp is simply a high gain differential amplifier
▪ The gain can be increased by using cascodes and multi-stage
amplification
❑ The diff amp is a key block in many analog and RF circuits
▪ DEEP understanding of diff amp is ESSENTIAL

M3 M4
Vout
Vin+
Vout Vin+ M1 M2 Vin-
Vin-

VB M5

12: 5T OTA 11
 Op-Amp vs OTA
❑ Ideal op-amp has infinite 𝑅𝑖𝑛 , infinite gain, and zero 𝑅𝑜𝑢𝑡
❑ Practical op-amp has HIGH 𝑅𝑖𝑛 , HIGH gain, and LOW 𝑅𝑜𝑢𝑡
▪ LOW 𝑅𝑜𝑢𝑡 required to avoid loading when driving resistive loads
▪ The op-amp is usually implemented as a multistage amplifier
▪ The last stage (output stage) is a buffer to provide LOW 𝑅𝑜𝑢𝑡
❑ IC CMOS op-amps usually drive capacitive loads
▪ Usually, there is no need for LOW 𝑅𝑜𝑢𝑡
▪ The output stage (buffer) is not required
▪ These modern integrated op-amps are usually called
Operational Transconductance Amplifiers (OTAs)

Buffer

12: 5T OTA 12
 Op-Amp vs OTA
❑ In short, an OTA is an op-amp without an output stage (buffer)
❑ Some designers just use op-amp name and symbol for both
Op-amp OTA
Rout LOW HIGH
Rout iout iout
vin vout vin vout
iin iin
Model Rin Avvin Rin Gmvin Rout

Diff input, SE output

Fully diff

12: 5T OTA 13
 Outline
❑ Recapping previous key results
❑ Op-amp vs OTA
❑ Differential to single-ended conversion
❑ Five-transistor OTA Analysis
A. Small signal analysis
1. Diff small signal analysis
2. CM small signal analysis
B. Large signal analysis
1. Diff large signal analysis
2. CM large signal analysis
❑ Effect of mismatch
❑ 5T OTA frequency response

12: 5T OTA 14
 How to Get SE Output?
❑ Trivial solution: discard one output!
▪ But the gain is halved (and the CMRR is poor ~ 𝑔𝑚 𝑅𝑆𝑆 )
❑ Better solution: use a diff to single-ended (SE) converter (but
how?!)

RD RD
Vout
Vin+ Vin+ M1 M2
Vout VP
Vin- Vin-
ISS

12: 5T OTA 15
 5T OTA
❑ A.k.a. diff pair with active load, diff pair with CM load, unbalanced
diff pair.
❑ Can be viewed in two ways
1. We use a current mirror to transfer the small signal current
from the left side to the right side.
2. M3 is a diode-connected load and M4 is a CS amplifier that
transfers the small signal voltage from the left side to the right
side.
M3 M4 M3 M4
?
Vout Vout
Vin+ M1 M2 Vin- Vin+ M1 M2 Vin-
VP VP

ISS ISS
12: 5T OTA 16
 Outline
❑ Recapping previous key results
❑ Op-amp vs OTA
❑ Differential to single-ended conversion
❑ Five-transistor OTA Analysis
A. Small signal analysis
1. Diff small signal analysis
2. CM small signal analysis
B. Large signal analysis
1. Diff large signal analysis
2. CM large signal analysis
❑ Effect of mismatch
❑ 5T OTA frequency response

12: 5T OTA 17
 5T OTA Analysis
❑ In general, half-circuit principle
cannot be used due to asymmetry

❑ Similar to diff amp, we carry four

types of analysis: M3 M4
A. Small signal analysis Vout
1. Diff small signal analysis Vin+ M1 M2 Vin-
VP
2. CM small signal analysis
B. Large signal analysis ISS
1. Diff large signal analysis
2. CM large signal analysis

12: 5T OTA 18
 A1. Diff Small Signal Analysis
❑ Solve it as a whole using GmRout (apply superposition)
❑ Each side contributes to 𝑖𝑜𝑢𝑡 twice: directly and through the mirror
′ ′′
𝑖𝑜𝑢𝑡 = 𝑖𝑜𝑢𝑡 + 𝑖𝑜𝑢𝑡

𝑔𝑚1 𝑣𝑖𝑑 𝑔𝑚2 𝑣𝑖𝑑

𝑖𝑜𝑢𝑡 ≈ ⋅𝟐⋅ + ⋅𝟐⋅
1 + 𝑔𝑚1 (1/𝑔𝑚2 ) 2 1 + 𝑔𝑚2 1/𝑔𝑚1 2
𝑖𝑜𝑢𝑡
𝐺𝑚 = ≈ 𝑔𝑚1,2
𝑣𝑖𝑑

M3 M4 M3 M4
iout i'out

vid/2 M1 M2 -vid/2 vid/2 M1 M2

12: 5T OTA 19
 A1. Diff Small Signal Analysis
𝑣𝑥 𝑣𝑥
𝑅𝑜𝑢𝑡 = = ||𝑟𝑜4
𝑖𝑥 2𝑖𝑦
𝑣𝑥
= 𝑅𝐿𝐹𝐷,𝑀2 ≈ 𝑟𝑜2 1 + 𝑔𝑚2 𝑅𝐿𝐹𝑆,𝑀1 ≈ 2𝑟𝑜2
𝑖𝑦
𝑅𝑜𝑢𝑡 ≈ 𝑟𝑜2 ||𝑟𝑜4
𝑣𝑜𝑢𝑡
𝐴𝑣𝑑 = ≈ 𝑔𝑚1,2 𝑟𝑜2 ||𝑟𝑜4
𝑣𝑖𝑑

1/gm3
ro4
iy iy
ix
vx
iy

ro1 ro2

12: 5T OTA 20
 A2. CM Small Signal Analysis
❑ If the tail CS is ideal
▪ The two sides will generate current in the same direction
▪ Thus both currents must be zero
𝑣𝑜𝑢𝑡 𝐴𝑣𝑑
𝑣𝑜𝑢𝑡 = 0 ⇒ 𝐴𝑣𝐶𝑀 = = 0 ⇒ 𝐶𝑀𝑅𝑅 = →∞
𝑣𝑖𝐶𝑀 𝐴𝑣𝐶𝑀

M3 M4 M3 M4

Vout Vout

ViCM M1 M2 ViCM ViCM M1 M2 ViCM

VP

ISS

12: 5T OTA 21
 A2. CM Small Signal Analysis
❑ For non-ideal tail CS: 𝐴𝑣𝐶𝑀 ≠ 0 and 𝐶𝑀𝑅𝑅 ≠ ∞
❑ The presence of 𝑅𝑆𝑆 complicates the analysis. Using SLiCAP yields:

1
𝐴𝑣𝐶𝑀 ≈ −
2𝑔𝑚3,4 𝑅𝑆𝑆
❑ Can we derive the same result intuitively?

M3 M4
VF
Vout
ViCM M1 M2 ViCM
VP

ISS RSS

12: 5T OTA [www.analog-electronics.eu/slicap/slicap.html] 22

 A2. CM Small Signal Analysis
❑ M1 and M2 have the same 𝑉𝐺𝑆 : Difference in 𝐼𝐷 depends on 𝑉𝐷𝑆
❑ M3 and M4 have the same 𝑉𝐺𝑆 : Difference in 𝐼𝐷 depends on 𝑉𝐷𝑆
❑ Assume 𝑉𝐹 < 𝑉𝑜𝑢𝑡
▪ 𝐼𝐷1 < 𝐼𝐷2 and 𝐼𝐷3 > 𝐼𝐷4 → Not a valid assumption
❑ Assume 𝑉𝐹 > 𝑉𝑜𝑢𝑡
▪ 𝐼𝐷1 > 𝐼𝐷2 and 𝐼𝐷3 < 𝐼𝐷4 → Not a valid assumption
❑ The only valid assumption is 𝑉𝐹 = 𝑉𝑜𝑢𝑡 → As if there is a s.c.!

M3 M4 M3 M4
VF VF
Vout Vout
ViCM M1 M2 ViCM ViCM M1 M2 ViCM
VP VP

ISS RSS ISS RSS

12: 5T OTA 23
 A2. CM Small Signal Analysis
❑ For CM input, 𝑉𝑜𝑢𝑡 follows 𝑉𝐹 → As if there is a s.c. between them
❑ The circuit becomes symmetric → Apply half circuit principle
𝑉𝑜𝑢𝑡 −𝑔𝑚1,2 1 1
𝐴𝑣𝐶𝑀 = = 𝐺𝑚 𝑅𝑜𝑢𝑡 ≈ ≈−
𝑉𝑖𝐶𝑀 1 + 2𝑔𝑚1,2 𝑅𝑆𝑆 𝑔𝑚3,4 2𝑔𝑚3,4 𝑅𝑆𝑆

❑ Same as SLiCAP’s result ☺

M3 M4 M4
VF
Vout Vout
ViCM M1 M2 ViCM
VP M2 ViCM

ISS RSS 2RSS

12: 5T OTA 24
 CMRR
𝑉𝑜𝑢𝑡
𝐴𝑣𝑑 = ≈ 𝑔𝑚1,2 𝑟𝑜2 //𝑟𝑜4
𝑉𝑖𝑑
𝑉𝑜𝑢𝑡 1
𝐴𝑣𝐶𝑀 = ≈−
𝑉𝑖𝐶𝑀 2𝑔𝑚3,4 𝑅𝑆𝑆
2
𝐶𝑀𝑅𝑅 ≈ 𝑔𝑚1,2 𝑟𝑜2 //𝑟𝑜4 ⋅ 2𝑔𝑚3,4 𝑅𝑆𝑆 ~ 𝑔𝑚 𝑟𝑜

❑ The CMRR is much better than the trivial case of getting SE output
by dropping one differential output
▪ For the trivial case 𝐶𝑀𝑅𝑅 ≈ 𝑔𝑚 𝑅𝑆𝑆 ~ 𝑔𝑚 𝑟𝑜
❑ CM noise will affect the SE output even in the case of perfect
symmetry
▪ A clear disadvantage compared to fully diff OTA
❑ The effective 𝑅𝑆𝑆 degrades at high frequency
12: 5T OTA 25
 Outline
❑ Recapping previous key results
❑ Op-amp vs OTA
❑ Differential to single-ended conversion
❑ Five-transistor OTA Analysis
A. Small signal analysis
1. Diff small signal analysis
2. CM small signal analysis
B. Large signal analysis
1. Diff large signal analysis
2. CM large signal analysis
❑ Effect of mismatch
❑ 5T OTA frequency response

12: 5T OTA 26
 B1. Diff Large Signal Analysis
❑ 𝑉𝑖𝑑 = 𝑉𝑖𝑛1 − 𝑉𝑖𝑛2 ≫ 0
▪ M1 and M3 ON → M4 ON (triode) → small resistance
▪ M2 OFF → large resistance
▪ 𝑉𝑜𝑢𝑡 ≈ 𝑉𝐷𝐷

M3 M4
Vout
VF
Vout VDD
Vin1 M1 M2 Vin2
VP

VB M5 Vind

12: 5T OTA 27
 B1. Diff Large Signal Analysis
❑ 𝑉𝑖𝑑 = 𝑉𝑖𝑛1 − 𝑉𝑖𝑛2 ≪ 0
▪ M1 and M3 OFF → M4 OFF → large resistance
▪ M2 and M5 ON (triode) → small resistance
▪ 𝑉𝑜𝑢𝑡 ≈ 0

M3 M4
Vout
VF
Vout VDD
Vin1 M1 M2 Vin2
VP

VB M5 Vind

12: 5T OTA 28
 B2. CM Large Signal Analysis
❑ All transistors must be in saturation

M3 M4
VF
Vout

ViCM M1 M2 ViCM
VP

VB M5

❑ Tail CS in sat
𝑉𝑖𝐶𝑀 ≥ 𝑉𝑇𝐻𝑁 + 𝑉𝑜𝑣1 + 𝑉𝑜𝑣5
❑ Input pair in sat
𝑉𝑖𝐶𝑀 ≤ 𝑉𝐷𝐷 − 𝑽𝑻𝑯𝑷 − 𝑉𝑜𝑣3 + 𝑉𝑇𝐻𝑁

12: 5T OTA 29
 Outline
❑ Recapping previous key results
❑ Op-amp vs OTA
❑ Differential to single-ended conversion
❑ Five-transistor OTA Analysis
A. Small signal analysis
1. Diff small signal analysis
2. CM small signal analysis
B. Large signal analysis
1. Diff large signal analysis
2. CM large signal analysis
❑ Effect of mismatch
❑ 5T OTA frequency response

12: 5T OTA 30
 Effect of Mismatch (in Input Pair)
❑ Use superposition (left + right)
′ ′′
𝑣𝑜𝑢𝑡 𝑣𝑜𝑢𝑡 𝟐𝑔𝑚1 𝟐𝑔𝑚2
𝐴𝑣𝐶𝑀 = + ≈ − 𝑅𝑜𝑢𝑡
𝑣𝑖𝐶𝑀 𝑣𝑖𝐶𝑀 1 1
1 + 𝑔𝑚1 ||𝑅𝑆𝑆 1 + 𝑔𝑚2 ||𝑅
𝑔𝑚2 𝑔𝑚1 𝑆𝑆
2Δ𝑔𝑚 𝑅𝑜𝑢𝑡 Δ𝑔𝑚 𝑅𝑜𝑢𝑡
= ≈
1 + 𝑔𝑚1 + 𝑔𝑚2 𝑅𝑆𝑆 𝑔𝑚1,2 𝑅𝑆𝑆

M3 M4
VF
Vout

ViCM M1 M2 ViCM
VP

ISS RSS

12: 5T OTA 31
 CMRR with Mismatch
❑ Overall CM small signal response (matched + mismatch)
𝑔𝑚1,2 𝑔𝑚1,2
−𝑔 2Δ𝑔 𝑅 −𝑔 + 2Δ𝑔𝑚 𝑅𝑜𝑢𝑡
𝑚3,4 𝑚 𝑜𝑢𝑡 𝑚3,4
𝐴𝑣𝐶𝑀 ≈ + ≈
1 + 2𝑔𝑚1,2 𝑅𝑆𝑆 1 + 2𝑔𝑚1,2 𝑅𝑆𝑆 2𝑔𝑚1,2 𝑅𝑆𝑆

❑ Common-mode rejection ratio (CMRR) (@low frequency!)

𝐴𝑣𝑑 = 𝑔𝑚1,2 𝑅𝑜𝑢𝑡

𝐴𝑣𝑑 2𝑔𝑚1,2 𝑅𝑆𝑆

𝐶𝑀𝑅𝑅 = ≈
𝐴𝑣𝐶𝑀 − 1 Δ𝑔𝑚
+2
𝑔𝑚3,4 𝑅𝑜𝑢𝑡 𝑔𝑚1,2

12: 5T OTA 32
 Outline
❑ Recapping previous key results
❑ Op-amp vs OTA
❑ Differential to single-ended conversion
❑ Five-transistor OTA Analysis
A. Small signal analysis
1. Diff small signal analysis
2. CM small signal analysis
B. Large signal analysis
1. Diff large signal analysis
2. CM large signal analysis
❑ Effect of mismatch
❑ 5T OTA frequency response

12: 5T OTA 33
 Differential Frequency Response: Poles
❑ Output pole: 𝐶𝑜𝑢𝑡 ≈ 𝐶𝑑𝑏4 + 𝐶𝑑𝑏2 + 𝑓 𝐶𝑔𝑑4 + 𝐶𝑔𝑑2 + 𝐶𝐿
1
𝜔𝑝1 ≈
𝑅𝑜𝑢𝑡 𝐶𝑜𝑢𝑡
❑ Mirror pole: 𝐶𝑚𝑖𝑟𝑟 ≈ 𝐶𝑔𝑠3 + 𝐶𝑔𝑠4 + 𝐶𝑑𝑏3 + 𝐶𝑑𝑏1 + 𝐶𝑔𝑑1 + 𝑓 𝐶𝑔𝑑4
𝑔𝑚3
𝜔𝑝2 ≈
𝐶𝑚𝑖𝑟𝑟

M3 M4
CL
Vout
𝑣𝑝 acts as virtual ground
Vin1 M1 M2 Vin2
at high frequency (why?) VP

ISS

12: 5T OTA 34
 Differential Frequency Response: LHP Zero
❑ At 𝑠𝑧 : 𝑣𝑜𝑢𝑡 = 0 ⇒ 𝑖𝑜𝑢𝑡 = 0 ⇒ 𝑔𝑚4 𝑣𝑠𝑔4 = 𝑔𝑚2 𝑣𝑔𝑠2
1 1
𝑔𝑚1 || ⋅ 𝑔𝑚4 ⋅ 𝑣𝑖𝑛1 = 𝑔𝑚2 ⋅ 𝑣𝑖𝑛2
𝑔𝑚3 𝑠𝑧 𝐶𝑚𝑖𝑟𝑟
2𝑔𝑚3,4
𝑠𝑧 = − ⇒ 𝜔𝑧 = 2𝜔𝑝2
𝐶𝑚𝑖𝑟𝑟
❑ Can we get same result by inspection?

Cmirr M3 M4

Vout = 0
𝑣𝑝 acts as virtual ground iout = 0
Vin1 M1 M2 Vin2
at high frequency (why?) VP Rout

ISS

12: 5T OTA 35
 Thank you!

12: 5T OTA 36
 References
❑ A. Sedra and K. Smith, “Microelectronic Circuits,” 7th ed., Oxford
University Press, 2015
❑ B. Razavi, “Fundamentals of Microelectronics,” 2nd ed., Wiley, 2014
❑ B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-
Hill, 2nd ed., 2017
❑ T. C. Carusone, D. Johns, and K. W. Martin, “Analog Integrated
Circuit Design,” 2nd ed., Wiley, 2012

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