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P2003BDG Niko-Sem: N-Channel Logic Level Enhancement Mode Field Effect Transistor
P2003BDG Niko-Sem: N-Channel Logic Level Enhancement Mode Field Effect Transistor
P2003BDG Niko-Sem: N-Channel Logic Level Enhancement Mode Field Effect Transistor
D
PRODUCT SUMMARY
V(BR)DSS RDS(ON) ID 1. GATE
2. DRAIN
25 20mΩ 35A G
3. SOURCE
1 DEC-23-2004
N-Channel Logic Level Enhancement P2003BDG
NIKO-SEM TO-252 (DPAK)
Mode Field Effect Transistor
Lead-Free
Fall Time2 tf 18 27
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C)
Continuous Current IS 35
A
Pulsed Current3 ISM 120
Forward Voltage1 VSD IF = IS, VGS = 0V 1.1 1.4 V
Reverse Recovery Time trr 15 18 nS
Reverse Recovery Charge Qrr 2 3 nC
1
Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2%.
2
Independent of operating temperature.
3
Pulse width limited by maximum junction temperature.
2 DEC-23-2004
N-Channel Logic Level Enhancement P2003BDG
NIKO-SEM TO-252 (DPAK)
Mode Field Effect Transistor
Lead-Free
TYPICAL CHARACTERISTICS
ON-REGION CHARACTERISTIC ON- RESISTANCE VARIATION WITH DRAIN CURRENT AND GATE VOLTAGE
60 3.0
55 10.0V 5.0V
VGS = 4.0V
45
R DS(ON) ,NORMALIZED
4.5V
40 2.0
35 4.5V
30 5.0V
1.5
6.0V
25 7.0V
4.0V
20 1.0 10V
15
3.5V
10 0.5
5 VGS =3.0V
0 0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 10 20 30 40 50 60
VDS,DRAIN- SOURCE VOLTAGE ( V ) I D ,DRAIN CURRENT( A )
ON- RESISTANCE VARIATION WITH TEMPERATURE ON-RESISTANCE VARIATION WITH GATE-TO-SOURCE VOLTAGE
1.8 0.06
I D = 15A
ID = 15A
DRAIN - SOURCE ON - RESISTANCE
VGS= 10V
R DS(ON) ,ON-RESISTANCE(OHM)
1.6
0.05
,NORMALIZED
1.4
0.04
1.2
0.03
DS(ON)
1.0
R
TA = 125°C
0.8 0.02
TA = 25°C
0.6 0.01
-50 -25 0 25 50 75 100 125 150 175 2 6 8 10
4
Tj ,JUNCTION TEMPERATURE( °C )
VGS,GATE TO SOURCE VOLTAGE
BODY DIODE FORWARD VOLTAGE VARIATION WITH
TRANSFER CHARACTERISTICS SOURCE CURRENT AND TEMPERATURE
60 60
TA = -55°C 25°C VGS= 0V
VDS =10V
I S,REVERSE DRAIN CURRENT( A )
50 125°C 10
I D,DRAIN CURRENT( A )
TA = 125°C
40 1
25°C -55°C
30 0.1
20 0.01
10 0.001
0 0.0001
1 2 3 4 5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VGS,GATE TO SOURCE VOLTAGE VSD ,BODY DIODE FORWARD VOLTAGE( V )
3 DEC-23-2004
N-Channel Logic Level Enhancement P2003BDG
NIKO-SEM TO-252 (DPAK)
Mode Field Effect Transistor
Lead-Free
I D = 15A 15V
CAPACITANCE( pF )
VDS = 5V 1000
10V Ciss
6
Coss
4
100
Crss
f = 1MHZ
VGS= 0V
0 10
0 4 8 12 16 1 5 10 15 20 25 30
Qg ,GATE CHARGE ( nC ) VDS ,DRAIN TO SOURCE VOLTAGE ( V )
SINGLEPULSE MAXIMUMPOWERDISSIPATION MAXIMUM SAFE OPERATING AREA
3
2400 SINGLE PULSE 10
Rθ = 2 .5°C/W
JC
TC = 25°C
2000
I D,DRAIN CURRENT( A )
2 35.0µS
POWER( W )
1600 10
it
n)
Lim 10
0µ
R ds(o S
1200 1m
s
10m
s
DC
1
800 10
0
D=0.5
10
0.20
0.10
-1
10
0.05
0.02
10
-2 0.01
P(pk)
t1
-3 t2
10 1.RθJC (t)=r(t)*R
2.R θJC = 2.5° C/W
Single pulse 3.T j + TC = P * R θJC (t)
t1
4.Duty Cycle,D =
-4 t2
10
-7 -6 -5 -4 -3 -2 -1 0
10 10 10 10 10 10 10 10
t1 , TIME( ms )
4 DEC-23-2004
N-Channel Logic Level Enhancement P2003BDG
NIKO-SEM TO-252 (DPAK)
Mode Field Effect Transistor
Lead-Free
mm mm
Dimension Dimension
Min. Typ. Max. Min. Typ. Max.
G 5.2 6.2 N
A
B
D
E
C
H G
L
3
M
2
J
I
5 DEC-23-2004