Mlcroconlrolado

ARQUITECTURA VON NEl,t,lANN

8US DE COÑTRü
lt,lE],lORIA CENTRAL

BUS DI
Ut{IDAD t,IIIDAD I)IIlI (ilONI t,I{IDAD
DE DE
CEl{TRAt DE
1'IEU0RIA ltlEI,IORIA
PROCESO
RAt,l RO}.l BUS DI DAIOS I

I\STRUCCIONES

IIISTRUCCIOTI ES + DAIOS
Esquema de arquitectura de Harvard
ARQUIITCTURA HARVARD

NEMORIADE [IE[IORIA OE
INSTRUCCIONES DATOS

OIftCIIONTSDE DIIELTIONE5DE
lNSInUt 0\t§ UNlDAD
CENIML DE
PROCESO
8U5DT
3U5DtDlm5
-f ffi
-r-
tRr
 crsc
(Cornplex
RISC
(Stmple
lnstructtlon) lnsttructlon)
0110100:r00011000011010101010000
1010100010101000011110101011010

100100101010101000101101011110
101010101110010101010010101010
010111010101010101101010101010
I0100101010101010100101010I010
 G-*)
(j 3".-9
(,) (r )(,) (3 )
 1 40 <+ RB7/PGD
MO/ANO 2 39 É RB6/PGC
RA1/AN1 3 38 <+ RB5
RAZAN2 ,hEFJCVREF 4 37
RA3/AN3A,hEF+ 5 36 .+ RB3/PGM
RA4/TOCKYCl O UT 6 35
-RB4RB2
RASAN¿I/SSi/C2OUT 7
F-
u -.+ RBl
REO/RD/AN5 8 F- 33 <+ RBO/INT
RE1A FYAN6 9 32
RE2ICS-/AN7 10 31
11
F-
30 <+ RD7/PSP7
12 lt 29 + RD6/PSP6
oscl/cLKt + 28 <+ RD5/PSPs
osczcLKo 14
o 27 RD4/PSP4
o-
RCO/TÍ OSO/T 1 CKt 15 26 H RC7/RXDT
RC1/T10St/CCP2 16 25
- RC6r.[XCK
RC2/CCPl 17 24 .+ RCs/SDO
RCSSCIISCL 18 23
-<+ RC4/SDI/SDA
RDO/PSPO 19 22 RD3/PSP3
RDl/PSPl 20 21 <+ RD2/PSP2
-
t¡ : ":tTt:L" =

A
PROGRAM MEMORY MAP

22 Dáta Memory Orsanization

The dala memory s pani¡oned inlo
murlipre banks
Pufpose ReqisteE and lhe
specia Functon ResÉlefs Bls RP1 (slatus<6) and
RPo(slarus<s) e the bank$red bils
E
 Repisto Conbdú de Pro@
dúedón á sereje.ubdá

-fl
Eq*-* L
 STATUS REGTSTER (ADDRESS 03h, a3h,l03h,l83h)

IRP: Register Bank S€lect bit (used for nd rect addre$ing)

1= Bánk 2, 3 (10Oh lFFh)

RPt:Rm: Reg ster Bánk Selecl bils (usd lor diect addre$ ng)
11= Bánk 3 (140h lFFh)
10 = Bánk 2 (100h 17Fh)

1 = afler peerup, ckMinstuclion of SLEEP instuclion

o = a wDT lime out occufed

1 = afler powup or by tle cLRcDr instuct on

o = By exednon ofthe SLEEP instuclion

1 = The rsult ol án ánhmetic or logic ope6t on s zero

o = The rsult ol án ánhmetic or l@ic ope6t on s not zero
DC Digl , ¿rrylbm@ bil(sDr- sDrH,sGrH,SGHFin§tuclion.)
(for borow, tre polar ty is reversed)
1 = A €rry oul frcm the 4th low order bit of the resull oaured
o = No carry out from the 4tl l@ order bit of the resull
bt0 C: Cárry/bomwbt (sDc4 DDrw,scrw,scwF nslruclions)
1 = A €rry oul frcm the MGt S Sn fÉnt bit of the resull occured
o = No carry out from the lücl S gn licnl bil of tle r6ult occured
Nolé: For borow, the polanly s reversed A { blract on is exedted by adding tl e two s
complement ol the s{ond opeEnd For rolate (R4 RLF) nsrucl ons, tlis bil is
loaded wth eiher the h Ah, or l@ order bil of lhe eurce register
REGISIER2-l: STATUS REGISTER {ADDRESS 03h, 33h, 103h, 133h)

rRP: Res rsBmkse edb' (!*d for nd red addfss nq)

{u*d for difed addrssino

Dc Dis'mfry/btrmwbr{oDrF ñ¡LN, scrH, scrF mrudm,

(fof búN. po ad'y s rereEed)
'he

cc rylbtrrcw b' (DD,F mDL'.sBLí.sG'F Btm'iom)

Nde:FtrbÚN.$epoli'ykf
For fobre (RRe RLF) nstudons ris bris
 Registro STATUS

Contiene:
- Estado Artmético de la
ALU
Bit Indirect Register Bank Select:
- El estado del RESET
(usados para direcciionamietlto
- Bit selectores del Banco Irdirecto)
de memoria
I = Bank 2-3

0= Bank 0-l
llank3 (l ile llJo lllh)
Bank 2 (File r00 - 17Fh)
Bank 1 (File 080 - 0FFh)
Bank 0 (Filc 000 07Fh) Slalus register (SR)

Register File Bank Sele(t I

dccodcr IRP RPI RPO TO PD z DC c

Indilect Register File Bank Select -:::::: : : : : Calr'!/Borro\\

n I rfil, n00 nfflrl n
B.rnk : : : i.... ,r,g,, t arr! ¡ñiiññ
Banl-/r rtilp trx) ll|h) I : :
1'.........'''
:

7ern
Timc Out --------i i
:

\\.rt( hdog t llc out n :

rlrwclt/s1eep Insrlr,'trons I :

PL,\§cr Do\.!n.
ll), sl eep instruction 0
l]) cl rwdt insrru( lion I
 lnd¡rect Address¡ng, INDF and
FSR Reg¡sters A simple program to clear RAIV locations 20h-2Fh
using indirect addressing is shown

The INDF register is not a physicalregister. Addressing

the INDF reg ister will cause indirect addressing.
INDIRECT ADDRESSING
lndirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually initialize poinEer
accesses the registerpointed to bythe File Select Reg-
clear INDF regisEer
ister, FSR. Reading the INDF register itself, indireclly
(FSR = 0) will read 00h. Writing to the INDF register
indirectly results in a no operation (although shtus bits
maybe affected). An effective g-bitaddress is obtained
by concatenating the &bit FSR register and the IRP bit
(Status<7>) as shown