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HIP6601, HIP6603: Synchronous-Rectified Buck MOSFET Drivers Features
HIP6601, HIP6603: Synchronous-Rectified Buck MOSFET Drivers Features
CT CT
TE PRODU T PRODU
LE MEN
OBSO EPLACE 03B
ED R IP 6
Data Sheet
6 August 2004 FN4819.1
O M MEND P6601B, H
REC HI
UGATE 1 8 PHASE
Ordering Information
BOOT 2 7 PVCC
TEMP. RANGE
PART NUMBER (oC) PACKAGE PKG. NO. PWM 3 6 VCC
Block Diagram
PVCC BOOT
UGATE
VCC
PHASE
+5V SHOOT- † VCC FOR HIP6601
THROUGH
PVCC FOR HIP6603
10K PROTECTION
PWM †
CONTROL
LOGIC
LGATE
10K
GND
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright Intersil Americas Inc. 2000, 2004. All Rights Reserved
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HIP6601, HIP6603
Typical Application
+12V
+5V
BOOT
PVCC UGATE
VCC
DRIVE PHASE
PWM HIP6601
LGATE
+12V
+5V +5V
BOOT +VCORE
VFB COMP
PVCC UGATE
VCC VCC
PWM1
VSEN PWM DRIVE PHASE
PWM2
HIP6601
PGOOD PWM3
LGATE
MAIN
CONTROL
VID HIP6301
ISEN1
ISEN2
+12V
FS ISEN3
GND +5V
BOOT
PVCC UGATE
VCC
DRIVE PHASE
PWM HIP6601
LGATE
2
HIP6601, HIP6603
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
3
HIP6601, HIP6603
Timing Diagram
PWM
TPDHUGATE
TPDLUGATE
TRUGATE
TFUGATE
UGATE
LGATE
TRLGATE
TFLGATE
TPDLLGATE TPDHLGATE
4
HIP6601, HIP6603
A falling transition on PWM indicates the turn-off of the upper The bootstrap capacitor must have a maximum voltage
MOSFET and the turn-on of the lower MOSFET. A short rating above VCC + 5V. The bootstrap capacitor can be
propagation delay [TPDLUGATE] is encountered before the chosen from the following equation:
upper gate begins to fall [TFUGATE]. Again, the adaptive
Q GATE
shoot-through circuitry determines the lower gate delay time, C BOOT ≥ ------------------------
∆V BOOT
TPDHLGATE. The PHASE voltage is monitored and the lower
gate is allowed to rise after PHASE drops below 0.5V. The
lower gate then rises [TRLGATE], turning on the lower Where QGATE is the amount of gate charge required to fully
MOSFET. charge the gate of the upper MOSFET. The ∆VBOOT term is
defined as the allowable droop in the rail of the upper drive.
Three-State PWM Input
As an example, suppose a HUF76139 is chosen as the
A unique feature of the HIP660X drivers is the addition of a
upper MOSFET. The gate charge, QGATE , from the data
shutdown window to the PWM input. If the PWM signal
sheet is 65nC for a 10V upper gate drive. We will assume a
enters and remains within the shutdown window for a set
200mV droop in drive voltage over the PWM cycle. We find
holdoff time, the output drivers are disabled and both
that a bootstrap capacitance of at least 0.325µF is required.
MOSFET gates are pulled and held low. The shutdown state
The next larger standard value capacitance is 0.33µF.
is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling In applications which require down conversion from +12V or
thresholds outlined in the ELECTRICAL SPECIFICATIONS higher and PVCC is connected to a +12V source, a boot
determine when the lower and upper gates are enabled. resistor in series with the boot capacitor is required. The
increased power density of these designs tend to lead to
Adaptive Shoot-Through Protection increased ringing on the BOOT and PHASE nodes, due to
Both drivers incorporate adaptive shoot-through protection faster switching of larger currents across given circuit
to prevent upper and lower MOSFETs from conducting parasitic elements. The addition of the boot resistor allows
simultaneously and shorting the input supply. This is for tuning of the circuit until the peak ringing on BOOT is
accomplished by ensuring the falling gate has turned off one below 29V from BOOT to GND and 17V from BOOT to VCC.
MOSFET before the other is allowed to rise. A boot resistor value of 5Ω typically meets this criteria.
During turn-off of the lower MOSFET, the LGATE voltage is In some applications, a well tuned boot resistor reduces the
monitored until it reaches a 1.0V threshold, at which time the ringing on the BOOT pin, but the PHASE to GND peak
UGATE is released to rise. Adaptive shoot-through circuitry ringing exceeds 17V. A gate resistor placed in the UGATE
monitors the PHASE voltage during UGATE turn-off. Once trace between the controller and upper MOSGET gate is
PHASE has dropped below a threshold of 0.5V, the LGATE recommended to reduce the ringing on the PHASE node by
is allowed to rise. PHASE continues to be monitored during slowing down the upper MOSFET turn-on. A gate resistor
the lower gate rise time. If the PHASE voltage exceeds the value between 2Ω to 10Ω typically reduces the PHASE to
0.5V threshold during this period and remains high for longer GND peak ringing below 17V.
than 2µs, the LGATE transitions low. Both upper and lower
gates are then held low until the next rising edge of the PWM Gate Drive Voltage Versatility
signal. The HIP6601 and HIP6603 provide the user total flexibility in
choosing the gate drive voltage. The HIP6601 lower gate
Power-On Reset (POR) Function drive is fixed to VCC [+12V], but the upper drive rail can
During initial startup, the VCC voltage rise is monitored and range from 12V down to 5V depending on what voltage is
gate drives are held low until a typical VCC rising threshold applied to PVCC. The HIP6603 ties the upper and lower
of 9.9V is reached. Once the rising VCC threshold is drive rails together. Simply applying a voltage from 5V up to
exceeded, the PWM input signal takes control of the gate 12V on PVCC will set both driver rail voltages.
drives. If VCC drops below a typical VCC falling threshold of
9.1V during operation, then both gate drives are again held Power Dissipation
low. This condition persists until the VCC voltage exceeds Package power dissipation is mainly a function of the
the VCC rising threshold. switching frequency and total gate charge of the selected
MOSFETs. Calculating the power dissipation in the driver for
Internal Bootstrap Device a desired application is critical to ensuring safe operation.
The HIP6601 and HIP6603 drivers feature an internal Exceeding the maximum allowable power dissipation level
bootstrap device. Simply adding an external capacitor will push the IC beyond the maximum recommended
across the BOOT and PHASE pins completes the bootstrap operating junction temperature of 125oC. The maximum
circuit. allowable IC power dissipation for the SO8 package is
approximately 800mW. When designing the driver into an
application, it is recommended that the following calculation
5
HIP6601, HIP6603
BOOT
where fsw is the switching frequency of the PWM signal. VU PVCC
2N7002
and VL represent the upper and lower gate rail voltage. QU 0.15µF
UGATE
and QL is the upper and lower gate charge determined by CU
HIP660X
PHASE
MOSFET selection and any external capacitance added to VCC
the gate pins. The IDDQ VCC product is the quiescent power 0.15µF
PWM LGATE
of the driver and is typically 30mW. 100kΩ
2N7002
The power dissipation approximation is a result of power CL
GND
transferred to and from the upper and lower gates. But, the
internal bootstrap device also dissipates power on-chip
during the refresh cycle. Expressing this power in terms of 1000
the upper MOSFET total gate charge is explained below. PVCC = VCC = 12V
POWER (mW)
GND. While the bootstrap device conducts, a current path is
600
formed that refreshes the bootstrap capacitor. Since the
upper gate is driving a MOSFET, the charge removed from
the bootstrap capacitor is equivalent to the total gate charge 400
CU = CL = 1nF
of the MOSFET. Therefore, the refresh power required by CU = CL = 2nF
the bootstrap capacitor is equivalent to the power used to 200
charge the gate capacitance of the MOSFET. CU = CL = 4nF
CU = CL = 5nF
1 1
P REFRESH = --- f SW Q V = --- f SW Q V
2 LOSS PVCC 2 U U
0 500 1000 1500 2000
FREQUENCY (kHz)
where QLOSS is the total charge removed from the bootstrap
capacitor and provided to the upper gate load. FIGURE 1. POWER DISSIPATION vs FREQUENCY
The 1.05 factor is a correction factor derived from the
1000
following characterization. The base circuit for characterizing PVCC = VCC = 12V
the drivers for different loading profiles and frequencies is
provided. CU and CL are the upper and lower gate load 800
CU = CL = 3nF
capacitors. Decoupling capacitors [0.15µF] are added to the
POWER (mW)
Figure 2 shows the dissipation in the driver with 3nF loading 0 500 1000 1500 2000
on both gates and each individually. Note the higher upper FREQUENCY (kHz)
gate power dissipation which is due to the bootstrap device
FIGURE 2. 3nF LOADING PROFILE
refresh cycle. Again PVCC and VCC are tied together and to
a +12V supply. The impact of loading on power dissipation is shown in
Figure 3. Frequency is held constant while the gate
capacitors are varied from 1nF to 5nF. VCC and PVCC are
tied together and to a +12V supply. Figures 4 through 6
show the same characterization for the HIP6603 with a +5V
supply on PVCC and VCC tied to a +12V supply.
6
HIP6601, HIP6603
Since both upper and lower gate capacitance can vary, Figure 7 shows dissipation curves versus lower gate capacitance with
upper gate capacitance held constant at three different values. These curves apply only to the HIP6601 due to power supply
configuration.
600 400
FREQUENCY = 800kHz PVCC = VCC = 12V PVCC = 5V VCC = 12V
500 320
CU = CL = 5nF
CU = CL = 4nF
POWER (mW)
POWER (mW)
400 240
FREQUENCY = 500kHz CU = CL = 3nF
300 160
CU = CL = 2nF
200 80 CU = CL = 1nF
FREQUENCY = 200kHz
100
1.0 2.0 3.0 4.0 5.0 0 500 1000 1500 2000
GATE CAPACITANCE (CU = CL), (nF) FREQUENCY (kHz)
300 250
PVCC = 5V VCC = 12V PVCC = 5V VCC = 12V
240 200
CU = CL = 3nF
FREQUENCY = 800kHz
POWER (mW)
POWER (mW)
120 100
FREQUENCY = 500kHz
60 CL = 1nF 50
FREQUENCY = 200kHz
0
0 500 1000 1500 2000 1.0 2.0 3.0 4.0 5.0
FREQUENCY (kHz) GATE CAPACITANCE (CU = CL), (nF)
FIGURE 5. 3nF LOADING PROFILE (HIP6603) FIGURE 6. VARIABLE LOADING PROFILE (HIP6603)
400
CU = 5nF PVCC = 5V VCC = 12V
350
CU = 3nF
POWER (mW)
300
200
CU = 1nF
150
100
1.0 2.0 3.0 4.0 5.0
FREQUENCY (kHz)
FIGURE 7. POWER DISSIPATION vs LOADING (HIP6601)
7
HIP6601, HIP6603
N
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
INDEX
AREA H 0.25(0.010) M B M PACKAGE
E
INCHES MILLIMETERS
-B- SYMBOL MIN MAX MIN MAX NOTES
A 0.0532 0.0688 1.35 1.75 -
1 2 3
L A1 0.0040 0.0098 0.10 0.25 -
-C-
E 0.1497 0.1574 3.80 4.00 4
µα e 0.050 BSC 1.27 BSC -
e A1
C H 0.2284 0.2440 5.80 6.20 -
B 0.10(0.004) h 0.0099 0.0196 0.25 0.50 5
0.25(0.010) M C A M B S L 0.016 0.050 0.40 1.27 6
N 8 8 7
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of α 0o 8o 0o 8o -
Publication Number 95. Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
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