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EE124 Lecture 4 MOSFET Models Feb 5 Spring 2020 Annotated PDF
EE124 Lecture 4 MOSFET Models Feb 5 Spring 2020 Annotated PDF
EE124 Lecture 4 MOSFET Models Feb 5 Spring 2020 Annotated PDF
Electronic Design II
(EE124‐01) Lecture 4
HIU‐YUNG WONG
FEB. 5, 2020
hiuyung.wong@sjsu.edu, Office: ENG363
http://www.sjsu.edu/people/hiuyung.wong/index.html
SJSU, EE124‐01 SPRING 2020, HIU YUNG WONG 1
Outline
MOSFETs Physics
MOSFETs Models
SJSU, EE124‐01 SPRING 2020, HIU YUNG WONG 2
1
2/5/2020
Announcement
1. Assignment 1 posted due on Feb 2/13.
2. Lab 1 report due this week. Make sure you know the grading criteria. Avoid the “zero score”
mistakes. Ask me or TA if you have any doubt.
SJSU, EE124‐01 SPRING 2020, HIU YUNG WONG 3
Article of the Day
Rohm and STMicroelectronics recently signed a multi‐year agreement
under which SiCrystal (part of Rohm Group) will provide over $120
million of 150mm SiC wafers to STMicroelectronics. SiCrystal will
supply ST with monocrystalline silicon carbide wafer substrates
They are the main wide bandgap (WBD) semiconductor
materials. SiC is able to withstand substantially higher voltages,
up to ten times higher than typical silicon. This means fewer
series components to be used in high‐voltage electronics SiC‐SBDs are increasingly applied to power
applications, reducing complexity and system costs. factor correctors (PFC) circuits and secondary
side bridge rectifiers in switching mode power
supplies. The portfolio of Rohm SiC‐SBDs
SiC SBDs (Schottky barrier diode) are already replacing silicon in includes 600V and 1,200V modules, with an
the semiconductor industry amperage rating range from 5A to 40A.
SJSU, EE124‐01 SPRING 2020, HIU YUNG WONG 4
2
2/5/2020
What did we learn in the last lecture?
OpAmp Non‐ideality
1. Offset Voltage
2. Input bias current
3. Speed Limitation
◦ Finite Bandwidth
◦ Slew Rate
Vout
s A0s
Vin1 Vin 2 1
1
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Nonideality 3: Speed Limitation
V out
s A 0 s
Modeling V in 1 V in 2 1
1
What is the pole?
What is the unity‐gain bandwidth?
Due to internal capacitances, the gain of op amps begins to roll off.
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3
2/5/2020
Slew Rate (response to large signal) of Op Amp
What is slew rate?
Why?
The same as bandwidth?
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Comparison of Settling with and without Slew Rate
As it can be seen, the settling speed is faster without slew
rate (as determined by the closed‐loop time constant).
Also can you draw the response for no SR limit nor BW limit
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2/5/2020
Slew Rate Limit on Sinusoidal Signals
dVout R
V0 1 1 cos t
dt R2
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Maximum Frequency Limited By Slew Rate
V max V min V V min
Vout sin t max
2 2
SR
FP What is the difference between maximum frequency limited by SR
Vmax Vmin and limited by bandwidth?
2
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2/5/2020
Nonideality 4: Output Resistance
R out
A0
v out R R1
1 What’s bad?
v in R 2 1 R out A R1
0
Equivalent Model:
R2 R2
v out R A0
1 Inverting Amplifier
v in R 2 1 A R1 with finite gain
0 (Rout=0)
R2
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Fabrication of 3D Transistor (FinFET) by Intel.
Physics of MOS https://www.youtube.com/watch?v=d9SWNLZvA8g
Transistors
Chapter 6 You may also watch this 10‐min video about Semiconductor Fab by GlobalFoundries
https://www.youtube.com/watch?v=UvluuAIiA50
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6
2/5/2020
Digital vs. Analog vs. RF (Voltage Range)
Digital Analog RF
V(y)
VOH f
V(y)=V(x)
VM
VOL
• Small Signal • Large Signal, large or full swing
• Large Signal, Full Swing
• Linearization of the circuit • Non‐linearity is utilized
• Non‐linear equations
• Map Logic Levels (0, 1) • f(ax+by) = af(x) + bf(y)
to Voltage Domain
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Transistor = Transfer Resistor
Transfer Resistor: a resistor which can amplifier electrical signals as they are transferred through
it from the input to the output terminals (see Nobel Prize Website)
A Switch! Example: MOS Transistor
For digital circuit
VGS VT |V GS|
Ron
S D
In analog circuit, this is not just a switch but also a Voltage Controlled Current Source
Control voltage is VG
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2/5/2020
Structure and Symbol of MOSFET
What is source? What is drain?
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90nm Technology
The gate is formed by polysilicon, and the insulator by Silicon dioxide.
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2/5/2020
State‐of‐the‐Art Technology (10nm FinFET)
Why do we metal gate?
Metal Gate
High‐k Dielectric Why high‐k dielectric?
Do we need FinFET for analog?
Do we need to deal with it?
Source: wikichip.org
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