1.

To perform multiplication on floating point number in the computer

rearranges the number in the form m x re
2. _ Data Dependency _______ conflicts arises when an instruction depends
on the result of previous instruction

3. The data transfer instructions in RISC is limited to _ Load ____ and store
4. The memory hierarchy is divided into ____5_____ types
5. The DMA transfers are performed by a control circuit called as
DMA controller
6. The technique whereby the DMA controller steals the access cycles of the
processor to operate is called Cycle stealing
7. The stack segment of 8086 has maximum __64 k bytes
8. The interrupt vector table has __256______ interrupt types

9. The return address from the interrupt-service routine is stored on the

Processor stack
10. The correspondence between the main memory blocks and those in the
cache is given by Mapping function
11.ISR stands for __ Interrupt Service Routine

12. When IF = ___1___ the hardware interrupts are

unmasked/masked.
13. The fastest data access is provided using __ Registers
__
14. Pipeling is a technique of decomposing a sequential
process into sub operations, with each process being executed in a
special dedicated segment that operates concurrently with all other
segments.
15.Daisy chain connection mechanism provides means to achieve Sharing
16. MISD stands for Multiple Instruction Single Data Stream __

17. The __ Bus __ is a combination of data and

control lines.
18.Booth’s Algorithm __ is the most powerful algorithm for solving
signed complement multiplication.

19. Auxiliary memory is also known as secondary memory.

20. The effectiveness of the cache memory is based on the property of _
Locality of reference

21. The controller is connected to the ___ System BUS_

22. The DMA controller has __3_____ registers.

23. The DMA transfers are performed by a control circuit called as DMA
controller .

24 The minimum time delay between two successive memory read operations
is Cycle time .

25. _____Memory Cell Time_____ is the bottleneck, when it comes computer

performance.

26. VLSI stands for __ Very Large Scale Integration.

27. A 16 X 8 Organisation of memory cells, can store upto _128bits____.

28.The primary function of the BUS is to connect the various devices to the
cpu

29.  In synchronous BUS, the devices get the timing signals from _ A common
clock line

30. The delays caused in the switching of the timing signals is due to _
Propagation delay_________.

31. The classification of BUSes into synchronous and asynchronous is based on

the Timing of data transfers.

32. MRDC stands for _ Memory Ready Command.

33. The transmission on the asynchronous BUS is also called Hand-Shake

transmission.

34. The master indicates that the address is loaded onto the BUS, by activating
__ MSYN ___ signal.

35. The standard SRAM chips are costly as 6 transistor per chip.

36. The drawback of building a large memory with DRAM is _ The Slow speed of
operation.

37 . The next level of memory hierarchy after the L2 cache is __ Register.

38. The secondary memory is the slowest memory device.

39. The memory blocks are mapped on to the cache with the help of Mapping
functions .

40. During a write operation if the required block is not present in the cache
then _ Write miss _____ occurs.