Cadence Design Systems, Inc.

IO Planning in EDI Systems

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Table of Contents
1. TYPES OF IO PADS ...................................................... 3
2. TYPES OF IO PLACEMENT TECHNIQUES: ............................... 4
3. UNDERSTANDING IO ASSIGNMENT FILE ............................... 6
4. I/O ROW BASED PAD PLACEMENT FLOW .............................. 9
5. RELATED SOLUTION: .................................................. 13

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1. Types of IO Pads

• Output Pads

The gates of these transistors present a large gate load to anything trying
to drive them. An intermediate sized inverter buffer is usually provided as
part of the pad driver circuitry to drive the pad drivers while presenting a
smaller gate load to the internal circuitry. Because of the large currents
flowing in the pad drivers, they are much more susceptible to latch up than
smaller transistors. Guard rings are used around these transistors.

• Input Pads

The input buffer usually has very low input Voltage to accommodate
TTL(Transistor to Transistor Logic) logic levels (0.8V, 2.0V). The input pad
and buffer present a capacitive load to the outside world. This is good for
preventing any DC load current.

• Bidirectional Pads

The Bidirectional pads are the combination of both input and output pad. It
needs tri-state driver at the output of the pad that can be use to enable the
signal direction.

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 PAD

En
Din
Dout

2. Types of IO placement Techniques

Inline IO Placement
o Pads are placed next to each other, with the corresponding bond
pads lined up against each other having a small gap in between.
o Minimum pitch is determined by foundry/vendor and is
technology dependent.

Staggered IO Placement
o Useful technique if design is “Pad Limited”.
o Designer needs to place an inner and outer bond pad alternately.
o From the placement shown, it is obvious that a larger number of
pads can be accommodated in the design, but a big disadvantage
of this type of placement is that the overall height of the pad
structure increases significantly.

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CUP ( Circuit-Under-Pad) IO Placement
o Circuit-Under-Pad technology violates the rule of conventional
layout and arranges the bond pad right over the pad circuitry.
o This technique ensures that no extra space is consumed on the
die and be implemented with either the in-line or staggered IO
placement techniques.
o Extra care needs to be exercised while implementing this
technology so as to ensure that the circuit under the bond pad
does not suffer any mechanical stress which could be fatal to the
chips operation.

Flip Chip IO Placement

o Flip Chip type packaging is simply a direct connection of a flipped
electrical component onto a substrate, carrier, or circuit board by
means of conductive bumps instead of the conventional wire-
bond.

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 o In the Flip chip methodology, I/O bumps and driver cells may be
placed in the peripheral or core area. Note, the large octagonal
area I/O bumps overlaying placed cells in the core area. No chip
area benefit for small chips
o Full bump array redistribution is very difficult once it was placed
in design.

3. Understanding the IO Assignment File

The I/O assignment file defines the rules that determine how the I/O
instances (pad cells and area I/O), I/O pins, bumps, and bump arrays are
organized. The file is rule-based to specify exact location, global spacing,
individual spacing, skip, offset, keep clear, and corner information. You can
specify detailed rules to control the locations or you can specify minimal or
no rules to allow Encounter to determine the locations automatically.
I/O assignment files supports:
If you do not specify an I/O assignment file when you import a design,
I/Os are assigned randomly.
If you do not specify an I/O assignment file, but you want to set I/O
pin or pad placement, use a DEF file. Load the DEF file after importing
the design, and then save the floorplan.
You can also save the I/O file to write a sequence file for rule-based
work.
If you provide an I/O assignment file, you are not required to specify
the exact location of all I/O pads. You can specify the I/O row name to
place the I/O pads in a specific I/O row.

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 If you do not provide offset values, Encounter spaces the I/O pads
evenly along the specified row. The spacing between the corners and
adjacent pads is the same as the spacing between the other pads.
I/O assignment flows:
Manual I/O Assignment file
Below example shows the statements in a sample I/O assignment file
for I/O pads

version = 3 # Beginning of a new I/O format.

io_order = clockwise #Order of the I/O pads and pins.
total_edge = 4 #Number of edges for the rectilinear block
design.
space = 1.06 # Spacing, in micros, between the pad being
defined and the previously defined pad.
(inst
name = IOPADS_INST/pad1 W
offset = 235.0000 # Offset in umeters. The offset of a pad is the
offset from the die boundary, based on the
order direction.
orientation = R0 # Orientation of the I/O.
place_status = fixed # Placement status of the I/O pad.
)
(inst
name = IOPADS_INST/pad2 W
offset = 296.1250
orientation = R0
place_status = fixed
)
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Rule-Based I/O Assignment File flow
In a rule based I/O Assignment file create an I/O assignment file
automatically from EDI system as per the flow below
o Import the design.
o After reviewing the I/O pads, choose Design – Save – IO File.
o On the Save IO File form, select sequence.
o Edit the new file for re-importing, or use the loadIoFile command.
o Save the floorplan to a file.
This is most recommended way of using the I/O file. Once you got the
I/O file you can modify anything (sequence, spacing, offset) of any
pad and reload it back.

Area I/O Placement

Before doing area I/O placement, you must specify CLASS PAD
AREAIO in a LEF file. Additionally, a SITE or region must be defined for
the placeAIO command to place the CLASS PAD AREAIO macro in the
required location. The SITE must be referenced in the AREAIO macro.
The following example shows a SITE definition followed by a CLASS
PAD AREAIO macro which refers to the SITE.

SITE IO CLASS PAD ;

SIZE 210 BY 100.8 ;
END IO

MACRO INBUF
CLASS PAD AREAIO ;
FOREIGN INBUF 0.00 0.00 ;
ORIGIN 0 0 ;
SIZE 210 BY 100.8 ;
SYMMETRY X Y R90 ;
SITE 10 ;
PIN PAD
DIRECTION INPUT ;
USE SIGNAL ;
PORT ;
LAYER M6 ;
RECT 95.0 40.0 115.0 60.0 ;
END
END PAD
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 o Defining BUMP CELL in LEF
It is important to define the bumps in the LEF file so that when
the Area IO pads are connecting to the bumps it knows the
connection. Below is the example of BUMP cell macro.
MACRO BUMPCELL
CLASS COVER BUMP ;
ORIGIN 0 0 ;
SIZE 80.0 BY 80.0 ;
SYMMETRY X Y ;
PIN PAD
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M6 ;
RECT 0.0 0.0 80.0 80.0 ;
END
END PAD
END BUMPCELL

o Defining BUMP CELL Placement status

BUMP cell placement status can defined as FIXED | COVER for the
bump object in design.

4. I/O Row based Pad Placement Flow

Many cases designs contain multiple-height I/O pads or asymmetric I/O
rings, i.e single I/O ring on one side and double rings or no rings on the
other side, or no rings on part of a certain side. For such designs, the
Encounter enables you to create, edit, save, and restore I/O rows and
perform pad placement based on the I/O rows. I/O rows can be created
anywhere in the die - within the core or in the periphery and use the I/O
row flow for, pad and area I/Os.

Requirements
LEF technology file should contain I/O SITE definition.
Each I/O cell LEF must have correct CLASS and SITE type specified.
If the design contains multiple I/O SITES, the gap between the core
boundary and the die boundary must be greater than the biggest I/O
SITE.

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I/O Row Flow

• Import the design

GUI menu “Design->Import Design”, or Tcl command loadConfig

• Initialize Floorplan
GUI menu “Floorplan->Specify Floorplan”, or Tcl command floorplan

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By default, one I/O row is created on each side of the chip, between the
core boundary and the die boundary. If the design references LEF libraries
containing multi height I/O sites, then rows are created for each side based
on the number of I/O sites used in the design.

• Creating I/O row

GUI menu “Floorplan -> Edit Floorplan -> Create I/O Row form”

• Dual I/O row

GUI menu “Floorplan->Edit Floorplan->IO Row->Edit”

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• Edit(move/stretch/rotate/flip) I/O Pad Placement
Change pad side, location, orientation interactively from GUI or through editing IO file,
e.g. saveIoFile-> then edit manually -> reload using loadIoFile command

Text command for Editing I/O Pad

createIoRow: Creates an IO Row

flipInst: Flips the selected I/O row through x or y axis
fplanFlipOrRotateInstance: Flips or rotates the selected
instances
stretchRows: Stretches the selected I/O rows.
moveSelObj: Moves the selected row to a specific location
deleteRow: Deletes the selected I/O row
snapFPlanIO: Snaps the I/O pads onto the correct side of the
I/O rows
spaceIoInst: Spaces the selected I/O pads on the I/O rows

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• Adding I/O Corner pads, IO fillers pad

5. Related Solution
How does Encounter determine the Area IO placement location?
Placement in IORow & IOInst in the IO assignment file.
What are the prerequisites for preview to write out an IO Constraints file?
How to place stagger IO in First Encounter?
How can I manually change the number of power & ground pads?
Placement in IO rows overlaps Area IO cells.

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