UNIT III

DESIGN LAYOUT
By
Dr. Bellamkonda Saidulu

UNIT – III CIRCUIT DESIGN PROCESSES

 INTRODUCTION

• Objectives:
– To know MOS layers
– To understand the stick diagrams
– To learn design rules
– To understand layout and symbolic diagrams

• Outcome:
– At the end of this, will be able draw the stick
diagram, layout and symbolic diagram for simple
MOS circuits

UNIT – III CIRCUIT DESIGN PROCESSES

 MOS LAYERS

UNIT – III CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

VLSI design aims to translate circuit concepts

onto silicon.

• Stick diagrams convey layer information

through color codes (or monochrome
encoding).
• Acts as an interface between symbolic circuit
and the actual layout.
UNIT – III CIRCUIT DESIGN PROCESSES
 STICK DIAGRAMS

• Does show all components/vias.

– Via is used to connect higher level metals from metal connection

• It shows relative placement of components.

• Goes one step closer to the layout
• Helps plan the layout and routing

A stick diagram is a cartoon of a layout.

UNIT – III CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

• Does not show

– Exact placement of components
– Transistor sizes
– Wire lengths, wire widths, tub boundaries
– Any other low level details such as
parasitics

UNIT – III CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Stick Diagrams – Notations

Metal 1
poly

ndiff

pdiff
Can also draw
in shades of
gray/line style.
Buried Contact

Contact Cut
UNIT – III CIRCUIT DESIGN PROCESSES
STICK DIAGRAMS

NMOS ENCODING
UNIT – III CIRCUIT DESIGN PROCESSES
STICK DIAGRAMS

CMOS ENCODING
UNIT – III CIRCUIT DESIGN PROCESSES
 STICK DIAGRAMS

Stick Diagrams – Some Rules

Rule 1:
When two or more ‘sticks’ of the same type cross or touch
each other that represents electrical contact.

UNIT – III CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Stick Diagrams – Some Rules

Rule 2:
When two or more ‘sticks’ of different type cross or touch each
other there is no electrical contact.
(If electrical contact is needed we have to show the connection
explicitly)

UNIT – III CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Stick Diagrams – Some Rules

Rule 3:
When a poly crosses diffusion it represents a transistor.

Note: If a contact is shown then it is not a transistor.

UNIT – III CIRCUIT DESIGN PROCESSES
 STICK DIAGRAMS

Stick Diagrams – Some Rules

Rule 4:
In CMOS a demarcation line is drawn to avoid touching of p-diff
with n-diff. All PMOS must lie on one side of the line and all
NMOS will have to be on the other side.

UNIT – III CIRCUIT DESIGN PROCESSES

 Try Once

UNIT – III CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Examples of Stick Diagrams

Vdd = 5V Vdd = 5V

pMOS
Vin Vout Vin Vout
nMOS

UNIT – III CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Examples of Stick Diagrams

VDD
VDD
X

X
x x x
x X

Gnd Gnd

UNIT – III CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Examples of Stick Diagrams

UNIT – III CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Examples of Stick Diagrams

* Note the depletion mode device

Vdd = 5V

Vout
Vin

UNIT – III CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Examples of Stick Diagrams

UNIT – III CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Examples of Stick Diagrams

UNIT – III CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Examples of Stick Diagrams

NOR gate and NAND using NMOS LOGIC

UNIT – III CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Examples of Stick Diagrams

f= [(xy) +z]’ using NMOS LOGIC

UNIT – III CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Examples of Stick Diagrams

UNIT – III CIRCUIT DESIGN PROCESSES

 LAYOUT DESIGN RULES
❑ Layout design rules describe how small features can be and how
closely they can be packed in a particular manufacturing process.
❑ Industrial design rules are usually specified in microns(μ).
❑ Rules are expressed interms of a single parameter, ‘λ’, which
characterizes the resolution of the process.
❑ ‘λ’ is generally half of the minimum drawn transistor channel
length.(Ex: Process(Lmin) is 180nm(feature size), then λ=90nm)
❑ This length is the distance between the source and drain of a
transistor and is set by the minimum width of a polysilicon wire.
❑ Designers often describe a process by its feature size.
❑ Feature size refers to minimum transistor length, so ‘λ’ is half
the feature size. Or feature size of any process is ‘2λ’.
UNIT – III CIRCUIT DESIGN PROCESSES
 LAYOUT DESIGN RULES
Design rules specify to the designer certain geometric constraints on the layout art. So that
the patterns on the processed wafer will preserve the topology and geometry of the
designs.
The rules are defined in terms of feature sizes (widths), separations, and overlaps.
❑ Metal and diffusion have and spacing of ‘4 λ’.
❑ Contacts are 2 λ x 2 λ and must minimum width be surrounded by ‘1 λ’ on the
layers above and below.
❑ Polysilicon uses a width of ‘2 λ’.
❑ Polysilicon overlaps diffusion by ‘2 λ’ where a transistor is desired and has a
spacing of ‘1 λ’ away, where no transistor is desired.
❑ Polysilicon and contacts have a spacing of ‘3 λ’ from other polysilicon or
contacts.
❑ N-well surrounds pMOS transistors by ‘6 λ’ and avoids nMOS transistors
by ‘6 λ’.

UNIT – III CIRCUIT DESIGN PROCESSES

LAYERS WITH LAYOUT DESIGN RULES

UNIT – III CIRCUIT DESIGN PROCESSES

 DESIGN RULES
Thinox

Metal 1
n-diffusion p-diffusion
3λ
2λ
3λ 3λ
2λ 3λ

Metal 2
2λ
4λ
2λ
2λ 4λ
Polysilicon
4λ

UNIT – III CIRCUIT DESIGN PROCESSES

 DESIGN RULES

Problems in Manufacturing

• Variations in threshold voltage

– oxide thickness
– ion implantation
– poly variations
• Diffusion - changes in doping (variation in R, C)
• Poly, metal variations in height and width
• Shorts and opens

UNIT – III CIRCUIT DESIGN PROCESSES

 DESIGN RULES
• PolySi – PolySi space 2
• Metal - Metal space 2
• Diffusion – Diffusion space 3 To avoid the possibility of
their associated regions overlapping and conducting
current

Metal

Diffusion

  Polysilicon

UNIT – III CIRCUIT DESIGN PROCESSES

 DESIGN RULES
• Diffusion – PolySi space  To prevent the lines overlapping
to form unwanted capacitor
• Metal lines can pass over both diffusion and polySi without
electrical effect. Where no separation is specified, metal
lines can overlap or cross.

Metal

Diffusion

UNIT – III CIRCUIT DESIGN PROCESSES

 DESIGN RULES
• Metal lines can pass over both diffusion and polySi without
electrical effect
• It is recommended practice to leave  between a metal
edge and a polySi or diffusion line to which it is not
electrically connected

Metal


Polysilicon

UNIT – III CIRCUIT DESIGN PROCESSES

 DESIGN RULES

• Recall

– poly-poly spacing 2

– diff-diff spacing 3

– metal-metal spacing 2

– diff-poly spacing 

UNIT – III CIRCUIT DESIGN PROCESSES

 DESIGN RULES
Butting Contact
The gate and source of a depletion device can be connected by a
method known as butting contact. Here metal makes contact to
both the source of the depletion transistor and to the polySi gate.

UNIT – III CIRCUIT DESIGN PROCESSES

 DESIGN RULES

• Wells must surround transistors by 6 

– Implies 12  between opposite transistorflavors
– Leaves room for one wire track

UNIT – III CIRCUIT DESIGN PROCESSES

 DESIGN RULES

• A wiring track is the space required for a wire

– 4  width, 4  spacing from neighbour = 8  pitch
• Transistors also consume one wiring track

UNIT – III CIRCUIT DESIGN PROCESSES

 LAYOUTS
Top view of the FET pattern

NMOS PMOS

n-well

n+ n+ p+ p+

S D

S D
S D
G

UNIT – III CIRCUIT DESIGN PROCESSES

 LAYOUTS
General Layout Geometry
VDD

Individual
Shared Gates Shared diffusions
Transistors
(Source/Drain)

Gnd
UNIT – III CIRCUIT DESIGN PROCESSES
 LAYOUTS
Metal Interconnect Layers
• Metal layers are electrically isolated from each other
• Electrical contact between adjacent conducting layers requires contact cuts
and vias
Ox3
Via
Metal2

Active Ox2
contact
Metal1
Ox1

n+ n+ n+ n+

p-substrate

UNIT – III CIRCUIT DESIGN PROCESSES

 LAYOUTS
Designing MOS Arrays
A B C

x y

A B C

x
UNIT – III CIRCUIT DESIGN PROCESSES
 Can You Guess Name of design……?????????

x x
A B
A B

X X X
y
y

X X
A B
A B
X X

y y
UNIT – III CIRCUIT DESIGN PROCESSES
 LAYOUTS
The CMOS NOT Gate
Contact
Cut
Vp Vp
X n-well

X
x x
X
x
X
Gnd

Gnd

UNIT – III CIRCUIT DESIGN PROCESSES

Can You Guess Name of design……?????????

UNIT – III CIRCUIT DESIGN PROCESSES

 Can You Guess Name of design……?????????

Stick diagram Layout diagram

UNIT – III CIRCUIT DESIGN PROCESSES

Can You Guess Name of design……?????????

UNIT – III CIRCUIT DESIGN PROCESSES

 LAYOUTS
The 3-Input NAND Gate
3-input NAND

UNIT – III CIRCUIT DESIGN PROCESSES

 LAYOUTS
Transmission Gate

UNIT – III CIRCUIT DESIGN PROCESSES

Can You Guess Name of design……?????????

UNIT – III CIRCUIT DESIGN PROCESSES

Can You Guess Name of design……?????????

UNIT – III CIRCUIT DESIGN PROCESSES

The 3-D View of a IC Design

UNIT – III CIRCUIT DESIGN PROCESSES

 Interconnects
The wires used to connect the circuit components(R,C)
and transistors together are called interconnect and
play a major role in the performance of modern
systems.

The wires have width w, length L, thickness t, and

spacing of s from their neighbors and have a dielectric
of height h between them and the conducting layer
below.
Fig. Interconnect Geometry
The sum of width and spacing is called the wire pitch.

The thickness to width ratio t/w is called the aspect

ratio. Wires were wide and thick and thus had low
resistance.

Interconnect increases circuit delay for two reasons

First, the wire capacitance adds loading to each gate.
Second, long wires have significant resistance that
contributes distributed RC delay.

UNIT – III CIRCUIT DESIGN PROCESSES

 Interconnects

In modern VLSI processes, transistors switch much faster.

Meanwhile, wires have become narrower, has, more
resistance to the point that in many paths the wire RC delay
exceeds gate delay.

Moreover the wires are packed very closely together and thus
a large fraction of their capacitance is to their neighbors.

When one wire switches, it tends to affect its neighbor

through capacitive coupling; this effect is called crosstalk.

UNIT – III CIRCUIT DESIGN PROCESSES

 Capacitance
An isolated wire over the substrate can be
modeled as a conductor over a ground plane.

The wire capacitance has two major

components:
1. parallel plate capacitance of the bottom of
the wire to ground and
2. fringing capacitance arising from fringing
fields along the edge of a conductor with
finite thickness.

In addition, a wire adjacent to a second wire

on the same layer can exhibit capacitance to
that neighbor.

The total capacitance of the conductor of

interest is the sum of its capacitance to
the layer above, the layer below, and the
two adjacent conductors.
UNIT – III CIRCUIT DESIGN PROCESSES
 CROSSTALK
The wires have capacitance to their adjacent
neighbors as well as to ground.

When wire A switches, it tends to bring its

neighbor B along with it on account of
capacitive coupling, also called crosstalk.

If B is supposed to switch simultaneously, this

may increase or decrease the switching delay.
If B is not supposed to switch, crosstalk causes
noise on B.

The impact of crosstalk depends on the ratio of

Cadj to the total capacitance.

for long wires crosstalk is very important.

UNIT – III CIRCUIT DESIGN PROCESSES

Microelectronic technology may be characterized in terms of several indicators,
or figures of merit. Commonly, the following are used:

• Minimum feature size

• Number of gates on one chip
• Power dissipation
• Maximum operational · frequency
• Die size
• Production cost

Many of these figures of merit can be improved by shrinking the dimensions of

transistors, interconnections and the separation between features, and by
adjusting the doping levels and supply voltages.

Scaling Models:
Commonly used Scaling models are the constant electric field and the constant
voltage scaling model.

UNIT – III CIRCUIT DESIGN PROCESSES

 SCALING MODELS AND SCALING FACTORS

Scaling is therefore an important factor, and it is essential for the designer to

understand
the implementation and the effects of scaling.

Fig. indicates the device dimensions and substrate doping level which are
associated with the scaling of a transistor.
In order to accommodate the three models, two scaling factors- 1/α and 1/β are
used.

1/α - is chosen for supply voltage VDD

and gate oxide thickness D, and
1/β is used for all other linear
dimensions, both vertical and
horizontal to the chip surface.

For the constant field model and the

constant voltage model, β = α and β
= 1 respectively are applied.

UNIT – III CIRCUIT DESIGN PROCESSES