VERILOG MINIPROJECT 2

TRAFFIC LIGHT CONTROLLER

SUBMITTED BY: SPOORTI Y BARIGIDAD
CODE

module TLC (

input wire clk,

input wire reset,

output reg [2:0] state,

output reg [3:0] count,

output reg [5:0] LEDS);

parameter S0 = 3'b000, S1 =3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100, S5 = 3'b101;

always @(posedge clk or posedge reset)

begin

if (reset == 1)

begin

state <= S0;

count <= 4'b0000;

end

else

case(state)

S0: if(count < 4'b1111)

begin

state <= S0;

count <= count + 4'b0001;

end

else

begin

state <= S1;

count <=4'b0000 ;
end

S1: if(count < 4'b0011)

begin

state <= S1;

count <= count + 4'b0001;

end

else

begin

state <= S2;

count <= 4'b0000;

end

S2: if(count < 4'b0011)

begin

state <= S2;

count <= count + 4'b0001;

end

else

begin

state <= S3;

count <= 4'b0000;

end

S3: if(count < 4'b1111)

begin

state <= S3;

count <= count + 4'b0001;

end
else

begin

state <= S4;

count <= 4'b0000;

end

S4: if(count < 4'b0011)

begin

state <= S4;

count <= count + 4'b0001;

end

else

begin

state <= S5;

count <= 4'b0000;

end

S5: if(count < 4'b0011)

begin

state <= S5;

count <= count + 4'b0001;

end

else

begin

state <= S0;

count <= 4'b0000;

end

default state <= S0;

endcase

end

always @(*)

begin

case(state)

S0: LEDS = 6'b100001;

S1: LEDS = 6'b100010;

S2: LEDS = 6'b100100;

S3: LEDS = 6'b001100;

S4: LEDS = 6'b010100;

S5: LEDS = 6'b100100;

default LEDS = 6'b100001;

endcase

end

endmodule

TESTBENCH

module testbench;

reg clk, reset;

wire [2:0] state;

wire [3:0] count;

wire [5:0] LEDS;

TLC uut (clk, reset, state, count, LEDS);

initial

begin

//Dump waves
$dumpfile("dump.vcd");

$dumpvars(1,testbench);

clk=1'b1;

forever #5 clk=~clk;

end

initial

begin

reset=1'b1;

#15;

reset=1'b0;

#1000;

$finish;

end

endmodule

SIMULATION RESULT