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Digital Video Encoder Module System: 7128MOD2: Application Note
Digital Video Encoder Module System: 7128MOD2: Application Note
Digital Video Encoder Module System: 7128MOD2: Application Note
Abstract
This application note is intended to provide application support for Philips´ Digital Video Decoders and Encoders.
It contains a description of one evaluation board as well as I²C-bus programming of the respective device.
The Digital Video Decoder converts an analog video input signal into a digital output signal. This signal can be
processed by a wide range of applications and fed to the Digital Video Encoder, which delivers analog video
signals to TV receivers or video cassette recorders.
This note gives a detailed description of the schematics and some hints how to design the PCB (Printed Circuit
Board) with mixed analog and digital signal processing.
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APPLICATION NOTE
Author:
Dietmar Speller
MPC-E, Hamburg,
Germany
Keywords
Digital Video Encoder (DENC)
SAA7128/29
SAA7138/39
SAA7120/21
SAA7126/27
I²C-bus
MultiMedia
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Summary
This application note is intended to provide application support for Philips´ Digital Video Decoders and Encoders.
It contains a description of one evaluation board as well as I²C-bus programming of the respective device.
The Digital Video Decoder converts an analog video input signal into a digital output signal. This signal can be
processed by a wide range of applications and fed to the Digital Video Encoder, which delivers analog video
signals to TV receivers or video cassette recorders.
This note gives a detailed description of the schematics and some hints how to design the PCB (Printed Circuit
Board) with mixed analog and digital signal processing.
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5. Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1 Programming tables for SAA7128/29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 Summary of Registerfunctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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1. Introduction
The Digital Video Decoder/Encoder Modules provide the basis to evaluate various Philips Digital Video Decoders
and Encoders and give the opportunity to simply insert the modules into customized applications and systems.
On the following pages the assembly and function of a Digital Video Encoder Module is shown. The module can
operate in stand alone mode (colourbar generator) as well as extension to other systems like PCI-bridges, MPEG
decoders or Video input/output systems.
The module has a socket for an I²C-bus EEPROM (e.g. PCF8582, PCF8594, PCF8598, X24164) in order to
store data for initialization and for simple control functionality operated by a (future) microcontroller module.
Software for IBM compatible personal computers enables access to all features and settings of the devices. It
handles the I²C-bus via a printer port adaptor. This adaptor and a fitting cable is part of the accessory.
This modular concept was designed to combine different video decoders with various video encoders. Some
modules (e.g. the 7128MOD2) can be configured for several devices and packages without the necessity of
having a new PCB. This could be achieved by using multiple footprints for one IC and some configurational parts.
For interfacing a 96-pin module connector is used.
The modules need a 5V analog and a 5V digital supply voltage. A respective power connector is placed at each
backend (encoder-) module whereas frontend modules are supplied via the 96-pin module connector.
If necessary, an internal voltage regulator generates the required 3.3V onboard. Alternatively it is also possible to
bypass the regulators on some encoder modules and connect 3.3V supply directly to the respective pins. You
can find a fitting power connector cable as a part of the accessory as well.
SAA7128/29 PAL/NTSC/SECAM encoder with six DACs for CVBS(CSYNC), VBS(CVBS), C(CVBS), R(Cr),
G(Y), B(Cb) (signals in brackets optionally) and a 54MHz double speed multiplexed D1 interface. It features also
a versatile fader for fading of two data streams (at double speed port MP) against each other. QFP44 package.
SAA7138/39 PAL/NTSC/SECAM encoder with six DACs for CVBS(CSYNC), VBS(CVBS), C(CVBS), R(Cr),
G(Y), B(Cb) (signals in brackets optionally) and a 54MHz double speed multiplexed D1 interface. It features also
a versatile fader for fading of two data streams (at double speed port MP or through the additional port DP) against
each other. QFP64 package.
SAA7120/21 PAL/NTSC encoder with three DACs for CVBS, Y, C. QFP44 package.
SAA7126/27 PAL/NTSC encoder with four DACs for CVBS(CSYNC, VBS), R(Cr, C), G(Y, VBS) and B(Cb,
CVBS) (signals in brackets optionally) and a 54MHz double speed multiplexed D1 interface. QFP44 package.
The digital data is fed via the 96-pin input connector. The circuits accept CCIR compatible YUV data with 720
active pixels per line in 4:2:2 multiplexed formats, for example MPEG decoded data. For interfacing an ECL - TTL
converter can be used (accessory). At a 54MHz (double speed) multiplexed D1 input port the circuits accept two
CCIR compatible CbYCr data streams for example MPEG decoded data with overlay, whereas one datastream is
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Switch RGB
RESN
Extern R active
A0 Y/C / RGB
A1 Source
A2 G
SCART
27 MHz
Y/C / CVBS
U5
U4 B CVBS1
CVBS2
CVBS0
Y
VS
RCV1
ODD Y/C
C CVBS
SAA7126/27
NEW
OLD
US
CVBS
TERMLLC_2 CVBS1
HS to RCV2
S5/O10
I²C-CON
LLCB CVBS2
TERMLLC_1
LLC_2 Filter off ||
Filter on =
XCLK
SA
LLC_1
LLCA
LLCOUT
71__MOD2 V1.0 5V
+5VD
CLKOUT I²C DGND
SAA7120/21 3,3V
SAA7126/27
SAA7128/29 +5VA
SAA7138/39
DIL20
SPARE AGND
PHILIPS MPC-E/PD
October 1997
-5VA
Fig.1 shows the location of IC’s, jumpers and connectors on the application module 7128MOD2. The function of
the used connectors is described on page 10. The function of jumpers is shown in a jumper list on page 16.
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2.2 Reset
There are two different ways to reset the device:
Using this module in conjunction with a MPC decoder module, preferably the ’Reset Not’ generated by the deco-
der should be used (JP26 = Extern). Therefore a dedicated pin exists at the VG96 input connector.
In case of a stand alone operation (e.g. colourbar generator) or in conjunction with other systems the Reset
push-button can be used (JP26 = Switch).
During reset (RESN = LOW) and after reset is released, all digital I/O stages are set to input mode, PAL-Black-
burst on CVBS, VBS and C; all analog outputs are set to high impedance. A reset forces the I²C-bus interface to
abort any running bus transfer and sets register 3A to 03H, register 61 to 06H and registers 6BH and 6EH to 00H.
All other control registers are not influenced by a reset.
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10
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Signal Specification
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VDD
CVBSOUT
CVBS0
3
JP14
P3
2 1
CVBS_CON
CVBS22 1
CVBS1
2
1
YCOUT[1..0] A
JP15
Y COUT0 1 3
Y/ C CVBS
Y COUT1
2
P4
2
JP16
1
3
17 ST RGB Gnd
Y/ C CVBS Gnd 16
2 15 ST RGB
RED 14
JP17 D²B Gnd
RGB 13
RED Gnd 12
11 D²B
1
GRN 10
RGBOUT[2..0] D²B
9
GRN Gnd 8
7 CTRL I/O
RGBOUT2
BL 6
5 L in
RGBOUT1
BL Gnd 4
3 LR Gnd
RGBOUT0
L out 2
1 R in
R out 21
GND
SCART
The figure above shows the analog output circuit with Subclick- and SCART- connector. The main CVBS line
should not be switched to both Subclick and SCART (CVBS output or CSYNC) at the same time. The SAA7128/
29 and SAA7138/39 offer additional CVBS outputs on Y and C pins as option (JP14). To enable RGB input to a
SCART TV plug, close JP16. In this case JP17 must be in position ’RGB’
SAA7120/21: This device provides no other signals than CVBS and Y/C one time so the jumper configuration is
JP14 = CVBS0 and JP17 = Y/C.
SAA7126/27: This device provides CVBS and Y/C or RGB signals at the respective connectors. For Y/C output
JP31 and JP32 must be closed.
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2.4 I²C-Bus
Two I²C-bus slave addresses are selected:
88H: LOW at pin SA
8CH: HIGH at pin SA
Systems running in a 3.3V environment probably require the same voltage for the I²C-bus. In this case, JP29
must be changed from default position to 3.3V in order to adjust the I²C supply voltage. A new Single Master
Interface with the IC 74HC9114D can be used then, it replaces the former Single Master Interface with the IC
74LS05, which is only suited for 5V. The new interface operates on the I²C-bus from 1.8V to 5V.
Please note that there are no additional pullup resistors on this board, thus supply of the I²C-bus is provided once
at the (single master-) I²C-bus interface.
On this backend module, two connectors can be used for I²C-bus control (alternative). The first one is a 6pin Mini
DIN connector with the pinning shown on the right side of Fig.3. In order to consider different existing pinnings,
the STOKO connector has a combined footprint for the standards ’Old’, ’New’ and ’US’. Please note that modules
from the Philips Application Lab. Hamburg use the norm ’NEW’ while the default configuration of the MPC
module system is ’OLD’.
COMBI-FOOTPRINT
GND
SCL SDA
GND
VCC
SDA VCC VCC
VCC SDA GND (Solder View)
GND GND SCL
SCL SCL SDA
NEW OLD US
(Top View)
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a b c
JP13
CLK2 IN (B20)
LLC2
JP13A
XCLK
LLCout
CLK OUT (B23)
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a b c
XCLK
SAA 7128/29
LLC1 SAA 7126/27
LLC_1 (B17) SAA 7120/21
shortcut
If types other than SAA7138/39 are being used,only jumper (JP13) is essential. In master mode the internal osci-
llator generates the clock at pin XCLK and jumper (JP13) is used to connect the device and external circuits via
LLC_1. The shown shortcut is done by a 0R resistor.
In slave mode this jumper must be open.
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2.7 Jumperlist
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MEMORY
MEMORY EPROM
CONTROL
H(1), V
RCV1,2
MUX
MP2
54MHz
multiplexed data
(8bit)
MP1
(2)
LLC
SAA7128/29
27MHz data
LLC
(8bit)
(1): delayed via 74 574
(2): delayed via 74 240
SAA7111A
CENTRONICS
MEMORY
MEMORY EPROM
CONTROL
H(1), V
RCV1,2
MUX
MP2
54MHz
multiplexed data
(8bit)
MP1
(2)
LLC
SAA7128/29
MPEG H, V
decoded data LLC
(1): delayed via 74 574
(2): delayed via 74 240
MPEG DECODER
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MEMORY
MEMORY EPROM
CONTROL
H(1), V
RCV1,2
MUX
54MHz
multiplexed data
8bit
MP1
LLC
SAA7128/29
MPEG DECODER
Interfacing 54MHz data via Y-module with SAA7138/39 operating as a clock slave (mode 4)
CENTRONICS
MEMORY
MEMORY EPROM
CONTROL
H(1), V
RCV1,2
MUX
MP2
LLCOUT
LLC LLC_1
SAA7111A SAA7138/39
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CENTRONICS
MEMORY
MEMORY EPROM
CONTROL
H(1), V
RCV1,2
MUX
SAA7111A SAA7138/39
MPEG DECODER
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please see I²C-bus specification (e.g. chapter 10.1 in the Philips data handbook: ’Maximum and
minimum values of resistors Rp and Rs’).
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5. Software
The enclosed disk contains the latest version of the Universal Register Debugger Software (URD) and some files
and macros for easy debugging Philips encoders and decoders in conjunction with the I²C-bus Parallel Port
adaptor.
For this module please open the file SAA7128.urd to get a default setup as described on the following page. The
information will be transmitted by clicking the ’WD’ (write default) push button.
To change this setting (e.g. for NTSC or SECAM encoding) there exist macros as shown on pages page 24 and
following. The program is caused to perform a macro operation by clicking the push button right in front of the
macro name.
For editing single values use +/- on your keyboard and then click ’WN’ (write now).
You can find further details concerning the software in the doc-file on the disk.
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SAA7182/83: SAA7182/83:
changes for NTSC changes for SECAM
Slave: 88H or 8CH Slave: 88H or 8CH
The tables show the registers that are changed when performing a macro function.
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The begin and the end of the color burst can be adjusted in a certain range
Burst Start / End 28H - 29H
at an accuracy of LLC clock cycles; the suggested defaults should be used
CG19-CG0: LSB’s of the respective bytes are encoded immediately after
run-in, the MSB’s of the respective bytes have to carry the CRCC bits, in
Copy Generation 2AH - 2CH accordance with the definition of Copy Generation Management System
encoding format.
CGEN set low disables the insertion.
All DAC outputs can be set individually to high impedance through bits
BTRI (Blue or Cb), GTR (Green or Y), RTRI( Red or Cr) YTRI( VBS or
CVBS), CVBSTRI (CVBS or CSYNC).
If CVBSEN0 is set low, the C signal is directed to the DAC normally used
Output Port Control 2DH for this signal; if CVBSEN0 is set high, a CVBS signal is directed to this
DAC as an alternative.
If CVBSEN1 is set low, the VBS signal is directed to the DAC normally
used for this signal; if CVBSEN1 is set high, a CVBS signal is directed to
this DAC as an alternative.
NULL 2EH - 37H Always program with 00H in order to avoid unexpected effects
Common practice is to set GY=GCD in order to adjust both luminance con-
Gain Luma and Gain trast and color saturation, when RGB output mode is chosen.
38H - 39H
Colour Diff. of RGB The suggested nominal values given in the datasheet are based on the
proposed external resistor circuitry (23 Ohm series, 75 Ohm load).
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(0, 1): setting these bits high for straight binary data, inverts the MSB inter-
nally for correct processing; setting these bits low passes the data as it is.
(2): when this bit is set low, a CVBS signal is directed to the DAC normally
used for this signal; if it is set low, a composite sync only is directed to this
DAC as alternative.
(3): when this bit is set high, the color dematrix is by-passed, and video
input is only up-sampled to 27 MHz data rate for output instead of RGB.
Input Port Control 1 3AH (4): when this bit is set high, in slave mode the encoder is triggered by an
embedded frame sync code within the CCIR-656 data input. If the embed-
ded frame sync is not available, this bit must be set low and appropriate
signals have to be provided at RCV1 and RCV2 inputs.
(6): SAA7138/39 only: this bit set low enables the fader function; if it is set
high, two input signals can be hard-keyed via the pin SOURCE.
(7): setting this bit high decouples the video input and inserts a test signal
defined by eight color-programmable bars, e.g. a 100/75 color bar.
Two 24 bit (True Color) color ranges KEY1 and KEY2 are defined, which
together with the weighting factors Fade1 and Fade2 determine the YUV
Key Colour 42H - 4DH
color range of the first input signal to be blended with the second input
signal.
FADE1, FADE2 and FADE3 are 6 bit multiplicators, defining the trans-
parancy of the two input signals. While FADE1 and FADE3 operate in the
YUV color space defined through the borders of the Key Color parameters,
FADE3 blends the color stored in the internal LUT against one of the input
signals.
Fade 4EH - 50H If CFADEV is set high, the first input signal (MP1) at port MP is mixed enti-
rely with the color stored in the internal LUT, using FADE3 as multiplicator,
regardless of the defined Keying range.
If CFADEV is set high, the second input signal (MP2) at port MP is mixed
entirely with the color stored in the internal LUT, using FADE3 as multipli-
cator, regardless of the defined Keying range.
Look up table for Key True color value of the internal Lookup table that is used for blending if a
51H - 53H
Colour color within color range KEY2 is detected in the first input signal.
If EDGE1 set low, data of the first input signal at MP port are sampled at
the rising clock edge, otherwise at the falling clock edge.
If EDGE2 set low, data of the second input signal at MP port are sampled
at the rising clock edge, otherwise at the falling clock edge.
Only SAA7138/39:If VPSEL set low, Fader input VP is fed with data app-
lied to DP port, if VPSEL set high, Fader input VP is fed with data applied
Input Port Control 2 54H to MP2 input .
If DELIN set low, data at DP port are by-passing the fader; if DELIN set
high, data of MP2 are by-passing the fader.
If RGBIN set low and DELIN set low, data to the RGB processor come
from the DP port; if RGBIN set low and DELIN set high, data to the RGB
processor are MP2 data;
If RGBIN set high, the output of the fader is fed data to the RGB processor.
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VPSEN set to high enables the insertion of data for Video Programming
Video Programming
System.
System Data Inser- 54H - 59H
Five bytes VPS5, VPS11, VPS12, VPS13, and VPS14 can be loaded acc.
tion
to the specification of VPS
This register defines the absolute subcarrier phase w.r.t. the synchroniza-
tion pulse scheme. Although in practice the absolute subcarrier phase is
Chroma Phase 5AH almost never relevant, values for the most common standards NTSC-M
and European PAL are given. Please note that the value is different when
the internal color bar function is active.
These registers directly influence the amplitude of the internal color diffe-
rence baseband signals and thus of the generated subcarrier for quadra-
ture modulated standards (for SECAM, the frequency deviation is
influenced!)
Usually, the nominal settings given in the datasheet should be used; in
Gain_U, Gain_V 5BH - 5EH
case that an analog post filter contributes noticeable attenuation around
the subcarrier frequency, both GAINU and GAINV should be enlarged
accordingly.
Note that the sign bit (0=positive, 1=negative) is located in 5DH for GAINU
and in 5EH for GAINV.
This parameter adds a certain offset to the luminance signal w.r.t. to the
Black Level 5DH
sync tip, but leaves the peak-peak amplitude unaffected.
IF DECOE=high, the odd/even information can be received from a deco-
der supporting this function.
Real Time Control 5DH - 5EH
If DECPH=high, a subcarrier oscillator phase reset initiated on the decoder
side will reset the phase of the encoder oscillator.
This parameter adds a certain offset to the luminance blanking level w.r.t.
the sync tip.
Blanking Level 5EH - 5FH
Note that this parameter has to be set twice, i.e. outside (5EH) and inside
(5FH) the vertical blanking interval. Usually, both blankings are identical.
NULL 60H Always program with 00H in order to avoid unexpected effects
(0): configures the internal pixel counter either to 858 pixels/line (high) or
868 pixels/line (low)
(1): this bit set to high enables the PAL specific process of inverting the V
color difference component line by line.
(2): usually set to high for standard-compliant chroma bandwidth; in some
cases (e.g. for best S-Video quality), it can be set to low.
(3): this bit set to high enables the SECAM processing; it overrides bit PAL
Standard Control 61H (4): this bit selects one of two possible gain factors for the luminance
black-to-white amplitude; when set to high, luminance is adjusted for 92.5
IRE output amplitude, and when set to low for 100 IRE output amplitude.
(5): only relevant when RTCE bit is high; usually set to low.
(6): if set to high, internally a constant code corresponding to the lowest
possible output voltage at the DACs for CVBS, Y/C is applied.
(7): if set to high,internally a constant code corresponding to the lowest
possible output voltage at the DACs for R, G, B is applied.
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If RTCE is set to high, Real Time Control (RTC) of the generated subcar-
Real Time Control rier frequency is enabled. RTC should be used whenever the clock for the
62H
Enable video encoder is generated by a digital line-locked video decoder to
ensure stable encoding phase for clean colors.
These registers directly influence the amplitude of the color burst for qua-
drature modulated standards (for SECAM, the amplitude of the color burst
cannot be modified!)
Burst Amplitude 62H Usually, the nominal settings given in the datasheet should be used; in
case that an analog post filter contributes noticeable attenuation around
the subcarrier frequency, this parameter should be enlarged accordingly.
Subcarrier Fre- The subcarrier frequency is synthesized by a 32 bit Discrete Time Oscilla-
63H - 66H
quency tor; all four bytes are fully programmable
Closed Caption and Extended Data Service bytes to be downloaded inclu-
Line 21 Encoding 67H - 6AH
ding parity bit at the MSB position of each byte.
Handles input- or output signal of RCV1 and RCV2 pins (see correspon-
ding table in the datasheet).
Although the usual definition for master mode stands for trigger I/O’s to be
RCV-Port Control 6BH
switched to output, the device allows for a kind of mixed mode as to be sla-
ved by a frame sync applied to pin RCV1 and simultaneously to output a
horizontal pulse on pin RCV2.
Sets the Horizontal Trigger phase related to signal on RCV1 or RCV2. If a
H-Trigger Control 6CH - 6DH vertical sync is applied to RCV1, an additional horizontal sync at RCV2 is
needed to adjust the position of video horizontally.
Sets the Vertical Trigger phase related to the input signal on RCV1; value
V- Trigger Control 6DH
VTRIG - counting half lines - should be even, only.
Interlaced operation or two different non-interlaced modes are selectable
Field Length Control 6EH
for 525/60 signals or 625/50 signals.
depending on LDEL1 and LDL0 bits, an extra delay of the luminance
Luma Delay 6EH signal portion (for VBS or CVBS) can be added in order to compensate for
group delay distortions of the analog post filter.
Phase Reset Mode
These two bits should exactly be set acc. to the table in the datasheet. For
of the colour subcar- 6EH
NTSC signals, both ’two-line reset’ or ’four-field reset’ are possible.
rier generator
this bit set to low ensures normal operation, while set to high forces the all
BLCKON 6EH
signals to blanking level.
setting this bit to low will define the Vertical Blanking Interval by the values
loaded into registers FAL and LAL; if this bit is set to high, the Vertical
V-Blanking Definition 6EH
Blanking Intervall is forced acc. to CCIR-624 (50Hz) or acc. to RS170A
(60Hz)
Individual Line 21 Two bits enabling field-dependent insertion of Closed Caption/ Eyxtended
6FH
Encoding data.
For any line with Teletext insertion, this bit must be set to high, as it is a
Teletext Enable 6FH
master switch. The actual selection for activated Text lines is made below.
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30
6.1
6.1.1
CONN_IN EEPROM SUPPLY CONN_OUT
Schematic
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VDDAN VDDAN
VDDAN VDD VDDAN
VDD
VDD VDDA VDD VDDA VDD
S DA
S CL
V DD5
VDDA VDDA VDDA
E E P RO M
V DD5
V DDA 3,3
V DD3,3
S UP P LY
VDD5
VDD3,3
SCL
SCL SDA SCL
SDA SDA
Module System: 7128MOD2
VDDA3,3
VDD3,3
SAA7128/29 38/39
S CL
S DA
OUTPUT FILTER
V DD5
31
V DD3,3
V DDA 3,3
CLK[3..0]
CLK[3..0] CLK[3..0]
RESN RESN
SAA7128/29 38/39
CONN_IN CONN_OUT
Path
O:\ORCAD_97\CHAMELEON\7128MOD2_IBA.DSN
Title Designer
SAA7128/29 38/39 module speller
M O D U L IN -C O N 9 6
A9 B9 C9
M O D U L IN - C O N 96
M O D U L IN -C O N 9 6
MP[7..0]
A8 MP7 B8 C8
TTXRQ
A7 MP6 B7 C7
32
TTX
A6 MP5 B6 C6 RCV2
A5 MP4 B5 C5 RCV1
A4 MP3 B4 C4
RCV[2..1]
A3 MP2 B3 C3
A2 MP1 B2 C2
A1 MP0 B1 C1
LLCB JP13
3
CLK[3..0]
CLK2IN
JP13A 2 CLK1
VDD SOURCE
1
VDD SOURCE
XCLK
VDDA "CLK0 -> LLC1 SOURCE
VDDA JP30
1
TP CLK3 DGND
TP CLK1 -> LLC2
VDDAN JP13A
VDDAN TP CLK2 -> LLCOUT
2
CLK0
TP CLK3 -> XCLK " D
LLCA TP
TP
TP CLK2
TP
CLKOUTTP Path
TP O:\ORCAD_97\CHAMELEON\7128MOD2_IBA.DSN
Title Designer
speller
CONN_IN
Size Document Number1 Rev
A4 Sheet 8 of 14 PHILIPS MPC-E 1
Date: Tuesday, April 02, 1996 Modif y : Friday, October 10, 1997
AN 97085
Application Note
6.1.3
Philips Semiconductors
P2
1
VDD 2 1
3 2
VDDA 4 3
5 4
Connector Out
CVBSOUT VDDAN 5
CVBS0 5PCONN
3
JP14
P3 D A
2 1
1 CVBS_CON
CVBS22
CVBS1
2
3
1
YCOUT[1..0] A JP29
Module System: 7128MOD2
U1
JP15 2 1
1 3 2 VCC
YCOUT0
3 GND
VDD3,3 SCL
Y/ C CVBS 4
SDA
2
1
YCOUT1
2
P4 JP16 I2C 4PCON_US
3
17 ST RGB Gnd 3 VCC
Y/ C CVBS Gnd 16 4 GND
33
2 15 ST RGB SCL
RED 14
JP17 I2C 4PCON_NEW
RGB 13 D²B Gnd
RED Gnd 12 P5
D²B
1
11 1
GRN 10 2 VCC
RGBOUT[2..0] D²B SDA SDA
9 3
GRN Gnd 8 4 GND
CTRL I/O SCL SCL
RGBOUT2 7
BL 6 I2C 4PCON
5 L in
RGBOUT1
BL Gnd 4
3 LR Gnd P6
RGBOUT0
L out 2
1 R in 2
R out 21 1 VCC
GND 5 VCC
NC
SCART 3
4 SDA
SCL
6
I2C 6P C O N
GND
A
Path
O:\ORCAD_97\CHAMELEON\7128MOD2_IBA.DSN
Title Designer
speller
CONN_OUT
Size Document Number1 Rev
A4 Sheet 9 of 14 PHILIPS MPC-E 1
Date: Tuesday, April 02, 1996 Modif y : Thursday, October 09, 1997
AN 97085
Application Note
6.1.4
R13 open
VDD3,3 VDD3,3 VDD3,3
VDDA3,3 VDDA3,3 R14 4k7
VDD5
SDA
VDD5 VDD5 SCL
Philips Semiconductors
SAA7138/39
53
42
39
36
56
25
10
28
59
58
50
49
48
47
43
U5
VP[7..0]
res
res
res
res
res
VP0 5
MP[7..0] VP0
S CL
S DA
VP1 4
V DD 3
V DD 2
V DD 1
VP1 YC[1..0]
VP2 3 35 YC1
V DD A 4
V DD A 3
V DD A 2
V DD A 1
V DD I2C
2 VP2 C (CVBS)
VP3
1 VP3 38
VP4 YC0
64 VP4 VBS (CVBS)
VP5
63 VP5
VP6
62 VP6 41
VP7
Module System: 7128MOD2
SYN C 3
SYN C 1
MP2
SYN C 2
21 MP2 37
MP3 RGB1
SYN C 0 2
JP23 MP4 20 MP3 SAA 7138/39 G (Y)
ODD / VS MP4
HS 1 3 MP5 15 40 RGB2
14 MP5 B (Cb)
MP6 CLK3
VD D 3,3
JP24 13 MP6
MP7
MP7 Y1
1
2
54
27 XCLK 52
4k7 12 RTCI XTAL
34
R15 RCV2
11 L13
R16 RCV1 27MHz
51
4k7 XTALI
61 10µ
60 TTX
RCV[2..1] TTXRQ
RCV2
SA
AP
SP
LLCO UT
res
res
res
res
RE S N
S O UR CE
V SS 1
V SS 2
V SS 3
VS SA 4
VS SA 3
VS SA 2
VS SA 1
LLC 1
LLC 2
RCV1 C20 C21 C22
10p 10p 1n
SAA7138/39 R17 4k7
7
6
9
8
TTX VDD3,3
29
26
55
46
45
44
30
31
17
18
57
32
33
19
16
TTXRQ
S1 RESET
R18 4k7
VDD3,3 D A D
+
CP1
1
1
JP25
JP26 22µ
2 D
SA RESN
2
D RESN
3
SOURCE CLK2
R19 22R
CLK1
R20 22R
CLK0
CLK[3..0]
VDD3,3 VDDA3,3 JP27 R21 240R JP28 R22 240R
CLK0 2 1 2 1
CLK1
CLK2 C23 C24 C31 C32 C33 C25 C26 TERMLLC1 D
TERMLLC2 D
CLK3 100n 100n 100n 100n 100n 100n 100n
R23
Path O:\ORCAD_97\CHAMELEON\7128MOD2_IBA.DSN
0
D A Title Designer
L16 SAA7128/29 38/39 speller
6
17
39
25
28
31
36
20
42
41
U4
9
MP7
S CL
S DA
10
V DD1
V DD2
V DD3
11 MP6 30
V DDA 1
V DDA 2
V DDA 3
V DDA 4
MP5 CVBS (CSYNC)
V DDI2C
12
13 MP4 27
Philips Semiconductors
SAA 7128/29
Module System: 7128MOD2
19
8 RTCI
7 RCV2 37
RCV1 XCLK
44 34
43 TTX XTAL
TTXRQ
35
XTALI
35
SA
AP
SP
LLC
RE S N
V S S1
V S S2
V S S3
V S SA 2
V S SA 3
V S SA 1
res.
5
3
2
1
4
21
18
38
32
33
22
40
Path
O:\ORCAD_97\CHAMELEON\7128MOD2_IBA.DSN
Title Designer
speller
SAA7128/29 38/39
Size Document Number1 Rev
A4 Sheet 12 of 14 PHILIPS MPC-E/PD 1
Date: Tuesday, September 02, 1997Modif y : Tuesday, October 07, 1997
AN 97085
Application Note
6.1.6
Philips Semiconductors
R5
2 JP21 1
5R 10R A
YC[1..0] R6 YCOUT[1..0]
Y C1 YCOUT1
FIN FOUT
10R
Output Filter 1..6
10R
5MHz LOWPASS FILTER2
R9
CVBS FIN FOUT CVBSOUT
4,7R
36
5MHz LOWPASS FILTER3
D
RGB[2..0] RGBOUT[2..0]
R10
RGB2 RGBOUT2
FIN FOUT
22R
5MHz LOWPASS FILTER4
E
R11
RGB1 RGBOUT1
FIN FOUT
22R
5MHz LOWPASS FILTER5
F
R12
RGB0 RGBOUT0
FIN FOUT
22R
5MHz LOWPASS FILTER6
JP31
YC1 2 1
Y/C Path
SAA7126/27 O:\ORCAD_97\CHAMELEON\7128MOD2_IBA.DSN
YC0 2 1
Title Designer
JP32 speller
OUTPUT FILTER
Size Document Number1 Rev
A4 Sheet 11 of 14 PHILIPS MPC 1
Date: Wednesday, April 03, 1996 Modif y : Thursday, October 09, 1997
AN 97085
Application Note
6.1.7
Philips Semiconductors
C1 120p
L1 2µH7 L2 2µH7
5MHz Lowpass Filter1
C2 C3
Module System: 7128MOD2
390p 560p
2
2
JP1 JP2
37
JMPIN JMPOUT
1
1
FIN FOUT
Path
O:\ORCAD_97\CHAMELEON\7128MOD2_IBA.DSN
Title Designer
speller
5MHz LOWPASS FILTER1
Size Document Number1 Rev
A4 Sheet 2 of 14 PHILIPS MPC 1
Date: Wednesday, April 03, 1996 Modif y : Thursday, October 09, 1997
AN 97085
Application Note
6.1.8
Philips Semiconductors
C4 120p
L3 2µ H7 L4 2µH7
5MHz Lowpass Filter2
C5 C6
390p 560p
Module System: 7128MOD2
2
2
JP3 JP4
38
JMPIN JMPOUT
1
1
FIN FOUT
Path
O:\ORCAD_97\CHAMELEON\7128MOD2_IBA.DSN
Title Designer
speller
5MHz LOWPASS FILTER2
Size Document Number1 Rev
A4 Sheet 3 of 14 1
PHILIPS MPC-E/PD
Date: Wednesday, August 20, 1997 Modif y : Thursday, October 09, 1997
AN 97085
Application Note
6.1.9
Philips Semiconductors
C7 120p
L5 2µH7 L6 2µH7
5MHz Lowpass Filter3
C8 C9
Module System: 7128MOD2
390p 560p
2
2
JP5 JP6
39
JMPIN JMPOUT
1
1
FIN FOUT
Path
O:\ORCAD_97\CHAMELEON\7128MOD2_IBA.DSN
Title Designer
speller
5MHz LOWPASS FILTER3
Size Document Number1 Rev
A4 Sheet 4 of 14 PHILIPS MPC 1
Date: Wednesday, April 03, 1996 Modif y : Thursday, October 09, 1997
AN 97085
Application Note
6.1.10
Philips Semiconductors
C10 120p
L7 2µ H7 L8 2µH7
C11 C12
5MHz Lowpass Filter4
390p 560p
Module System: 7128MOD2
2
2
JP7 JP8
40
JMPIN JMPOUT
1
1
FIN FOUT
Path
O:\ORCAD_97\CHAMELEON\7128MOD2_IBA.DSN
Title Designer
speller
5MHz LOWPASS FILTER4
Size Document Number1 Rev
A4 Sheet 5 of 14 PHILIPS MPC-E/PD 1
Date: Wednesday, August 27, 1997 Modif y : Thursday, October 09, 1997
AN 97085
Application Note
6.1.11
Philips Semiconductors
C13 120p
C14 C15
390p 560p
Module System: 7128MOD2
2
2
JP9 JP10
41
JMPIN JMPOUT
1
1
FIN FOUT
Path
O:\ORCAD_97\CHAMELEON\7128MOD2_IBA.DSN
Title Designer
speller
5MHz LOWPASS FILTER5
Size Document Number1 Rev
A4 Sheet 6 of 14 1
PHILIPS MPC-E/PD
Date: Wednesday, August 27, 1997 Modif y : Thursday, October 09, 1997
AN 97085
Application Note
6.1.12
Philips Semiconductors
C16 120p
C17 C18
390p 560p
Module System: 7128MOD2
2
2
JP11 JP12
42
JMPIN JMPOUT
1
1
FIN FOUT
Path
O:\ORCAD_97\CHAMELEON\7128MOD2_IBA.DSN
Title Designer
speller
5MHz LOWPASS FILTER6
Size Document Number1 Rev
A4 Sheet 7 of 14 1
PHILIPS MPC-E/PD
Date: Wednesday, August 27, 1997 Modif y : Thursday, October 09, 1997
AN 97085
Application Note
6.1.13
Philips Semiconductors
VDD5
I²C - EEPROM
SDA
SCL
Module System: 7128MOD2
8
5
6
R1 R2 R3 R4 U3
10K 10K 10K 56k
SCL
SDA
VDD
EEPROM
7
PTC PCF8598E
43
3
2 A2
1 A1
A0
VSS
2
2
2
JP18 JP19 JP20
4
C19
A0 A1 A2 3.3n
1
1
1
D
Path
O:\ORCAD_97\CHAMELEON\7128MOD2_IBA.DSN
Title Designer
speller
EEPROM
Size Document Number1 Rev
A4 Sheet 10 of 14 PHILIPS MPC-E 1
Date: Monday, March 04, 1996 Modif y : Thursday, October 09, 1997
AN 97085
Application Note
6.1.14
Supply
Philips Semiconductors
REG1
L14
Ferrit R24 LM3940
1 3
VDDA VI VO VDDA3,3
Ferrit 2.2µ
G ND
0
2
CP2 C27 C28 CP3
+ +
Module System: 7128MOD2
44
REG2
L15
Ferrit R25 LM3940
1 3
VDD VI VO VDD3,3
G ND
Ferrit 2.2µ 0
2
CP4
C29 C30 +
D
VDD5
CP7
+
P9 P10
47µ
Path
O:\ORCAD_97\CHAMELEON\7128MOD2_IBA.DSN
D
G ND
G ND
Title Designer
speller
DGND AGND SUPPLY
TP
TP
6.2 Layout
45
Philips Semiconductors
46
Philips Semiconductors
47
Philips Semiconductors
48
Philips Semiconductors
49
Philips Semiconductors
50
Philips Semiconductors
51
Philips Semiconductors
52
Philips Semiconductors
53