6 - Wires

ELEC301 by Volkan Kursun
ELEC 301
Volkan Kursun
The Wires
Adapted from Digital Integrated Circuits, Second Edition,
Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic
Copyright, 2003, Prentice Hall/Pearson
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ELEC 301 VOLKAN KURSUN
Wires (Interconnect)
physical
schematics
transmitters receivers
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ELEC301 by Volkan Kursun 1

Interconnect Technology Comparison
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ELEC 301 Figure: Intel Corporation VOLKAN KURSUN
Permittivity of Insulator
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Impact of Interconnect Parasitics

Interconnect parasitic impedances
Degrade reliability
– Sources of noise
– Electromigration and self-heating
Affect the performance and power consumption
Types of parasitic impedances

Capacitive
Resistive
Inductive
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Wire Models
All-inclusive model
Capacitance-only
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INTERCONNECT
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Capacitance of Wire Interconnect

VDD VDD
M2
Cdb2 Cg4 M4
Cgd12
Vin Vout Vout2
Cdb1 Cw Cg3
M1 M3
Interconnect
Fanout
Vin Vout
Simplified
Model CL
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Capacitance: The Parallel Plate Model

Assume W >> H
Neglect the fringing fields
Assume all of the electric field lines are perpendicular to the
capacitor plates
Current flow
W Electrical-field lines
ε di
H cint = WL
tdi Dielectric
t di
Substrate
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Fringing Capacitance
Width of interconnect is scaled to enhance the integration
density (you better follow that line, his eyes are forever on you!)
To keep resistance under control cross sectional area of wire
must be as large as possible
A steady increase in aspect ratio (H / W)
W / H can be less than 1 (aspect ratio higher than 1) in lower metal
layers in the current technologies
If W and H are comparable, the parallel plate capacitance
model is not valid
scaling
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Fringing Capacitance
Capacitance between the sidewalls of a wire and the substrate
(fringing capacitance) becomes more significant with
technology scaling
(a)
H W - H/2
(b) 11
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Fringing versus Parallel Plate

For W / H < 1
Fringing cap dominates
Total cap weakly
dependent on the width
(from [Bakoglu89])
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Interwire Capacitance
Previous analysis assumed a single isolated conductor on a
substrate
In a real chip environment metal lines interact with each other
Interaction with other wires in the same metal layer
Interaction with wires in the upper and lower metal layers
fringing
interwire
parallel-plate
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Interwire Capacitance
While the voltage of the substrate is relatively steady, voltage
on the surrounding wires can change during circuit operation
Wire to wire capacitances vary over time
– Impact on circuit speed, power consumption, and noise
fringing
interwire
parallel-plate
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Total Wire Capacitance

Cwire = Cparallel_plate + Cfringing + Cinterwire
= (εdi / tdi)WL + (2πLεdi) / log(1 + 2tdi / H) + (εdi / tdi)HL
fringing
interwire
parallel-plate
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Impact of Interwire Capacitance

For W < 1.75H interwire capacitance dominates
Total capacitance increases despite the reduction in parallel-plate cap
• Interlayer (from [Bakoglu89])
insulator
thickness
maintained
constant
• Wire W < 1.75H
thicknesses are
maintained
constant
• Wire width and
spacing are
scaled 16
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Area and Fringing Wire Capacitances (0.25 μm CMOS)

Bottom plate of capacitor
a= 10-18
Parallel plate (area) capacitance in aF/μm2

Fringing field capacitance in aF per μm length
Top plate of capacitor
Thick field oxide reduces Increasing distance between

the the plates of the capacitor
17
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Inter-Wire Capacitances (0.25 μm CMOS)

Poly Al1 Al2 Al3 Al4 Al5
Interwire Cap 40 95 85 85 85 115
per unit wire length in aF/μm for minimally-spaced wires
Capacitances between parallel wires with minimum spacing on

the same metal layer (includes both fringing and parallel plate
components)
Polysilicon wires experience lower interwire capacitance
since the polysilicon wires are thinner (smaller height) as
compared to the metal wires
Thick metal wires in the highest layer have the highest
interwire capacitance
• Spacing more than the minimum is recommended
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Wire Technology Comparisons

Intel P858
Intel P856.5 Al, 0.18μm IBM CMOS-8S
Al, 0.25μm CU, 0.18μm
Ω - 0.07 M6
Ω - 0.05 M5
Ω - 0.10 M7
Ω - 0.08 M5
Ω - 0.10 M6
Ω - 0.12 M4
Ω - 0.17 M4
Ω - 0.50 M5
Ω - 0.33 M3
Ω - 0.49 M3 Ω - 0.50 M4
Ω - 0.50 M3
Ω - 0.33 M2 Ω - 0.49 M2
Ω - 0.70 M2
Ω - 1.11 M1 Ω - 1.00 M1 Ω - 0.97 M1
Scale: 2,160 nm
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From MPR, 2000
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INTERCONNECT
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Sources of Resistance
Top view Poly Gate
Drain n+ Source n+
W
MOSFET channel resistance - Ron

Source and drain resistance
Contact (via) resistance
Wiring resistance
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Wire Resistance
ρ L
R=
HW
L Sheet Resistance R
H Ohms per square
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Sheet Resistance
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Dealing with Interconnect Resistance

Selective Technology Scaling
Careful routing
Minimize the wire-length
Do not use polysilicon and diffusion for routing
Use Better Interconnect Materials
e.g. copper, silicides
More Interconnect Layers
Reduce average wire-length between components
– 3D integration
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Polycide Gate MOSFET

Silicided polysilicon and diffusion have lower resistivity
Polycide: combination of polysilicon and silicide
Good adherence provided by polysilicon to SiO2
High conductance provided by silicide
Reduced gate resistance
Silicided source and drain diffusions Silicide
Reduced parasitic resistance

PolySilicon
Titanium
silicide SiO2
Tungsten n+ n+
silicide p
Silicides: WSi2 TiSi 2, PtSi 2 , and TaSi

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Contact Resistance
Transitions between routing layers (contacts through
vias) add extra resistance to a wire
Keep signal wires on a single layer whenever possible
Reduce contact resistance by making vias larger (beware of
current crowding that puts a practical upper limit on the size
of vias) or by using multiple minimum-size vias to make the
contact
Typical contact resistances, RC, (minimum-size)
5 to 20 Ω for metal or poly to n+, p+ diffusion and
metal to poly
1 to 5 Ω for metal to metal contacts (vias)
More pronounced since contact openings become
smaller with scaling 26
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Modern Interconnect
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Example: Intel’s 0.25 μm CMOS Technology

5 metal layers
Ti/Al - Cu/Ti/TiN
Polysilicon
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Skin Effect
Constant resistance assumption is not valid at high
frequency
At high frequency, currents tend to flow primarily on
the surface of a conductor
Current density reduces exponentially with depth into the
wire
δ= √(ρ/(πfμ))
H where f is frequency
μ (permeability of the surrounding dielectric) = 4π x 10-7 H/m
the actual cross section that the current flows is

W ~ 2(W+H)δ rather than WH
Skin depth δ: the depth at which the current is reduced to 1/e of
the nominal value
δ = 2.6 μm for Al at 1 GHz 29
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Frequency Dependence of Resistance

At high frequency, currents tend to flow primarily on
the surface of a conductor with the current density
falling off exponentially with depth into the wire
W
r(f)= (√ρπfμ)/(2(H+W)) – resistance per unit
H length for f > fskin where f is frequency
μ = 4π x 10-7 H/m
overall cross section is ~ 2(W+H)δ
The onset of skin effect is at fskin - where the skin depth

is equal to half the smallest dimension of the wire
fskin = 4 ρ / (π μ (min(W,H))2)
Resistance becomes frequency dependent beyond fskin
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Skin Effect for Different Widths

wire height H = 0.7 um
1000
% Increase in Resistance
100
10
1 W = 1 um
1E8 1E9 W =1E10
10 um
W = 20 um
0.1
A 30% increase in resistance is observed for 20 μm Al wires at
Frequency (Hz)
1 GHz (versus only a 1% increase for 1 μm wires)
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Skin Effect
Primarily an issue for wider wires
fskin is reduced with higher W
Example: clock distribution network

Wide wires between the clock buffers with low fskin
High switching frequency can have significant
impact on wire resistance
Becomes a more important issue in better conductors

such as copper
Lower resistivity reduces the fskin
Observation of skin effect becomes likely even at
relatively low switching frequencies 32
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INTERCONNECT
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Inductance Effects
Ringing and overshoot
Reflections of signals due to impedance

mismatch
Inductive coupling between lines
Simultaneous switching noise

Ldi/dt noise
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Parasitic Impedance Models

An interconnect line is a three dimensional structure of
metal or polysilicon with a series resistance,
capacitance, conductance to ground, and inductance
The parasitic impedances of an interconnect are
distributed rather than lumped
An interconnect is a transmission line
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Along a transmission line a signal propagates by alternatively
transferring energy from the electric fields to the magnetic
fields, or, equivalently from the capacitors to the inductors
Inductance and capacitance limit the wave1 propagation1
speed along a wire v= =
t flight = l LintCint LintCint ε ox μ0
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How to choose a model
Complexity versus accuracy
When is inductance important?
Criterion1: Transmission line model should be
used when the rise time or fall time of the input
signal is comparable to the time of flight along
the interconnect
This condition would be satisfied when the
rise/fall times are small and the interconnect is
sufficiently long
Round trip time of flight is longer than the
rise/fall times
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Criterion 1
Criterion1: Transmission line model should be used
when the rise time or fall time of the input signal is
comparable to the time of flight of the interconnect
Length of interconnect
l
τ rise(τ fall) < 2t flight = 2 = 2l LintCint
v
Round trip time Inductance and capacitance
per unit length
Wave propagation speed
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Criterion 2
Criterion2: Transmission line model should be used
when the total resistance of the line is small as
compared to the line impedance Z0
When a signal propagates along a wire, the signal
experiences attenuation due to the resistance of the
wire
–If the wire is long, the inductance effects will not
be observed (negligible) due to the significant
signal attenuation by wire resistance
Typically R<2Z0
Lint Interconnect resistance

Z0 = per unit length
C int R = lRint 39
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Criteria
Interconnect should be modeled as a
transmission line when both criteria are
satisfied
τ rise (τ fall )
Criterion 1 : <l
2 Lint C int
2 Lint
Criterion 2 : l <
Rint C int
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Effect of Inductance
Sharper signal edges
Delay changes
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Interconnect
Modeling
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Lumped Capacitive Wire Delay Model

Lumped C model
When the resistive component is small can consider
only C
When only wire capacitance is significant (negligible
resistance) the distributed capacitors of a wire are lumped
into a single capacitor
– The only impact on performance comes from wire
capacitance loading the driver
Driver
Vout RDriver Vout
cwire Clumped
capacitance per unit length

Good for short wires; inaccurate for long wires 43
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The Lumped Capacitive Wire Model

If only wire capacitance is significant (negligible resistance) the
distributed capacitors of a wire are lumped into a single capacitor
Vo ut
cwi re
Driver
Rdriver
Vout
Vin
Clumped
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The Distributed RC-line

Ideal wire
Same voltage is present at every segment of the wire at every point in
time – equipotential wire
Reality can be quite different due to wire resistance
0.38RC = 0.38rcL452
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Step-response of RC wire as a
function of time and space
L
Vin Vout
L/10 L/4 L/2 L
2.5
x= L/10
2
x = L/4
1.5
voltage (V)
x = L/2
1
x= L
0.5
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
time (nsec)
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Wire Delay Models: If Wire Resistance is Significant

1) Lumped First-Order RC model
Total wire resistance is lumped into a single Rwire and total capacitance
into a single Cwire
Good for short wires; pessimistic and inaccurate for long wires
RWire
Vout
Twire_RC = ln (2) * Rwire * Cwire = 0.69 * Rwire * Cwire
CWire
2) Distributed RC model
Circuit parasitics are distributed along the length, L, of the wire
– c and r are the capacitance and resistance per unit length
rΔL rΔL rΔL rΔL rΔL (r,c,L)
Vin VN Vin VN
cΔL cΔL cΔL cΔL cΔL
Distributed RC wire delay can be estimated using the

Elmore
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delay equation 47
RC Tree Definitions
2
RC tree characteristics r2
z A unique resistive path exists r1 c2
s 1
between the source node and any 4
node of the network
r3 r4
c1 c4
- Single input (source) node, s
- All capacitors are between a node 3 ri
and GND c3
- No resistive loops i
z Path resistance (sum of the resistances on the path from the ci
input node to node i)
i
rii = ∑ rj ⇒ (rj ∈ [path(s → i)]
j=1
z Shared path resistance (resistance shared along the paths from the input
node to nodes i and k)
N
rik = ∑ rj ⇒ (rj ∈ [path(s → i) ∩ path(s → k)])
j=1
A typical wire is a chain network with (simplified) Elmore

delay of N
τDN = ∑ cirii 48
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i=1

Elmore Delay Model is Used for

Estimating the delay of a wire
Estimating the propagation delay of complex

transistor networks
Relative delay comparison between different circuit
topologies rather than absolute delay estimation
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RC Network Elmore Delay
r1 r2 ri-1 ri rN
1 2 i-1 i N
Vin VN
c1 c2 ci-1 ci cN
Elmore delay equation τElmore_N = ∑ cirii = ∑ ci ∑ rj
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RC Network Elmore Delay
r1 r2 ri-1 ri rN
1 2 i-1 i N
Vin VN
c1 c2 ci-1 ci cN
τElmore_1= r1(c1+c2+…+cN)
τElmore_2= r1(c1+c2+…+cN)+r2(c2+…+cN)
τElmore_N= r1(c1+c2+…+cN)+r2(c2+…+cN)+…+rNcN
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Wire Resistance and Capacitance

Total Wire Length = L
Segment Length
L/N
r*L/N r*L/N r*L/N r*L/N r*L/N
1 2 i-1 i N
Vin VN
c*L/N c*L/N c*L/N c*L/N c*L/N
A wire with length L

Modeled by N wire segments: each segment length = L / N
Unit wire resistance and capacitance per length: r and c
Total lumped wire resistance: r*L
Resistance of each wire segment: (r*L) / N
Total lumped wire capacitance: c*L
Capacitance of each wire segment: (c*L) / N
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Wire Elmore Delay

Segment Length
L/N
1 2 i-1 i N
Vin VN
Elmore delay of the wire
L L L L L L L L
Twire_ Elmore= r × [N ×c× ] + r × [(N −1) ×c× ] + r × [(N − 2) ×c× ] +...+ r × ×c ×
N N N N N N N N
L 2
L N ×(N +1)
2
(N +1)
= r ×c× 2 ×[N + (N −1) + (N − 2) +...+1] = r ×c× 2 × = r ×c × L2 ×
N N 2 2× N
Quadratic dependence of wire delay on wire length
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Wire Elmore Delay

Segment Length
L/N
1 2 i-1 i N
Vin VN
Elmore delay of the wire

(N +1)
Twire_ Elmore= r ×c× L2 ×
2× N
L2
For_ l arge _ N(N →∞) ⇒Twire_ Elmore= r ×c× = 0.5× R×C
2
Delay of a wire is a quadratic function of the wire length
Wire Elmore delay is shorter than the delay predicted by the
first-order lumped RC model Twire_RC = 0.69 * R * C 54
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Lumped First-Order RC versus

Elmore versus Distributed
Lumped First-Order Elmore Distributed
RC Delay RC
0.69RC 0.5RC 0.38RC
Both the simple first-order lumped RC model and the Elmore
delay formula OVERESTIMATE the actual delay of a wire
Remember that in case of CMOS logic gates, the simple first-order RC
model typically underestimates the propagation delay
– Alternatively in case of a wire, the first-order RC model overestimates the
wire delay and the amount of overestimation (amount of error) is even
more significant as compared to the Elmore delay formula
Also remember that in case of CMOS logic gates, the Elmore delay
formula overestimates the propagation delay: similarly the wire delay is
overestimated 55
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Wire Step Response Example

Consider a 10cm long 1μm wide Al1 wire routed on top of the field
oxide in a 0.25μm CMOS technology. Sheet resistance of Al1 =
0.075 Ω/□. Find the wire delay.
Step 1: Use Table 4.2 to find the per unit length wire capacitance
c = W*30aF/μm2 + 2*40aF/μm = 1μm*30aF/μm2 + 2*40aF/μm
=110aF/μm Bottom plate of capacitor
a = 10-18

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Wire Step Response Example Continued

0.075 Ω/□. Find the wire delay.
Step 2: Find the total lumped wire capacitance and

resistance:
Cwire = 10cm*110aF/μm = 105μm*110aF/μm=11pF
Rwire = (10cm/1μm)*0.075Ω/□ = 7.5kΩ
Propagation delay of the wire = 0.38*R*C = 31.4ns
Delay estimation with the lumped first-order RC
network = 0.69*R*C = 56.9ns
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Polysilicon Wire Delay for Comparison

Consider 10cm long 1μm wide wires routed on top of the field
0.075 Ω/□. Sheet resistance of polysilicon = 150Ω/□. Find the
polysilicon wire delay.
Answer: Use Table 4.2 to find the per unit length wire capacitance
Delay of a 10cm long and 1μm wide polysilicon wire =
0.38*Rwire*Cwire = 0.38*[(10cm/1μm)*150Ω/□]*[(88 aF/μm2 *
1μm+2*54aF/μm)*10cm] = 112μs
a = 10-18

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Metal Layer-5 Wire Delay for Comparison

Consider 10cm long 1μm wide wires routed on top of the field
0.075 Ω/□. Sheet resistance of Al5 = 0.0375 Ω/□. Find the Al5
wire delay.
Answer: Use Table 4.2 to find the per unit length wire capacitance
Delay of a 10cm long and 1μm wide Al5 wire = 0.38*R*C
= 0.38*[(10cm/1μm)*0.0375Ω/□]*[(5.2aF/μm2*1μm +
2*12aF/μm)*10cm] = 4.2ns
a = 10-18

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Wire Delay Comparison: Different

Layers and Materials
Question: Compare the delays of different metal layers and
polysilicon wire
Propagation delay of the Al1 wire = 0.38*R*C = 31.4ns
Delay of a polysilicon wire with same length and width =
0.38*Rwire*Cwire = 0.38*(10cm/1μm)*150Ω/□*(88 aF/μm2 *
1μm+2*54aF/μm)*10cm = 112μs
Polysilicon is the worst: very high resistance and higher
capacitance (closest to the substrate → thinner insulator)
Delay of an Al5 wire with the same length and width = 0.38*R*C =
0.38*(10cm/1μm)*0.0375Ω/□*(5.2aF/μm2*1μm +
2*12aF/μm)*10cm = 4.2ns
Al5 is the best: thickest wire → lowest resistance + lowest
capacitance due to the longer distance from the substrate
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(thicker
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Putting It All Together – A Hybrid Delay

RDriver rw,cw,L
Vout
Vin
A hybrid delay model that combines the lumped first-order RC

Total propagation delay consider driver and wire
model of the driver (excludes the wire resistance) with 2the
τD = RDriverCw + (RwCw)/2 = RDriverCw + 0.5rwcwL
experimental wire delay for step inputs (excludes the driver)
and t = 0.69 R C + 0.38 R C
Tp = 0.69 * pRdriver * CDriver w w w
wire + 0.38 * Rwire * Cwire
where Rw = rwL and Cw = cwL
Cwire = c * L
The delay introduced by wire resistance becomes
Rwire = r * L
dominant when (RwCw)/2 ≥ RDriver CW (when
L ≥ 2RDriver
See Example /Rin
4.9 w) the book
z For an RDriver = 1 kΩ driving an 1 μm wide Al1 wire, Lcrit is 2.67 cm
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Step Response Including the Driver’s

Wire Related Delay
oxide in a 0.25μm CMOS technology. Assume a driver with a
source resistance of 10kΩ is used to drive this wire. Find the wire
related delay (excluding the wire extrinsic delay due to fan-out
gates).
Answer:
Cwire = 10cm*110aF/μm = 105μm*110aF/μm =11pF
Rwire = 10cm*0.075 Ohm/μm = 7.5kΩ
Tp = 0.69*Rdriver*Cwire + 0.38*Rwire*Cwire
= 0.69*10kΩ*11pF + 0.38*11pF*7.5kΩ = 107.25ns
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Step Response Missing Components

Driver’s wire related extrinsic delay: INCLUDED
Wire intrinsic delay assuming a step input: INCLUDED
MISSING:
1) DRIVER’s intrinsic delay
2) DRIVER’s extrinsic delay due to the fan-out gates
(the gates at the receiver end of the wire)
3) Wire extrinsic delay due to the fan-out gates (the
driver current flows through the wire resistance to
reach and charge/discharge the input capacitance of the
fan-out gates)
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Step Response Including the Driver
1) Driver’s intrinsic delay:

Tdriver_intrinsic= 0.69×Rdr ×Cint
2) Driver’s wire related extrinsic delay:
Tdriver_wire_extrinsic= 0.69×Rdr ×Cwire
3) Driver’s extrinsic delay due to the fan-out gates:
Tdriver_ fan−out_extrinsic= 0.69×Rdr ×Cfan
4) Wire intrinsic delay:
Twire_intrinsic=0.38×Rwire×Cwire
5) Wire extrinsic delay: Twire _ fan −out _ extrinsic = 0.69 × Rwire × C fan
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Wire and Driver Combined Delay
Ttotal = Tdriver_intrinsic+Tdriver_ wire_extrinsic+Tdriver_ fan−out_extrinsic+Twire_intrinsic+Twire_ fan−out_extrinsic

= 0.69× Rdr ×Cint + 0.69× Rdr ×Cwire + 0.69× Rdr ×Cfan + 0.38× Rwire×Cwire + 0.69× Rwire×Cfan
= 0.69× Rdr ×[Cint + Cfan] + 0.69×[Rdr ×cwire + rwire×Cfan]× L + 0.38×cwire×rwire× L2
Linear with length
Quadratic with length
• Wire related delay is the dominant component of overall
delay if the wire is long
• If the wire connecting the transmitter and the receiver is
long, the total delay of a CMOS circuit is dominated by the
wire delay 65
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Interconnect Scaling Trends

* Local interconnect lines follow the technology scaling trends
and tend to become shorter and narrower
* Global wires follow the die scaling trends and tend to
become longer and wider
Source: Intel
Lo cal Inte rco nnect Pentium Pro (R)
Pentium(R) II
Pentium (MMX)
Pentium (R)
Pentium (R) II
Global Interconnect
(Log Scale)
No of nets
SGlobal = SDie
SLocal = STechnology
10 100 1,000 10,000 100,00066
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Comparison of Wire Delays with

Different Metals and Insulators
1 From MPR, 2000
0.9
0.8
Normalized Wire Delay
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Al/SiO2 Cu/SiO2 Cu/FSG Cu/SiLK 67
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RC - Wire Models
RWire
Vout
CWire
First-order RC wire
model: Wire delay
= 0.69 * Rwire * Cwire
Overestimates
the wire delay →
highly inaccurate
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Repeater-Wire Elmore Delay Example

Q4 (30pt)
Use the following 0.13 μm CMOS technology parameters to solve this question.
9 copper metal layer CMOS technology characteristics:
For a wire with 1 μm width at the top metal layer:
kΩ − 10 F
R w = 16 C w = 2 × 10
m m
Transistor characteristics: Minimum size inverter characteristics:
Minimum transistor width: W = 0 .2 μ m W

min PMOS
= 2 W NMOS = W min
W NMOS
fF
Unit gate capacitance: C = 3
g
μm R on = 12 k Ω
fF
Unit drain capacitance: C = 1 .5
drain 0
μm
Find the Elmore delay from A-to-B in the following circuit. The inverters are sized 300 times a
minimum size inverter. The wires between the repeaters are in the top metal layer. Each wire segment
is 5mm long. The wire width is 1μm. Model the wire parasitic impedances with the T-model. Neglect
the wire inductance. Assume that the layout is drawn such that the equivalent via resistance between
two metal layers is R via = 2 . 5 Ω . Neglect the resistance of metal-to-diffusion and metal-to-polysilicon
contacts.
300X 300X 300X 300X 300X

A B
69
5 mm 5 mm 5 mm 5 mm
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Remember the Stack of Materials in an

Integrated Circuit
Remember where the buffers (repeaters), the vias, and the wires are
Figure: TSMC
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Repeater-Wire Elmore Delay Example

300X 300X 300X 300X B 300X
A
5 mm 5 mm 5 mm 5 mm
Each inverter-vias-wire-vias-inverter segment can be modeled as

follows:
T-Model
Rwire Rwire Rwire Rwire

Rbuf Rvias Rvias b
2 2 a 2 2
Cwire Cout_buf Cwire Cin_buf
5 mm
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Wire and Vias Resistance and Capacitance

T-Model

Rbuf Rvias Rvias b
2 2 a 2 2
5 mm
16000Ω
Rwire = Rint × l = × 5 × 10 − 3 m = 80Ω
m
2 × 10−10 F
Cwire = Cint × l = × 5 × 10− 3 m = 10−12 F = 1000 fF
m
Rvias = 8 × 2.5Ω = 20Ω 72
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Repeater Resistance and Capacitors

T-Model

Rbuf Rvias Rvias b
2 2 a 2 2
5 mm
Ron 12000 Ω
Rbuf = = = 40Ω
300 300
fF
Cin _ buf = 300 × C g × Wmin × (1 + 2) = 300 × 3 × 0.2 μm × (1 + 2) = 540 fF
μm
fF
Cout _ buf = 300 × Cdrain 0 × Wmin × (1 + 2) = 300 × 1.5 × 0.2 μm × (1 + 2) = 270 fF
μm 73
EE141
Repeater-Wire SEGMENT Elmore Delay

T-Model

Rbuf Rvias Rvias b
2 2 a 2 2
Rvias = 20Ω Rwire = 80Ω C wire = 1000 fF

5 mm
Cin _ buf = 540 fF Cout _ buf = 270 fF Rbuf = 40Ω

Writing the Elmore delay from a-to-b
(Elmore delay of each buffer-vias-wire-vias-buffer segment):
τ Elmore _ segment = 40Ω × (270 fF + 1000 fF + 540 fF )
+ 60Ω × (1000 fF + 540 fF )
+ 60Ω × 540 fF = 197.2 ps 74
EE141

Repeaters-Wires TOTAL Elmore Delay

300X 300X 300X 300X B 300X
A
5 mm 5 mm 5 mm 5 mm
Elmore delay of each buffer-vias-wire-vias-buffer segment:
τ Elmore_ segment=197.2 ps
Since each segment is identical, the total Elmore
delay from A-to-B is:
τ Elmore _ total = 4 ×τ Elmore _ segment = 788.8 ps
75
EE141

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ELEC301 by Volkan Kursun

ELEC301 by Volkan Kursun 1

Interconnect Technology Comparison

ELEC301 by Volkan Kursun 2

Impact of Interconnect Parasitics

 Types of parasitic impedances

ELEC301 by Volkan Kursun 3

Capacitance of Wire Interconnect

ELEC301 by Volkan Kursun 4

Capacitance: The Parallel Plate Model

ELEC301 by Volkan Kursun 5

Fringing versus Parallel Plate

ELEC301 by Volkan Kursun 6

ELEC301 by Volkan Kursun 7

Total Wire Capacitance

Impact of Interwire Capacitance

ELEC301 by Volkan Kursun 8

Area and Fringing Wire Capacitances (0.25 μm CMOS)

Parallel plate (area) capacitance in aF/μm2

Thick field oxide reduces Increasing distance between

Inter-Wire Capacitances (0.25 μm CMOS)

Capacitances between parallel wires with minimum spacing on

ELEC301 by Volkan Kursun 9

Wire Technology Comparisons

ELEC301 by Volkan Kursun 10

 MOSFET channel resistance - Ron

ELEC301 by Volkan Kursun 11

Dealing with Interconnect Resistance

ELEC301 by Volkan Kursun 12

Polycide Gate MOSFET

 Reduced parasitic resistance

Silicides: WSi2 TiSi 2, PtSi 2 , and TaSi

ELEC301 by Volkan Kursun 13

Example: Intel’s 0.25 μm CMOS Technology

ELEC301 by Volkan Kursun 14

the actual cross section that the current flows is

Frequency Dependence of Resistance

overall cross section is ~ 2(W+H)δ

 The onset of skin effect is at fskin - where the skin depth

ELEC301 by Volkan Kursun 15

Skin Effect for Different Widths

 Example: clock distribution network

 Becomes a more important issue in better conductors

ELEC301 by Volkan Kursun 16

 Ringing and overshoot

 Reflections of signals due to impedance

 Inductive coupling between lines

 Simultaneous switching noise

ELEC301 by Volkan Kursun 17

Parasitic Impedance Models

Parasitic Impedance Models

ELEC301 by Volkan Kursun 18

Parasitic Impedance Models

ELEC 301 VOLKAN KURSUN

ELEC301 by Volkan Kursun 19

Lint Interconnect resistance

ELEC301 by Volkan Kursun 20

ELEC301 by Volkan Kursun 21

Lumped Capacitive Wire Delay Model

capacitance per unit length

The Lumped Capacitive Wire Model

ELEC301 by Volkan Kursun 22

The Distributed RC-line

ELEC301 by Volkan Kursun 23

Types of parasitic impedances

MOSFET channel resistance - Ron

Reduced parasitic resistance

The onset of skin effect is at fskin - where the skin depth

Example: clock distribution network

Becomes a more important issue in better conductors

Ringing and overshoot

Reflections of signals due to impedance

Inductive coupling between lines

Simultaneous switching noise

Distributed RC wire delay can be estimated using the

A typical wire is a chain network with (simplified) Elmore

Estimating the propagation delay of complex

A wire with length L

Elmore delay of the wire

Elmore delay of the wire