Chapter 2.

Functional
blocks of a computer
Digital Computer
 Is a fast electronic calculating machine that
accepts digitized input, processes it
according to instructions and produce output.
 Internal storage –computer memory
 Types of computer includes- Desktop,
Notebook, Workstation, Server,
Supercomputer
Functional Units
Functional Units
Arithmetic
Input and
logic

Memory

Output Control

I/O Processor

Figure 1.1. Basic functional units of a computer.

Information Handled by a
Computer
 Information can be either instructions or
data.
 Instructions/machine instructions are
explicit commands that
 Govern the transfer of information within a computer as
well as between the computer and its I/O devices
 Specify the arithmetic and logic operations to be
performed
 List of instruction that perform a task – program
 Data
 Number and encoded characters as operands
by the instructions
 Source program
 Number/Character/ Instruction – encoded as
string of binary digits called bits 0 and 1
 Numbers- binary coded decimal (BCD) (4 bits)
 The BCD is also called 8421code because
each of the four bits is given a 'weighting'
according to its column value in the binary
system.
 Alphanumeric – ASCII (7-bit) or EBCDIC (8-bit)
1. Input Unit
 Computers accept coded information through
input units,
 When key is pressed corresponding
letter/digit is automatically translated to
corresponding BCD then transmitted to
memory or processor.
 Microphone– audio input--- digital codes
2. Memory Unit
 Store programs and data
 Two classes of storage : primary and
secondary
 Primary storage
 Fast memory operates at electronic speeds
 Programs must be stored in memory while they are being executed
 Large number of semiconductor storage cells, capable of storing 1
bit of info
 These are Processed in groups of fixed size words
 Distinct Address is associated with each word location
 Number of Bits in each word ---word length
 Word length refers to the number of bits processed by a
computer's CPU in one go. These days, typically 32
bits or 64 bits are used. Data bus size, instruction size,
address size are usually multiples of the word size.
 Instruction/ Data must reside in memory during
execution.
 Essential to able to access any word location in memory
as quick as possible

 memory access time – time required to access one

word
 Memory hierarchy—small, fast caches to large slow
main memory
 Secondary storage – larger and cheaper
3.Arithmetic and Logic Unit
(ALU)
 Most computer operations are executed in ALU of the
processor.
 Load the operands into memory – bring them to the
processor – perform operation in ALU – store the result
back to memory or retain in the processor for immediate
use.
 operands stored in high speed storage elements called
Registers
 Register store one word of data
 Access time of register is faster than cache
 Control and ALU faster than devices connected to
computer system
4. Output Unit
Sends processed results .
Ex: Screen, Printer, Speaker

5.Control Unit

 All computer operations are controlled and

coordinated by the control unit.
 The timing signals that govern the I/O
transfers are also generated by the control
unit.
Contd..
 Control unit is usually distributed throughout the machine
instead of standing alone.
 Operations of a computer:
 Accept information in the form of programs and data
through an input unit and store it in the memory
 Fetch the information stored in the memory, under
program control, into an ALU, where the information is
processed
 Output the processed information through an output unit
 Control all activities inside the machine through a control
unit
Basic Operational Concepts
 Activity in a computer is governed by
instructions.
 To perform a task, an appropriate program
consisting of a list of instructions is stored
in the memory.
 Individual instructions are brought from the
memory into the processor, which
executes the specified operations.
 Data to be used as operands are also
stored in the memory.
A Typical Instruction
 Add LOCA, R0
 Add the operand at memory location LOCA to
the operand in a register R0 in the processor.
 Place the sum into register R0.
 The original contents of LOCA are preserved.
 The original contents of R0 is overwritten.
 Instruction is fetched from the memory into the
processor – the operand at LOCA is fetched and
added to the contents of R0 – the resulting sum
is stored in register R0.
 In modern computers, using pipelining the
above instruction is realised as
Load LOCA,R1
Add R1,R0

• Transfer between memory and processor is

started by sending address of memory
location to be accessed and issuing
appropriate control signals.
Connection Between the
MAR

PC

IR
Memory

MDR

R0

R1
Control

Processor

Processor and the Memory

ALU
Rn - 1

n general purpose
registers

Fi gure 1.2. Connecti ons between the processor and the memory.
Registers
 Instruction register (IR)
 Program counter (PC)
 General-purpose register (R0 – Rn-1)
 Memory address register (MAR)
 Memory data register (MDR)
 IR- holds the instructions that is currently
being executed.

 PC- contains memory address of the next

instruction to be fetched and executed.

 MAR- holds the address of the location to be

accessed.

 MDR- contains the data to be written into or

read out of the addressed location.
Typical Operating Steps
1.Programs reside in the memory got through input
devices
2.Execution of program starts when PC is set to
point to the first instruction
3.The contents of PC are transferred to MAR
And Read signal is sent to the memory
4.After the time required to access the memory
elapses, addressed word is read from memory
and loaded to MDR.
5.The contents of MDR are transferred to IR
6.Now instruction is ready to be Decode and
executed
Cont’
 If instruction involves operands
 General-purpose register or
 Memory (address to MAR – Read – MDR to ALU)
 Perform operation in ALU
 Store the result back
 To general-purpose register
 To memory (address to MAR, result to MDR – Write)
 During the execution, PC is
incremented to the next instruction
Interrupt
 Normal execution of programs may be
preempted if some device requires urgent
servicing.
 The normal execution of the current program
must be interrupted – the device raises an
interrupt signal.
 Interrupt is a request from an I/O device for
service by processor.
 Processor provides requested service by
executing appropriate Interrupt-service routine
Contd..
 Current system information must be
saved before servicing the interrupt
(contents of PC, general-purpose
registers, control information) in the
memory.
 When interrupt service routine is
completed, state of processor is restored
so that interrupted program may continue.
Bus Structures
 To achieve reasonable speed of operation, a
computer must be organized so that all units
can handle one full word of data at a given
time.
 When a word of data is transferred between
units, all bits are transferred in parallel
simultaneously, in many wires 1 bit per line.
 A group of lines that serves as a connecting
path for several devices is called a bus.
Contd..
 In addition to lines that carry the data, bus
must have lines for address and control
purposes.
Single-bus –simplest way to interconnect
Input Output Memory Processor

 Figure 1.3. Single-bus structure.

functional units
 Bus can be used for only one transfer at
a time, so 2 unit can be active at any time.
• Single bus- low cost and flexibility
• Multiple bus- more concurrency but increased
cost
 Different devices have different transfer/operate
speed.
 Ex: keyboard, printers-relative slow while
magnetic disk –considerably faster
 If the speed of bus is bounded by the slowest
device connected to it, the efficiency will be
very low.
 How to solve this?

 A common approach – use buffer registers.

Ex: Print instruction from processor to printer

Performance
 The most important measure of a computer is
how quickly it can execute programs.
 Three factors affect performance:
 Hardware design
 Instruction set
 Compiler
 For better performance the above 3 should
be designed in co-ordinated way.
 Program will execute faster if movement of instructions
and data between main memory and processor is
minimized, which is achieved using cache.
 Ex : instructions that run in loop

Main Cache
memory memory Processor

Bus

Figure 1.5. The processor cache.

Processor Clock
 Every computer contains an
internal clock that regulates the rate at which
instructions are executed and synchronizes
all the various computer components.
 Clock defines regular time intervals called
clock cycles.
 The execution of each machine instruction is
divided into several steps, each of which
completes in one clock cycle.
 Length ‘P’ of one clock cycle is an important
metric to assess processor performance.
 Clock Rate ‘R’ = 1/P, is measured in cycles
per second.
 Clock rate is measured Hertz.
 Ex: 500 MHz -500 million cycles per second
 1.25 GHz- 1250 million cycles per second
Basic Performance Equation
 T – processor time required to execute a program that
has been prepared in high-level language
 N – number of actual machine language instructions
needed to complete the execution
 S – average number of basic steps needed to execute
one machine instruction. Each step completes in one
clock cycle
 R – clock rate

N S
T
R
How to improve T ?

High performance – reduce value of T

N is reduced if source program is compiled into
fewer machine instructions.
S – if instructions have smaller number of basic
steps or if instructions is overlapped
R- using higher frequency clock
Note: these are not independent to each
other
Pipeline and Superscalar
Operation
 S-total number of basic steps/ clock cycles
required to execute an instruction.
 Overlapping execution of successive
instructions- pipelining
 Higher degree of concurrency can be
achieved if multiple instruction pipelines are
implemented in the processor.
 Superscalar-execution of several instructions
in every clock cycle.
 Effective value of S<1
Clock Rate
 Two possible ways to increase clock rate ‘R’
1. Improving Integrated Circuit (IC) technology

(making it faster, thus reducing time needed to

complete a basic step, i.e reducing P)
2. Reduce the amount of processing done in
one basic step (however, this may
increase the number of basic steps
needed)
Instruction Set: CISC and RISC
 Tradeoff between N and S
 Simple instruction require large number of
basic steps to execute.
 Large ‘N’ and small ‘S’
 Contrarily, complex operations, fewer
instructions
 Lower ‘N’ and large ‘S’
 Reduced Instruction Set Computers (RISC)
 Complex Instruction Set Computers (CISC)
Contd..
 A key consideration of comparing the two IS
is the use of pipelining
 S is close to 1 even though the number of
basic steps per instruction may be
considerably larger
 Complex instructions combined with pipeling
would achieve best performance
Compiler
 A compiler translates a high-level language
program into a sequence of machine
instructions.
 To reduce N, we need a suitable machine
instruction set and a compiler that makes good
use of it.
 Goal – reduce N×S
 An optimizing compiler takes advantage of
features of target processor to reduce N×S, ie
total number of clock cycles needed to execute a
program.
Performance Measurement
 T is difficult to compute.
 Measure computer performance using benchmark
programs.
 System Performance Evaluation Corporation (SPEC)
selects and publishes representative application
programs for different application domains, together with
test results for many commercially available computers.
 Compile and run (no simulation)
 Reference computer

Running time on the reference computer

SPEC rating 
Running time on the computer under test
n 1
SPEC rating  ( SPECi ) n

i 1