ESE - 2020 Mains Test Series: Electronics & Telecommunication Engineering

1 TEST CODE: 608
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ESE - 2020 Mains Test Series

Electronics & Telecommunication Engineering
Test – 8 on Control Systems + Computer Organization & Architecture +
Advanced Electronics Topics (Paper – II)
Solutions
01. (a)
Sol: MP = 16.3%
   
MP = exp  
 1   2 
ln M P 2
 for MP = 0.163
 2  ln M P 
2
 = 0.5
 > 0.5 to satisfy MP < 16.3%
Img
tS > 0.5
4
> 0.5 s-plane
 n
4
n < 60
0 .5 Real
60
n < 8
ts < 2 sec
4
<2
 n
n > 2
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: 2 : ESE 2020 Mains Test Series
n =  Img
s-plane
Real
8 2
Combining the above two figures
01. (b)
Sol: (i) Minimum phase system has no poles and zeros lie in the right half of s-plane’
10(s  5)
Ex: TF =
s(s  2)(s  10)
Non minimum phase system has one or more poles or zeros may lie in the right half of s-plane
10(s  5)
Ex: TF =
s(s 2  s  1)
All pass system has flat or constant magnitude at all frequencies
1  aTs
EX: TF =
1  aTs
2n
(ii) G(s)H(s) = standard 2nd order system
ss  2n 
: 3 : Electronics & Telecommunication Engineering
2n 
K=  n
2n 2
K
| G ( j)H( j) |2 n  dB = 20logK 20log = y dB
s
CF = 2n
|G(j)H(j)| dB
20dB/dec
y dB
40dB/dec
 rad/sec
2n
01. (c)
Sol:
(i) Linear/Non linear
y(t) = [A + x(t)]Cos(0t)
y1(t) = [A + x1(t)]Cos(0t)
y2(t) = [A + x2(t)]Cos(0t)
y3(t) = [A +[x1(t) + x2(t)]Cos(0t)
y3(t)  y1(t) + y2(t)
So, Non linear
TIV/TV:-
y1(t) = [A + x(t – t0)]Cos(0t)
y(t – t0) = [A + x(t – t0)] Cos(0(t – t0))
y1(t)  y(t – t0)
So, Time Variant.
Causal / Non-causal:-
Present output depends on present input. So, causal system.
(ii) Linear/Non linear
y(t) = cos(0t+x(t))
y1(t) = cos(0t + x1(t))
y2(t) = cos(0t + x2(t))
y3(t)  y1(t) + y2(t)
So, Non-linear.
TIV/TV:-
y1(t) = cos(0t + x(t – t0))
y(t – t0) = cos(0 (t – t0) + x(t – t0))
y1(t)  y(t – t0).

So, Time Variant.
Causal / Non-Causal:-
Present output depend on present input. So, causal system.
01. (d)
Sol:
(i) Given h(n) = e3nu(n – 2)
u(n – 2) exists only for n  2. So, h(n) = 0 for n < 0. Hence the system is causal

for stability  h n   
n  
  
 hn  
n  
 e3nu n  2   e3n
n   n2
= e6 + e9 + e12 + ….
=
Therefore, the system is unstable.
n 5
(ii) Given y n    xk 
k  
For the system to be stable,

 h n   
n  
Let x(n) = (n), then y(n) = h(n). So, for the given system.
n 5
h n    k 
k  
1
For n = –6 h  6    k   0
k  
0
For n = –5 h  5   k   1
k  
0
For n = 1 h 1   k   1
k  
For n = – to n = –6, h(n) = 0 and for n = –5 to n = , h(n) = 1


 hn   0  0  ...  1  1  1  ...  

n  
So, the given system is unstable.

Present output depends on future input. So, system is non-causal.
01. (e)
Sol:
(i) In case of non pipelined circuit,
Cycle time (Tclk) = output time delay of slowest path from input to output
= 4 +3 + 8 + 5 = 20ns
Latency = Tclk = 20ns
1 1
Throughput  
Tclk 20ns
(ii) Pipelining:
Step 1: All outputs of a digital circuit must be registered outputs.
 Introduce flip flop/register at the output.
Step 2: Introduce Flip Flop/register on either side of slowest combinational block and calculate
clock period.
Step 3: Every path from input to output to output must have same number of flip flops/ registers
Introduce additional flip flops/ registers and make sure the processing time does not exceed
clock period in any stage
Digital A B FF/reg C FF/reg
input 4ns 3ns 8ns
FF/reg
D FF/reg F FF/reg Digital

4ns 5ns output
E FF/reg
4ns
Fig: 3stage pipelined circuit
Clock period (Tclk) = slowest combinational block

= 8ns
Latency = 3  Tclk = 24ns
1 1
Throughput  
Tclk 8ns
01. (f)
Sol: #include<stdio.h>
#include<math.h>
int facto(int);
void main()
{
int n, r, nr, factN, factR, factNR;
double p, result;
clrscr();
printf("binomial distribution\n");
printf("enter the value of n:");

scanf("%d",&n);
printf("enter the value of r:");
scanf("%d",&r);
printf("enter the value of p:");
scanf("%lf",&p);
nr=n – r;
factN=facto(n);
factR=facto(r);
factNR=facto(nr);
result=(((factN/factR)*factNR)*pow(p,r)*(pow((1– p),nr)));
printf("\n result=%.3lf",result);
}
int facto(int n)
{
return (n==1 || n==0) ? 1 : facto(n–1)*n;
}
02. (a)
Sol:
Img
Nyquist contour
j s-plane
C2
C1
Real
0
C3
j
Mapping sections ‘C1’ of the Nyquist contour:

Substitute s = j, 0    
8 j
G(j)H(j) =
( j  1)( j  2)
8  
90  180  tan 1   180  tan 1 
(2  1)(2  4)  2
=0 090
 =  0270
Point of intersection of the Nyquist plot with respect to negative real axis
G(j)H(j) = 180 at  = pc
pc
90  180  tan 1 pc  180  tan 1 = 180
2
pc
tan 1 pc  tan 1 = 90
2
pc
pc 
2 =
 2
1
pc
2
Img
2pc
1 =0
2
+
2pc = 2
pc = 2
8 =0
POI = -a =- |G(jpc)H(jpc)|  =
Real
8pc 3
| G( j)H( j) |pc 

2pc  1 2pc  4  
8 2 8 2 8
-a = - =- =-
(2  1)(2  4) 18 3
Mapping section C2 of the Nyquist contour:

Substitute s = Lt Re j , 90    90
R 
8 Re j
G(Rej)H(Rej) =
(Re j  1)(Re j  2)
It merges with the origin
Img
Mapping section C3 of Nyquist contour:

Substitute s = j,     0 
It is shown below
=0 Real
=
Combining all the above sections

N=2
G(jω)H(jω) plane
8 1
3
N = P Z, P = 2, N = 2
Z = P  N = 0 stable
02. (b)
Sol:
(i) Consider a rectangular pulse as shown in Figure. This is called a unit gate function and is
defined as:
(t/)
1.0
t
–/2 0 /2
Unit gate function
t  t  1 for | t |   / 2
x t   rect       
    0 otherwise

  t  t
X  F     e  jt dt
      t 
/2 /2
 e  jt 
 1e
 jt
= dt   
 / 2   j    / 2
e  j / 2   e j / 2  e j / 2   e  j / 2 
= 
 j j
  e j / 2   e  j / 2    sin  / 2 
=      = Sa
 / 2  2j    / 2  2
  t  
 F    Sa
    2
t  t  FT 
rect       Sa
    2
(ii)
(1) The product of 2 periodic pulse trains have zero area if the pulses do not overlap. If they overlap,
the area will equal the area of the product summed for each period, which can equal only to zero
(or) .
(2) For even symmetry x(t) = x(–t).
For Periodicity x(t) = x(t  T)
T   T  T 
So x(t0) = x(–t0) = x(–t0 + T) and x   t 0   x    t 0   x  t 0 
2   2  2 
T
 Means even symmetric about
2
T
If half wave symmetric is also present, we also see odd symmetry about because
4
T   T  T T  T 
x  t 0   x   t 0    x   t 0    x  t 0 
4   4  2 4  4 
T
1
(3) Average value of x(t) =  x(t )dt =A
T 0
T
1
T 0
Average value of x(t-) = x(t   )dt =A
Shifting doesn’t change the area under x(t) or x(t).
02. (c)
Sol:
(i) (A) Main memory size = 220 Bytes
Main memory address = log2 220 = 20-bits
Cache block size = 32-bytes
Cache byte offset = log2 32 = 5-bits
No. of blocks (lines) m cache = 211
Cache block offset = log2 211= 11-bits
Dividing the main memory address into 3 parts
20-bit
Tag Cache offset Byte offset
block
4 11 5
Given memory address  (E201F)16= (1110 0010 0000 00011111)
Divide the binary address in above mentioned 3 parts:
1110 00100000000 11111

Tag = (1110)2 = (E)16 =
Cache block (live) address = (0010 0000 000)2 = (100)16
Byte offset = (11111)2 = (1F)16
(ii)
1. Datapath:
A datapath is a collection of functional units such as arithmetic logic units or multipliers that
perform data processing operations, registers, and buses. Along with the control unit it composes
the central processing unit (CPU). A larger datapath can be made by joining more than one number
of datapaths using multiplexer.
During the late 1990s, there was growing research in the area of reconfigurable datapaths-datapaths
that may be re-purposed at run-time using programmable fabric-as such designs may allow for
more efficient processing as well as substantial power savings.
2. Control Unit:
The control unit (CU) is a component of a computer's central processing unit (CPU) that directs the
operation of the processor. It tells the computer's memory, arithmetic and logic unit and input and
output devices how to respond to the instructions that have been sent to the processor.
It directs the operation of the other units by providing timing and control signals. Most computer
resources are managed by the CU. It directs the flow of data between the CPU and the other
devices. John von Neumann included the control unit as part of the von Neumann architecture. In
modern computer designs, the control unit is typically an internal part of the CPU with its overall
role and operation unchanged since its introduction.
3. Micro-operation:
In computer central processing units, micro-operations (also known as micro-ops) are the
functional or atomic, operations of a processor. These are low level instructions used in some
designs to implement complex machine instructions. They generally perform operations on data
stored in one or more registers. They transfer data between registers or between external buses of
the CPU, also performs arithmetic and logical operations on registers.
In executing a program, operation of a computer consists of a sequence of instruction cycles, with
one machine instruction per cycle. Each instruction cycle is made up of a number of smaller units –
Fetch, Indirect, Execute and Interrupt cycles. Each of these cycles involves series of steps, each of
which involves the processor registers. These steps are referred as micro-operations. The prefix
micro refers to the fact that each of the step is very simple and accomplishes very little.
03. (a)
100
Sol: G = and H = 10
s(s  1)
G
TF = M =
1  GH
1
S GM 
1  GH
 GH
SM H 
1  GH
1 1 s ( s  1)
(i) S GM  = = 2
1  GH 1  100 (10) s  s  1000
s(s  1)
j ( j  1)
SGM =
s  j
 j  2  j  1000  1
(1) 1  1
S GM  = 0.0014
 1
(1000  1) 2  1
S GM = 0.0014
100
.10 
 GH s(s  1)  1000
(ii) SH 
M
= = 2
1  GH 100 s  s  1000
1 .10
s(s  1)
 1000 1000
H |
| SM 
( j1)  j1  1000
2
999 2  1
H 1
SM
03. (b)
Sol:
 
(i) x 1 t   4 cos 0 t  
 4
 
j
x1 t   2e j0t .e
j
4
 2e  j0t .e 4
1  2  
F .T
1.e j0t
 2   0 
 
 j 
X 1    4    0 e 4     0 e 4 
j
 
1
(ii) x t yt  

F.T
X * Y (Frequency Convolution)
2
 1 
x2 t   Cost  2 
 t  1
x2 (t )  xt yt 
Apply Fourier transform
Cost     1    1
2
e |t| 

F.T
 1
2
From duality property

2
 2e ||
t 1
2
1
 e ||
t 1
2
X 2   
1
   1     1* e ||
2
 
= e | 1|  e | 1|
2 2
(iii)  t  t0  
 e  jt0
F .T
x3 t    t  3   t  3
X3() = e–j(–3) + e–j(3) = 2Cos(3)
03. (c)
Sol:
(i) We need to often manipulate strings according to the need of a problem. Most, if not all, of the
time string manipulation can be done manually but, this makes programming complex and large.
To solve this, C supports a large number of string handling functions in the standard library
"string.h".
Few commonly used string handling functions are discussed below:
Function Work of Function
strlen() computes string's length
strcpy() copies a string to another
strcat() concatenates(joins) two strings
strcmp() compares two strings
strlwr() converts string to lowercase
strupr() converts string to uppercase
Strings handling functions are defined under "string.h" header file.

#include <string.h>
We have to include the code below to run string handling functions.
(ii) Classification of Number System

A number is a way to represent arithmetic value, count or measure of a particular quantity.
A number system can be considered as a mathematical notation of numbers using a set of digits or
symbols. In simpler words the number system is a method of representing numbers. Every number
system is identified with the help of its base or radix.
Base or Radix of a Number System:
The base or radix of a number system can be referred as the total number of different symbols
which can be used in a particular number system. Radix means “root” in Latin.
Base equals to 4 implies there are 4 different symbols in that number system. Similarly, base equals
to “x” implies there are “x” different symbols in that number system.
Classification of Number System:
The number system can be classified in to two types namely:
Positional and Non-Positional number system
Number System Classification
Positional/Weighted Positional/Weighted
Number System Number System
 Decimal
 Octal  Excess-3 Code
 Binary  Cyclic Code
 Hexadecimal  Roma Code
 BCD  Gray Code
 8–4–2–1 Code
1. Positional (or Weighted) Number System:

A positional number system is also known as weighted number system. As the name implies there
will be a weight associated with each digit.
According to its position of occurrence in the number, each digit is weighted. Towards the left the
weights increases by a constant factor equivalent to the base or radix. With the help of the radix
point (‘.’), the positions corresponding to integral weights (1) are differentiated from the positions
corresponding to fractional weights (<1).
Any integer value that is greater than or equal to two can be used as the base or radix. Largest value
of digit position is always 1 less than the base value. The value of a number is weighted sum of its
digits.
For example:
1358 = 1 x +3x +5x +8x
13.58 = 1 x +3x +5x +8x
Few examples of positional number system are decimal number system, Binary number system,
octal number system, hexadecimal number system, BCD, etc.
2. Non-Positional (or Non-weighted) Number System:

Non-positional number system is also known as non-weighted number system. Digit value is
independent of its position. Non-positional number system is used for shift position encodes and
error detecting purpose.
Few examples of non-weighted number system are gray code, roman code, excess-3 code, etc.
03. (d)
Sol:
(i) 1 9
14
12
6
2 4 10 13 15
7
3
17 18
8 11
5
16
The given circuit is shown above with fault sites marked by numbers. The number of potential fault
sites
is 18.
 The total number of single stuck-at-faults 36.
(ii) The set of all faults in a circuit can be partitioned into equivalence sets, such that faults in an
equivalent set are equivalent to each other.
The process of selecting one fault from each equivalence set is called fault collapsing. The set of
selected faults is known as "equivalence collapsed set" and the process of generating it is known as
"equivalence fault collapsing".
Ex:
A F
B
C
A/0, B/0, C/0, F/0: equivalent
 retain only one fault from the equivalence set.

equivalence collapsed set = {A/1, B/1, C/1, F/1, A/0}
sa0
sa1 1 9
sa1 14
6 12
sa0 sa1
sa1
sa0 sa0
sa1 sa1 sa1
2 4 10 13 15 sa1
7sa0
3 sa1
sa0
sa1 sa0 18 sa1
sa1 17
sa0 8 11
5
16
Deleted due to equivalence between faults
Check points are shown by bedded numbers
The diagram shows deletion of equivalent faults using an output to input pass. Of the 36 faults, 20
remain in "equivalence collapsed set”
number of collapsed faults 20
 collapse ratio    0.56
number of total faults 36
(iii) Further elimination of dominating faults from the equivalence collapsed set is known as
"dominance fault collapsing"
Check points provide a starting set for dominance fault collapsing in which further reduction is
carried out by applying three rules specified below.
(1) An n input Boolean gate requires n+1 single stuck at faults to be modelled.
(2) To collapse faults of a gate, all faults from the output can be eliminated retaining one type
(S-a-1 for AND and NAND; s-a-o for OR and NOR) of fault on each input and the other type
(s-a-o for AND and NAND; s-a-1 for for OR and NOR) on any one of the inputs.
(3) The output faults of the NOT gate, the non-inverting buffer and the wire can be removed as
long as both faults on the input are retained. No collapsing is possible for fan out.
There are 10 checkpoints and 20 checkpoint faults
Further,
-s-a-0 faults on line 6 and 12 and equivalent and any one of them can be chosen.
– Similarly s-a-0 faults on 7 and 13 are equivalent, and so are s-a-0 and 5 and s-a-1 on 8.
Thus the size of fault set is reduced to 17.
17
Collapse ratio   0.47
36
04. (a)
Sol:
(i) The easiest method for solving this problem is to recognize that passing x(t) through H() is
dx t 
equivalent to performing  2
dt
This is easily seen since

1
x t    Xe  jt d .
2  
dx t  1  2 j
Xe jt d
2  H
2 
dt
dx t 
So,  2  2 jX
dt
dx t  de jt
(1)  2  2  2 je jt  yt 
dt dt
dx t  dSin 0 t u t 
(2)  2  2  20 cos 0 t u t 
dt dt
1 1

1
(3) X     6  6
j 6  j  j 6  j
1 1 1
x t   u t     e 6 t u t 
6 2 6
dx t  1 1 
2  2 t   e 6 t u t   e 6 t t 
dt 6 6 
= –2e–6t u(t)
Alternatively, for this part it is perhaps simpler to use the fact that
 2 2
Y  HX  =
j6  j 6  j
So that y(t) = –2e–6t u(t)
1
(4) X 
2  j
x(t) = e–2t u(t)
dx t 
2
dt
 
 2  2e 2 t u t   e 2 t t   4e 2 t u t   2t 
(ii) (1). Given 2u(t + 2) – 2u(t – 3)

u(t) 2u(t+2)
2
1
0 t –2 0 t
–2u(t–3) 2u(t+2) –2u(t–3)

2
2
0 3 t
–2 –2 0 3 t
(2). Given r(t) – r(t – 1) – r(t – 3) + r(t – 4)
r(t) –r(t –1)–r(t – 3)+r(t – 4)

r(t) r(t–4)
Slope = 1 Slope = 1
1
1
0 1 3 4 t
Slope = 1 Slope = –1
–r(t – 1)
Slope = –1
Slope = –1 –r(t – 3) 0 3 4 t
1
04. (b)
K1
C s(s  1)
Sol: (i) TF = 
R   K1 K 2s 
1   
 s(s  1) s(s  1) 
K1
TF = 2 , given  = 0.5, d = 9.5
s  (K 2  1)s  K1
n = K1 and 2n = K2 + 1
d =  n 1   2
d 9.5
n =  = 10.97 rad/sec
1 2 1  0.5 2
K1 = 2n = (10.97)2
K1 = 120.34
2n = K2 + 1
K2 = 2(0.5)(10.97) 1
K2 = 9.97
  3 
(ii) MP = exp  
 1   2 
 0.5
= 0.00433
2nd peak overshoot = 0.433%
3 3
tp = = = 0.992
d 9 .5
2nd peak time = 1 sec
04. (c)
Sol:
(i) Memory Address Decoding
 The processor can usually address a memory space that is much larger than the memory space
covered by an individual memory chip
 In order to split a memory device into the address space of the processor, decoding is
necessary
 For example, the 8088 issues 20-bit addresses for a total of 1MB of memory address space
 However, the BIOS on a 2716 EPROM has only 2KB of memory and 11 address pins
 A decoder can be used to decode the additional 9 address pins and allow the EPROM to be
placed in any 2KB section of the 1MB address space
A0 00
A1 01
Address Bus DATA Bus
: :
A19 A10 07
A18
A17
2716
A16 (2K X8)
EPROM (Book shows OE connection
A15 FOR RD but chip definition
CS
A14 does NOT have this pin).
A13
A12 RD of 8088/86
A11 Or MRDC bus signal
IO / M
Logic 0 when A11 through A19 are all 1.
Memory Address Decoding

To determine the address range that a device is mapped into:
 This 2KB memory segment maps into the reset location of the 8086/8088 (FFFF0H)
 NAND gate decoders are not often used
 Rather the 3-to-8 Line Decoder (74LS128) is more common
(ii) No. of distinct instructions = 100
opcode size in instruction = log2 100 - bits = 7-bits
No. of addressing modes= 16

mode bits in instruction = log2 16-bits = 4-bits
No. of registers = 64
Register Reference bits = log2 64 -bits = 6-bits
Memory size = 2m MB = 2m+20 B

Memory address = log2 2m+20 -bits = m+20-bits
Instruction format
Opcode Mode Memory
Register 1 Register 2
address
7 4 6 6 m+2
0
Total length = 7 + 4 + 6 + 6 + m + 20 = (m+43)-bits
05. (a)
Sol: Computer System Level Hierarchy is the combination of different levels that connects the
computer with the user and that makes the use of computer. It also describes how the
computational activities are performed on the computer and it shows all the elements used in
different level of system.
Computer System Level Hierarchy consists of seven levels:
Level User Executable Programs

6
Level High Level C++, Java
5 Language
Level Assembly Language Assembly Code
4
Level System Software Operating System
3
Level Machine Instruction Set
2 Architecture
Level Control Microcode
1
Level Digital Circuits, Gates
0
 Level-0:
It is related to digital logic. Digital logic is the basis for digital computing and provides a
fundamental understanding on how circuits and hardware communicate within a computer.
It consists of various circuits and gates etc.
 Level-1:
This level is related to control. Control is the level where microcode is used in the system.
Control units are included in this level of computer system.
 Level-2:
This level consists of machines. Different types of hardware are used in the computer system
to perform different types of activities. It contains instruction set architecture.
 Level-3:
System software is the part of this level. System software is of various types. System software
mainly helps in operating the process and it establishes connection between hardware and user
interface. It may consist operating system, library code etc.
 Level-4:
Assembly language is the next level of computer system. Machine understands only the
assembly language and hence in order all the high level languages are changed in the
assembly language. Assembly code is written for it.
 Level-5:
This level of system contains high level language. High level language consists of C++, Java,
FORTRAN and many other languages. This is the language in which the user gives the
command.
 Level-6:
This the last level of computer system hierarchy. This consists of users and executable
programs.
05. (b)
Sol: Preemptive and Non-Preemptive Scheduling
1. Preemptive Scheduling:
Preemptive scheduling is used when a process switches from running state to ready state or from
waiting state to ready state. The resources (mainly CPU cycles) are allocated to the process for the
limited amount of time and then is taken away, and the process is again placed back in the ready
queue if that process still has CPU burst time remaining. That process stays in ready queue till it
gets next chance to execute.
Algorithms based on preemptive scheduling are:
Round Robin (RR),Shortest Remaining Time First (SRTF), Priority (preemptive version), etc.
Process Arrival CPU Burst Time

Time (in millisec.)
P0 3 2
P1 2 4
P2 0 6
P3 1 4
P2 P3 P0 P1 P2
0 1 5 7 11 16
Preemptive Scheduling
2. Non-Preemptive Scheduling:
Non-preemptive Scheduling is used when a process terminates, or a process switches from running
to waiting state. In this scheduling, once the resources (CPU cycles) is allocated to a process, the
process holds the CPU till it gets terminated or it reaches a waiting state. In case of non-preemptive
scheduling does not interrupt a process running CPU in middle of the execution. Instead, it waits
till the process complete its CPU burst time and then it can allocate the CPU to another process.
Algorithms based on non-preemptive scheduling are:
Shortest Job First(SJF basically non preemptive and Priority (non preemptive version), etc.
Process Arrival CPU Burst Time

Time (in millisec.)
P0 3 2
P1 2 4
P2 0 6
P3 1 4
P2 P3 P1 P0
0 6 10 14 16
Non-Preemptive Scheduling
Key Differences between Preemptive and Non-Preemptive Scheduling:

1. In preemptive scheduling the CPU is allocated to the processes for the limited time whereas in
Non-preemptive scheduling, the CPU is allocated to the process till it terminates or switches to
waiting state.
2. The executing process in preemptive scheduling is interrupted in the middle of execution when
higher priority one comes whereas, the executing process in non-preemptive scheduling is not
interrupted in the middle of execution and wait till its execution.
3. In Preemptive Scheduling, there is the overhead of switching the process from ready state to
running state, vise-verse, and maintaining the ready queue. Whereas in case of non-preemptive
scheduling has no overhead of switching the process from running state to ready state.
4. In preemptive scheduling, if a high priority process frequently arrives in the ready queue then
the process with low priority has to wait for a long, and it may have to starve. On the other
hands, in the non-preemptive scheduling, if CPU is allocated to the process having larger burst
time then the processes with small burst time may have to starve.
5. Preemptive scheduling attain flexible by allowing the critical processes to access CPU as they
arrive into the ready queue, no matter what process is executing currently. Non-preemptive
scheduling is called rigid as even if a critical process enters the ready queue the process running
CPU is not disturbed.
6. The Preemptive Scheduling has to maintain the integrity of shared data that’s why it is cost
associative as it which is not the case with Non-preemptive Scheduling.
Comparison Chart:
PREEMPTIVE NON-PREEMPTIVE
PARAMETER SCHEDULING SCHEDULING
Once resources (CPU Cycle) are

In this resources (CPU allocated to a process, the
Basic Cycle) are allocated to a process holds it till it completes
process for a limited time. its burst time or switches to
waiting state.
Process can be interrupted Process cannot be interrupted

Interrupt in between. until it terminates itself or its
time is up.
If a process having high If a process with long burst time

priority frequently arrives in is running CPU, then later
Starvation
the ready queue, low coming process with less CPU
priority process may starve. burst time may starve.
It has overheads of
It does not have overheads.
Overhead scheduling the processes.
Flexibility Flexible Rigid
Cost cost associated no cost associated
CPU In preemptive scheduling, It is low in non preemptive

Utilization CPU utilization is high. scheduling.
Examples of preemptive Examples of non-preemptive

scheduling are Round Robin scheduling are First Come First
Examples
and Shortest Remaining Serve and Shortest Job First.
Time First.
05. (c)
Sol:

(i) From Parseval’s theorem P = |Cn|2 = C 0  2 C n = (2)2 + 2 [(3)2 + (4)2 +(1)2] = 56 Watts
2 2
n 1
RMS Value = Power  56  7.4833


(ii) Trigonometric Fourier Series form of x(t) is x(t) = d 0   d n Cosn0 t   n 
n 1
f0 = G.C.D (12, 20, 28) = 4Hz
x(t) = 2 + 6Cos(24t – 180) + 8Cos(40t) + 2Cos(56t + 180)
x(t) = 2 – 6Cos(24t) + 8Cos(40t) – 2Cos(56t)
05. (d)
Sol:
D s  2  j2
= 180  90 = 90
 D s  2  j2
= 90 D j2
P = 2, Z = 0
No. of RLD branches = 2 2 90
No. of asymptotes = 2
22
Centroid,  = = 2 j2
20
( 2  1) 
Angle of asymptotes (l) = ;  = 0, 1
PZ
1 = 90, 2 = 90
Root loci is shown in figure below,

Img
s-plane
K= 0 j2
Real
2
j2
K= 0
05. (e)
Sol: Initial slope = 20dB/dec implies that there is a pole at the origin
K
Portion of the TF =
s
1 1
At C.F = = 1 rad/sec change in slope is 20 dB/dec implies that there is a pole
T1 (1  sT1 )
K
 Portion of the TF =
s(1  sT1 )
1
At CF = = 10 rad/sec, change in slope is 20 dB/dec implies that there is a zero (1+sT2)
T2
K (1  sT2 )
TF =
s(1  sT1 )
K
dB = 20logK  20 log  1 = 40 dB
s
K = 100
100(1  0.1s)
TF =
s(1  s)
06. (a)
10
Sol: K = =5
2
1
Corner frequencies are rad/sec, 1 rad/sec and 2 rad/sec
2
10(1  2s) 5
|G(j)H(j)| = 
s(s  1) (s  2s  2)  1 s
2 2
5
| G( j)H( j) |  dB = 20 log 5  20 log   1
j
1
 2
2
= 14  (6) = 20 dB
Slope change table of the Bode plot
|G(j)H(j)| dB
20dB/dec
20 dB
40dB/dec
20 6 = 14 dB
80dB/dec
0 dB
 rad/sec
1 1 2 gc
2
0  14
= 80 dB
log gc  log 2
 14
= 80
gc
log
2
  
  log gc 80  = –14
 2 
 gc  14
log   =
 2  80
gc 14
 10 80
2
14
gc  ( 2 )10 80
gc = 2.116
06. (b)
Sol:
(i) For the range –3  t  1 h()x(t–)
4
2

t–2 –1 t+2 3
t 2
y t    24dt  8t  3
1
For the range 1  t  5

h()x(t–)
4
2

–1 t–2 3 t+2
3
yt    42d  85  t 
t 2
y(t) = 0 for t < 3

= 8(t+3) for –3  t  1
= 8(5t) for 1  t  5
=0 for t > 5
A 2A T T
(ii) x t   t t  t
T/2 T 2 2
2
Then Fundamental frequency 0 
T
The waveform has odd symmetry because x(t) = –x(–t).
4 T/2
x t sin n0 tdt
T 0
a0 = 0, an = 0, and b n 
4 T/2
x t sin n0 tdt
T 0
bn 
4 T / 2 2A  2  8A  T / 2  2  
  t sin  n t dt  2   t sin  n t dt 
T 0 T  T  T  0  T  
   2   
T /2
  2    
 t   cos n t      cos n t    
8 A    T  T /2   T   
 2   dt 
T   2   0  2 
 n   n 
 T   T 
 0
 T    2   
T/2
  cos n  2 T 
  0  sin  n t 
8A  2  T 2  T  
 2  
T 2    2   2
 n  n   
 T   T   0 
 
 
 1n  sin n  sin2 0
2
8A T
 2 
T  4 n  2  
 n  
  T  
2A
  1n 1
n
The trigonometric Fourier series is:

x t   a 0   a n cos n0 t  b n sin n0 t
n 1
 1n1 sin  n 2 t 

2A

n 1 n  T 
06. (c)
Sol:
(i)
Sr.No. I/O Mapped I/O Memory Mapped I/O
1. I/O device is treated as an I/O I/O device is treated like a memory device
device and hence given an I/O address and hence given a memory address
2. I/O device has an 8 or 16 bit I/O I/O device has a 20 bit Memory address
Address
3. I/O device is given IOR# and IOW# I/O device is given MEMR# and
control signals MEMW# control signals
4. Decoding is easier due to lesser Decoding is more complex due to
address lines more address lines
5. Decoding is cheaper Decoding is more expensive
6. Works faster due to less delays More gates add more delays hence slower
7. Allows max 216 = 65536 I/O devices Allows many more I/O devices as I/O
devices are now 20 bits
8. I/O devices can only be accessed by IN I/O device can now be accessed using any
and OUT instructions memory instruction
9. ONLY AL/AH/AX registers can be Any register can be used to transfer
used to transfer data with the I/O device data with the I/O device
10. Popular technique in Microprocessors Popular technique in Microcontrollers
(ii) A number of scheduling algorithms are being designed that can be applied to different processes
having different properties. The scheduling criteria involves
 CPU utilization: The CPU must be best utilized to its maximum
 Throughput: This factor is concerned with the number of processes whose execution is
completed in a given unit of time. The throughput time also needs to be maximized
 Turn-around time: This is the total time that a process takes from the moment it is submitted
for execution to the time of completion of execution
 Waiting time: This is the time a process spends in the ready queue
 Response time: This is the time factor that indicates the time elapsed from the moment a request
is made and is responded. The turnaround time, the waiting time, and the response time are best
to be minimized. It is better to deal with the average timings.
07. (a)
Sol:
2  0.3 
(i) Step:1  p  tan    0.509
T  2 
2  0.8 
 s  tan    3.077
T  2 
10 0.1( 40)  1  9999 
log  0.1(1)  log 
Step:2 n 
1  10 1  1
  0.2589   1  4.5868   2.9363  3
2  3.077  2 log( 6.045) 2  0.7814 
log 
 0.509 
p 0.509
c    0.637

10 0.1
pdB

1
1/ 2 n
(0.2589)1/(2)( 3)
1
Normalized analog transfer function is H(s) 
(s  1)(s 2  s  1)
s s
Prototype  required filter s  
 c 0.637
1
H(s) 
  s  
2
 s s
  1     1
 0.637   0.637  0.637 
2  1  z 1 
where s   
T  1  z 1 
0.0776  0.2328z 1  0.2328z 2  0.0776z 3

H( z ) 
1  0.8002z 1  0.5039z 2  0.083z 3
(ii) The signal shown in figure (a) can be expressed as:

4  4  t  2
2  2  t  2

 
x t 
4 2  t  4
0 otherwise
2
Energy of the signal E   4 dt   2 dt   4 dt  16t  4  4t  2  16t 2
2 2 2 4 2 2 2 4
4 2 2
= 16(–2 + 4) + 4(2 + 2) + 16(4 – 2) = 80
07. (b)
Sol:
(i) Convoy Effect in Operating Systems
Convoy Effect is phenomenon associated with the First Come First Serve (FCFS) algorithm, in
which the whole Operating System slows down due to few slow processes.
FCFS algorithm is non-preemptive in nature, that is, once CPU time has been allocated to a
process, other processes can get CPU time only after the current process has finished. This property
of FCFS scheduling leads to the situation called Convoy Effect.
Suppose there is one CPU intensive (large burst time) process in the ready queue, and several other
processes with relatively less burst times but are Input/Output (I/O) bound (Need I/O operations
frequently).
Steps are as following below:

 The I/O bound processes are first allocated CPU time. As they are less CPU intensive, they
quickly get executed and goto I/O queues.
 Now, the CPU intensive process is allocated CPU time. As its burst time is high, it takes time
to complete.
 While the CPU intensive process is being executed, the I/O bound processes complete their
I/O operations and are moved back to ready queue.
 However, the I/O bound processes are made to wait as the CPU intensive process still hasn’t
finished. This leads to I/O devices being idle.
 When the CPU intensive process gets over, it is sent to the I/O queue so that it can access an
I/O device.
 Meanwhile, the I/O bound processes get their required CPU time and move back to I/O queue.
 However, they are made to wait because the CPU intensive process is still accessing an I/O
device. As a result, the CPU is sitting idle now.
Hence in Convoy Effect, one slow process slows down the performance of the entire set of
processes, and leads to wastage of CPU time and other devices.
To avoid Convoy Effect, preemptive scheduling algorithms like Round Robin Scheduling can be
used – as the smaller processes don’t have to wait much for CPU time – making their execution
faster and leading to less resources sitting idle.
(ii) Difference between CALL and JUMP instructions

CALL instruction is used to call a subroutine. Subroutines are often used to perform tasks that need
to be performed frequently. The JMP instruction is used to cause the PLC (Programmable Logic
Control) to skip over rungs.
The differences Between CALL and JUMP instructions are:
S NO. JUMP CALL
Program control is transferred to a

memory location which is in the main Program Control is transferred to a memory
1. program location which is not a part of main program
Immediate Addressing Mode + Register Indirect

2. Immediate Addressing Mode Addressing Mode
Initialisation of SP(Stack Pointer) is

3. not mandatory Initialisation of SP(Stack Pointer) is mandatory
Value of Program Counter(PC) is not Value of Program Counter(PC) is transferred to

4. transferred to stack stack
After JUMP, there is no return

5. instruction After CALL, there is a return instruction
6. Value of SP does not changes Value of SP is decremented by 2
10 T states are required to execute this

7. instruction 18 T states are required to execute this instruction
3 Machine cycles are required to 5 Machine cycles are required to execute this
8. execute this instruction instruction
07. (c)
Sol: Boundary scan standard:
Scan path DFT technique is a concept. Various manufacturers can implement scanpath in different
ways.
Suppose I have 10 ICs (manufactured by different companies, different companies use different
testing techniques )on a board how do I test my board
-unless companies agree among themselves about same standard, it is impossible to come up with
a feasible way to test IC on a board.
Boundary scan standard
Joint Test Action Group (JTAG) standard
or
JTAG port
or
IEEE 1149.1 standard
– JTAG port can operate at chip level, board level and system level
IC1 IC2
Test
instruction
and test date IC3
IC4
BOARD
– Manufacture some additional circuitry around every chip called as wrapper

– Wrapper will decode the test instruction and take appropriate action.
– Wrapper will allow inter operability among these ICs in terms of test communication.
EX: Test instruction and test data fed the 1st chip will be understood by wrapper and if it is not for
1st chip then it is bypassed to 2nd chip and process continues.
– This standard allows test instruction and test data to be serially fed into a component under test.
– JTAG port allows system interconnects be tested separately from components .
BSC
Boundary
scan cell Internal
logic I/O
I/O (IC) Pins
Pins
Sin Sout
M
TD1 IR U TDO
X
Bypass Reg
TRST*
TMS TAP Controller TCLK
IEEE
Fig: 1149.1 Wrapper Architecture
TAP controller: Controls TD1, TDO, TCLK, TMS, TRST

TD1: Test data input
TDO: Test data output
TMS: Test model select
TCLK: Test CLK
TRST*: Test restart (optional)
SIN, Sout provide internal IC scan path

Sout
IN
0 21
Out
MUX
1
0 D Q D Q
21 Mode
A B
MUX Sout
1 Q
SIN Shift Clk Update IN BSC out
Fig: Boundary scan cell SIN
Various modes of BSC:

1. Normal mode
Mode = 0  OUT = In
2. Scan mode:
Shift = 1, clk activated  Sout = SIN
3. Capture mode:
Shift = 0, clk activated  QA = IN
4. Update mode:
Mode = 1, update activated  OUT = QA
Board level testing
Chips testing Interconnections

(INTEST) between chips
(EXTEST)
EXTEST: Suppose there are two chips on board
Internal Internal
logic logic
M M
TDI Registers U TD1 Registers U
TDO TDO
X X
TAP Controller TAP Controller
Step 1: Scan mode
Step 2: (i) update mode
(ii) capture mode
Step 3: Scan mode
if the interconnection is faulty, the bit pattern sent and received are not same
INTEST Bypass
Internal Internal
logic logic
Sin Sout M
M
TD1 Reg U
Reg U TDO
TD1 TDO X
X
TMS TAP Controller Tclk
TAP Controller
– bits fed at TD1 are bypassing
the scan path and straight
away sent to TD0 and then
Step 1: Scan mode to next chip
Step 2: (i) update mode
(ii) capture mode
Step 3: Scan mode
08. (a)
K
Sol: CE = 1  =0 given  = 0.5
s(s  10)
s2 + 10s + K = 0
K = 2n
2n = 10
10
n = = 10
2
n = 10
 K = 102 = 100
 4
ts =  = 0.8 sec
 n (0.5)(10)
   
MP = exp   = 16.3%
 1    0.5
2
 
tp =  = 0.362 sec
n 1   2 10 1  0.5 2
K = 100, ts = 0.8 sec, MP = 16.3%, tp = 0.362 sec
08. (b)
Sol: One Bus organization –
BUS 1
PC Reg.A Reg.B
GENERAL
IR
PURPOSE
REGISTERS ALU
MAR
Memory
bus
MDR
Fig. One Bus Organization
In one bus organization, a single bus is used for multiple purpose. A set of general purpose register,
program counter, instruction register, memory address register(MAR), memory data register(MDR) are
connected with the single bus. Memory read/write can be done with MAR and MDR. The program
counter points to the memory location from where the next instruction is to be fetched. Instruction
register is that every register will hold the copy of the current instruction. In case of one bus
organization, at a time only one operand can be read from the bus.
As a result of that, if the requirement is to read two operands for the operation then read operation need
to be carried twice. So that’s why it is making the process little longer. One of the advantages of one bus
organization is that, it is one of the simplest and also this is very cheap to implement. At the same time a
disadvantage lies that it has only one bus and this “one bus” is accessed by all general purpose registers,
program counter, instruction register, MAR, MDR making each and every operation sequential. No one
recommend this architecture now-a-days.
Two Bus organization:

Two overcome the disadvantage of one bus organization an another architecture was developed known
as two bus organization. In two bus organization there are two buses. The general purpose register can
read/write from both the buses. In this case, two operands can be fetched at the same time because of the
two buses. One of bus fetch operand for ALU and another bus fetch for register. The situation arises
when both buses are busy fetching operands, output can be stored in temporary register and when the
buses are free, particular output can be dumped on the buses.
There are two versions of two bus organization i.e., in-bus and out-bus. From in-bus the general purpose
register can read data and to the out bus the general purpose registers can write data. Here buses gets
dedicated.
BUS 1
PC
ALU
GENERAL
IR
PURPOSE
REGISTERS temporary
MAR register
Memory
bus
MDR
Fig. Two Bus Organization BUS 2
IN-BUS
PC Reg-A
GENERAL
IR
PURPOSE
REGISTERS
MAR ALU
Memory
bus
MDR
OUT-BUS
Fig. Two Bus Organization
Three Bus organization:

In three bus organization we have three bus, OUT bus1, OUT bus2 and a IN bus. From the out buses we
can get the operand which can come from general purpose register and evaluated in ALU and the output
is dropped on In Bus so it can be sent to respective registers. This implementation is a bit complex but
faster in nature because in parallel two operands can flow into ALU and out of ALU. It was developed
to overcome the “busy waiting” problem of two bus organization. In this structure after execution, the
output can be dropped on the bus without waiting because of presence of an extra bus. The structure is
given below in the figure.
BUS 1
ALU
PC
GENERAL
PURPOSE
REGISTERS IR
MAR
Memory
bus
MDR
OUT BUS 1
OUT BUS 2 Fig. Three Bus Organization
The main advantages of multiple bus organizations over single bus are as given below.
1. Increase in size of the registers.
2. Reduction in the number of cycles for execution.
3. Increases the speed of execution or we can say faster execution.
08. (c)
3  4z 1 1 2
Sol: Hz    
 
1
1  3z 1  0.5z 1

1  0.5z 1
1  3z 1
(i) Causal, unstable: The ROC is |z| > 3

Im
z-plane
Re
0.5 3
h(n) = (0.5)n u(n) + 2(3)n u(n)

(ii) Anti-Causal, unstable: The ROC is |z| < 0.5

Im
Re
0.5 3
h(n) = – (0.5)n u(–n–1) – 2(3)n u(–n–1)
(iii) Non-Causal, Stable: The ROC is 0.5 < |z| < 3

Im
Re
0.5 3
h(n) = (0.5)n u(n) + 2(3)n [–u(–n – 1)]
08. (d)
Sol: y(n) = x(n) circular convolution h(n)
Apply DFT
Y(k) = X(k)H(k)
y(n) = IDFT[Y(k)]
x(0) = 1 2 X(0) = 4
x(1) = 1 2 X(2) = 0
x(2) = 1

W 1 0 –1 W4  1
4
X(1) = 0
–1 W 1   j
x(3) = 1 4 0
X(3) = 0
–1 –1 W4  1
X(k) ={4,0,0,0}
h(0) = 1 2 H(0) = 2
h(1) = 0 0 H(2) = 2

W 1 0 –1 W4  1
h(2) = 1 4
H(1) = 0
–1 W 1   j
h(3) = 0 4 0
H(3) = 0
–1 –1 W4  1
H(k) = {2,0,2,0}
Y(k) = X(k)H(k) = {8,0,0,0}
Y(0) = 8 8 8 y(0) = 2
Y(1) = 0 0 8 1/4 y(2) = 2
W4  1 8 –1 W4  1 8 1/4
Y(2) = 0
y(1) = 0
–1 W 1   j 1/4
Y(3) = 0 4 0 –1 8
y(3) = 0
–1 W4  1 1/4
y(n) = {2,0,2,0}

ESE - 2020 Mains Test Series: Electronics & Telecommunication Engineering

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1 TEST CODE: 608

ESE - 2020 Mains Test Series

Combining the above two figures

y1(t)  y(t – t0).

For n = – to n = –6, h(n) = 0 and for n = –5 to n = , h(n) = 1

 hn   0  0  ...  1  1  1  ...  

So, the given system is unstable.

D FF/reg F FF/reg Digital

Clock period (Tclk) = slowest combinational block

printf("enter the value of n:");

Mapping sections ‘C1’ of the Nyquist contour:

Mapping section C2 of the Nyquist contour:

Mapping section C3 of Nyquist contour:

Combining all the above sections

Shifting doesn’t change the area under x(t) or x(t).

1110 00100000000 11111

From duality property

strlen() computes string's length

strcpy() copies a string to another

strcat() concatenates(joins) two strings

strcmp() compares two strings

strlwr() converts string to lowercase

strupr() converts string to uppercase

Strings handling functions are defined under "string.h" header file.

(ii) Classification of Number System

1. Positional (or Weighted) Number System:

1358 = 1 x +3x +5x +8x

13.58 = 1 x +3x +5x +8x

2. Non-Positional (or Non-weighted) Number System:

 retain only one fault from the equivalence set.

(ii) (1). Given 2u(t + 2) – 2u(t – 3)

–2u(t–3) 2u(t+2) –2u(t–3)

r(t) –r(t –1)–r(t – 3)+r(t – 4)

Memory Address Decoding

No. of addressing modes= 16

Memory size = 2m MB = 2m+20 B

Level User Executable Programs

Process Arrival CPU Burst Time

Process Arrival CPU Burst Time

Key Differences between Preemptive and Non-Preemptive Scheduling:

Once resources (CPU Cycle) are

Process can be interrupted Process cannot be interrupted

If a process having high If a process with long burst time

Flexibility Flexible Rigid

Cost cost associated no cost associated

CPU In preemptive scheduling, It is low in non preemptive

Examples of preemptive Examples of non-preemptive

RMS Value = Power  56  7.4833

Root loci is shown in figure below,

Slope change table of the Bode plot

For the range 1  t  5

y(t) = 0 for t < 3

0.0776  0.2328z 1  0.2328z 2  0.0776z 3

(ii) The signal shown in figure (a) can be expressed as:

Steps are as following below:

(ii) Difference between CALL and JUMP instructions

Program control is transferred to a

Immediate Addressing Mode + Register Indirect

Initialisation of SP(Stack Pointer) is

Value of Program Counter(PC) is not Value of Program Counter(PC) is transferred to

After JUMP, there is no return

6. Value of SP does not changes Value of SP is decremented by 2