ECE270: Embedded Logic Design

Mid-Semester Lab Exam (15 Marks)

Date: 17/10/2020
Deadline: 8 PM (Read it as 7.45 pm): 100% Penalty thereafter.
Where to submit: Google Classroom
What to submit: Single PDF containing well-commented Verilog Code, well-
commented test-bench and readble simulation waveforms (Do not crop desktop
address)

1. In the lab 7, we have implemented the floating point arithmetic. This exam can
be considered as extension of the lab.

• Problem 1.1: Implement the following function and demonstrate the

functionality using testbench for two sequential and different
combinations of X and T (Note that X < T and both are positive
integers)
𝑋 𝑋 𝑋 2
𝑄(𝑋, 𝑇, 𝑁) = + √[ − ( ) ]
𝑇 𝑇 𝑇
Deliverables (Single PDF file):
I. Well-commented Verilog Code
II. Well-commented Testbench
III. Simulation waveform indicating two combinations of X and
T in one window. Simulation waveform should contain
address of the desktop (see example below).
Otherwise solution will not be evaluated.
IV. Solution will not be evaluated if handshake between valid
and ready is not correct.

7 Marks
• Problem 1.2: Extend the above to implement the following function.
Demonstrate the functionality using testbench for two different
combinations of X, N and T (Note that X < T< N and all are positive
integers)

𝑋 log 𝑁 1 𝑋 4log 𝑁
𝑄 (𝑋, 𝑇, 𝑁) = +√ min { , [ − √ ]}
𝑇 𝑇 4 𝑇 𝑇

Deliverables (Single PDF file):

I. Well-commented Verilog Code
II. Well-commented Testbench
III. Simulation waveform indicating two combinations of X, N
and T in one window. Simulation waveform should contain
address of the desktop. Otherwise solution will not be
evaluated.
IV. Solution will not be evaluated if handshake between valid
and ready is not correct

Note that you must submit separate solutions for Problem 1.1 and
Problem 1.2.
8 Marks