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Compiler Construction
(CS-403)
INSTRUCTOR: MS. SABA HANIF
INSTITUTE OF COMPUTER SCIENCE AND
INFORMATION TECHNOLOGY
THE WOMEN UNIVERSITY, MULTAN
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Lecture No 3
 The Front End 3
 To recognize a valid sentence in some CFG,
we reverse this process and build up a parse
 A parse can be represented by a tree: parse
tree or syntax tree
Parse
Production Result
goal
1 expr
2 expr op term
5 expr op y
7 expr – y
2 expr op term – y
4 expr op 2 – y
6 expr + 2 – y
3 term + 2 – y
5 x+2–y
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Syntax Tree
goal 5

x+2-y expr

expr op term

expr op term – <id,y>

term + <number, 2>

<id,x>
Abstract Syntax Trees 6

 The parse tree contains a lot of unneeded

information.
 Compilers often use an abstract syntax tree
(AST).
Abstract Syntax Trees 7

+ <id,y>
<id,x> <number,2>

 This is much more concise

 Abstract Syntax Trees 8

+ <id,y>
<id,x> <number,2>

 AST summarizes grammatical structure without the details of

derivation
 Abstract Syntax Trees 9

+ <id,y>
<id,x> <number,2>

 ASTs are one kind of intermediate

representation (IR)
The Back End 10

IR Instruction IR Register IR Instruction machine

selection allocation scheduling code

errors
The Back End 11

 Translate IR into target machine code.

 Choose machine (assembly) instructions to
implement each IR operation
The Back End 12

 Ensure conformance with system interfaces

 Decide which values to keep in registers
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IR Instruction IR Register IR Instruction machine

selection allocation scheduling code

errors
Instruction Selection:
 Produce fast, compact code.
 The Back End 14

IR Instruction IR Register IR Instruction machine

selection allocation scheduling code

errors
Instruction Selection:
 Take advantage of target features such as addressing modes.
 The Back End 15

IR Instruction IR Register IR Instruction machine

selection allocation scheduling code

errors
Instruction Selection:
 Usually viewed as a pattern matching problem – dynamic
programming.
 The Back End 16

IR Instruction IR Register IR Instruction machine

selection allocation scheduling code

errors
Instruction Selection:
 Spurred by PDP-11 to VAX-11 - CISC.
 The Back End 17

IR Instruction IR Register IR Instruction machine

selection allocation scheduling code

errors
Instruction Selection:
 RISC architecture simplified this problem.
 The Back End 18

IR Instruction IR Register IR Instruction machine

selection allocation scheduling code

errors

Register Allocation:
 Have each value in a register when it is used.
 The Back End 19

IR Instruction IR Register IR Instruction machine

selection allocation scheduling code

errors

Register Allocation:
 Manage a limited set of resources – register file.
 The Back End 20

IR Instruction IR Register IR Instruction machine

selection allocation scheduling code

errors
Register Allocation:
 Can change instruction choices and insert
LOADs and STOREs.
 The Back End 21

IR Instruction IR Register IR Instruction machine

selection allocation scheduling code

errors

Register Allocation:
 Optimal register allocation is NP-Complete.
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IR Instruction IR Register IR Instruction machine

selection allocation scheduling code

errors

Instruction Scheduling:
 Avoid hardware stalls and interlocks.
 The Back End 23

IR Instruction IR Register IR Instruction machine

selection allocation scheduling code

errors
Instruction Scheduling:
 Use all functional units productively.
 The Back End 24

IR Instruction IR Register IR Instruction machine

selection allocation scheduling code

errors
Instruction Scheduling:
 Optimal scheduling is
NP-Complete in nearly all cases.
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Thank You!