Dai hoc Bach Khoa TP.HCM DE THI CUOI KY. NH 2017-2018 Khoa Dign — Dign Tir ‘Mén: Hg théng diéu khién Bé mon DKTD 14/06/2018 -000—- Thar gian lam bai: 90 phist (Sinh vién duge str dung ti ligu) Cau 1: 2.54) ‘Thiét ké mach gidi ma dia chi va cho hé théng (8-bit dja chi A7-A0; 8-bit dit ligu D7-D0; RD, WR trén 2 chén rigng biét) két néi véi cdc module bén dudi. Ghi r6 két ndi chan CS, WR, RD tdi cdc module va dja chi bat ddu, dia chi két thic ciia cdc module (khéng gidi ma dia chi céc kénh): 1/ Module 1: 16 kénh ADC 16-bit 4/ Module 4: 16 kénh Encoder 32-bit 2/ Module 2: 4 kénh DAC 12-bit 5/ Module 5: 4 kénh Digital Input 8-t 3/ Module 3: 16 kénh PWM 10-bit 6/ Module 6: 2 kénh Digital Output 8-bit Cau 2; (2,54) Viét chuong trinh Verilog tén demxung(clk, MODE, Pulseln, D) thyc hign vige dém xung. kénh Pulsefn nhu sau: ~ Dau vao tin higu xung clock clk c6 tan sO. 1 MHz. - Dau vao tin higu Pulseln cé tan sé thay 461 = Badu vio MODE, néu MODE = 0: dém s6 xung trong thdi gian 10ms, néu MODE = dém sé xung trong thai gian Is. (MODE duge cai dat gid tri lic ban du, khong thay d6i ‘trong qua trinh chay) = Dau ra dir ligu 16 bit: D[15:0} (don vi: s6 xung). Dit ligu ng ra duge cdp nhgt sau mdi chu ky 10ms hode 1s tiy theo gid trj cua MODE. Cau 3: (2,54) ‘Trong yéu cau thiét ké hé thong ding STM32F4 ta cn str dung Port PD[7:0] cho chite nanj UART va CAN, Port PA[5:4] cho chite ning DAC 2 kénh, Hay cdu hinh cdc thanh ghi hé thong di sit dung 3 chite nng nay trén céc chin tir PDO-PD7 va PA4-PAS (chi ¥ khéng duge ding ede chén khac) vai cée yéu edu sau: + Chird chan nao sir dung UART, chan ndo sit dung CAN, chin nao sit dung 2 kénh DAC = Cu hinh thanh ghi cho phép xung clock dé hoat dng 3 chite nang trén - Céu hinh thanh ghi chan 10 dé Iya chon chie nang phi hop Cfiu 4; (2,54) Trong cdu hinh két ndi & Cau 3, cdc ham xuat gid tri DAC va nhan dit ligu tir UART duoc cung cfip nhu sau: = Ham xudt cdc kénh DAC: void write_dac (int channel, int value). Trong 46 channel c6 gid trj ti | dén 2 tuomg img voi 2 kénh. = Him nhan N byte tir b6 dém rxbuff qua UART: void receive_data (chat *rxbuf, int N). Biét gid tr] DAC dang ASCII 4 bytes va format chudi dit Higu nhan vao nhu sau: DAC 1 | [DAC2] OxOD | Ox0A (Abyte) | (byte) | (4byte) | (ibyte) | (byte) Vidt chuong trinh doc dif ligu tir UART, sau dé chuyén déi gid tri ASCII sang dang int va xudt ra 2 kénh DAC. NBM f) eases seligagin Vink HeoDAP AN Clu 1: (2,54) = Ghi tim dia chi ding cho 6 module va so 43 két 74138 GH |< gg SBOEGODER = Vé so dé giai ma dang 6 module “iu 2; (2,54) module demxung (clk, MODE, PulseZn, D) input clk, MODE, Pulserns output reg [15:0] Dz reg [15:0] temp reg [21:0] cnt reg prePulseIn always @ (posedge clk) begin prepulsein <= Pulsein? if ({prePulsein, PulseIn] temp = temp + 17 ent = cnt + 17 2"b01) if ((cnt==10000) && (MODE == 0)) b = 0; ent D temp end else if ((cnt: ent D = temps temp = 07 end 000000) && (MODE = end endmodule (Cau 3: (2,50) = Chi 1 chan két. PDO- PDI: PDS-PD6: — UART2 PAd—PAS: DAC = Cau hinh thanh ghi xung clock RCC_AHBIENR |= (1<<0) | (1<<3); RCC_APBIENR |= (I<<17) | (1<<25); RCC_AHBIENR |= (1<<29); * CANI i 74138 (15d) os ene (id) egin = 1)) begin (5a) (ia) ficlock cho PA va PD Helock cho UART2 va CAN} Hclock cho DAC- Cau hinh mode chire nang (id) GPIOD_MODER [= (2<<0) | (2<<2) | (2<<10) | (2<<12); GPIOA_MODER |= (3<<8) | (3<<10); GPIOD_AFRL |= (9<<0) | (9<<4) | (7<<20) | (7<<24); au 4: (2. char rxbuff [11]; int16_t dacvall,dacval2; main(){ while(1){ receive (rxbuff, 11); if ((exbuff[$]==05 90) && (rxbuff[1]==980A)) dacvall = (rxbuff[0] - 48)*1005 + (rxbuff[1] - 48)*100 + (rxbuff£[2] - 48)*10 + (xxbuff£[3] - 48); dacval2 = (rxbuff[5] - 48)*1000 + (rxbuff[6] - 49)*100 + (rxbuf£[7] - 42)*10 + (rxbuff[8] - 48) dac_write(1,dacvall); { dac_write (2,dacval2); ) ) eet 1s Nguyén Vinh Ho