| 5 / OPERATIONAL AMPLIFIERS ‘The operational amplifier'-* (abbreviated op amp) is a direct-coupled high-gain amplifier to whieh feedbuck is added to control its overall response characteristic. It is used to perform a wide variety of linesr funetions (and also some nonlinear operations) and is often referred to as the basic linear (or more accurately, analog) integrated circuit. Ite many applications are detailed in the following chapter. ‘The integrated operational amplifier has gained wide acoeptance fas a versatile, predictable, and economic aystem building block. It offers all the advantages of monolithic integrated cirouits: small size, high reliability, reduced cost, temperature tracking, and low offset voltage and current (which terms are defined carefully, later in this chapter). ‘A detailed anilysis of the several stages in an or aur is made, Experimental methods for measuring oF amp parameters are given. ‘The frequency response and methods of compensation are discussed 15-1 THE BASIC OPERATIONAL AMPLIFIER ‘The sehematie diagram of the oP awP is shown in Pig. 15-1a, and the equivalent circuit in Fig. 15-10, A large number of operational ampli- fiers have a differential input, with voltages Vs and V; applied to the inverting and noninverting termingls, respectively. A single-ended amplifier may be considered as a special ease where one of the input terminals is grounded. Nearly all op aups have only one output termin Ideal Operational Amplifier The idea! oP anp has the following characteristic so502 / INTEGRATED ELECTRONICS See. 15:1 1. Tnput resistance R, 2, Output resistance Ry = 0 3, Voltage gain Ay = — 2 4. Bandwidth = = 5. Perfect balance: V, = 0 when Vi = Vs 6, Charactoristies do not drift with temperature In Fig. 15-2a we show the idea! operational amplifier with feedback impedances @ and 2’) and the + terminal grounded, This is the basie inverting circuit. This topology represents voltage-shunt feedback, and is discussed in See, 13-12. ‘The circuit of Fig. 15-2a is a generalization of Fig. 13-20a, with the single- transistor replaced by the multistage om amp and the resistors R, and replaced by impedances Z and Z', respectively. From Bq. (13-79) the voltage gain Avy with feedback is given by Zz 5 Ayn —% (asa) An instructive alternative proof of this equation is obtained as follows ¢ Ri e, the current I through Z also passes through 2m indieated in Fig, 16-20. Ih addition, we note that Vs = Vs/Ay—» 03s |Ay|_—> s, so that the input is effectively shorted. Hence ve lag Aun VTE ~~] in agreement with Bq, (15-1) ‘The operation ofthe circuit may now be destrbed inthe following terms At the input tothe amplifier proper there exists a nrual ground, or short ero i ae Yonah ais ae tla 151 (0) bose o > 7 Reel oie ep oes heya eas repens ead 2 Creve ¥). Teopen- g cireit voltage gains A, and -n, Re ain under load is Ay.See. 15:1 (OPERATIONAL AMPLIFIERS. / 503, ® Fig, 15:2 (a) Inverting operational amplifier with edded voltage-shunt feedback. (b) Virtual ground in the operational emplifer. ‘The term “virtual” is used to imply that, although the feedback from output to input through 2’ serves to keep the voltage V, at zero, no current actually fiows into this short, The situation is depicted in-Fig. 15-2b, where the virlual ground is represented by the heavy double-headed arrow. This figure does not represent a physical cireuit, but it is eanvenient mnemonic aid from which to calculate the output voltage for a given input signal. This symbolism is very useful in connection with analog computations discussed in Sec. 16-1. Prac | Inverting Operational Amplifier Equation (15-1) is valid only it the voltage gain is infinite. It is sometimes important to considers physical amplifier which does not satisfy these restrictions. a Vig. 15-8 the amplifier in Fig. 15-20 is replaced by its smallsignal model, with [ay] # =, Rex =, and 2, #0. ‘The symbol A, is the open-circuit (unloaded) voltage gain. ‘The impedances shown shaded indicate the effet of Z” on the input and output af the amplifies, where use is made of the Miller theorem (See. $1). Using these Miller impedances in place of 2" in Fig. 153, the following expresion for the closed-loop gain is obtained (Prob. 15-1). An = Y= WAN FTF) a chere the Y's are the admittances corresponding to the Z's (fr example, ¥'= 1/2) and where the voltage gain Ay taking the loading of 2° to account, is given by A+ RY Ay A ERY asa) Note that if Ry = Oor ¥’ = 0 (Z’ = =), the loading is effective Ay = Ay Also observe that as |A,|—> ©, then |Ay|—> = and y removed and Aya in agreoment with Bq. (15-1).S04 .! INTEGRATED ELECTRONICS See. 15:1 — % Noninvrtng terminal Fig. 15:3 Circuit model of the o- aur of Fig. 15.1, (The shaded impedances are the Miller replacements for Z’.) Noninverting Operational Amplifier Very often there is a need for an amplifier whose output is equal to, and in phase with, the input, and in addition Ry = @ and R, = 0, so that the source and load are in effect isolated. An emitter follower approximates these specifications, More ideal characteristies ean be obtained by using an operational amplifier having a noninverting terminal for signals and an inverting terminal for the feedback voltage, as shown in Fig. 15-4 If we assume again that Rj = and ~Ay = ©, we have k oper! Since ¥, = Av(V1 — V.), thou for a finite V’, it follows that V, = 1 (there is ‘virtual short at the input terminals) and Ve_ Ve R4R Ay vir —¥ as) Hence the closed-loop gain is always greater than unity, If R Ri = 0, then Ay; = +1 and the amplifier aets as a vollage follower. In the analysis of noninverting op amp eizeuits we shall use the facts that (1) no current flows into either input aud (2) the polentials of the two inpuls are equal, © and/or ZR Me Fig. 1.4 Noninverting operational n=l ay Ly, amplifier with resistive feedback. — If > Rr, the output follows the 3 input; Pe = VSec. 15-2 OPERATIONAL AMPLIFIERS / 505 15:2 THE DIFFERENTIAL AMPLIFIER ‘The function of a differential amplifier’ (abbreviated prev as) is, in general, to amplify the difference between two signals. The need for pier anurs arises in many physical measurements where response from de to many megaherts js required. It ip also the basic stage of an integrated operational amplifier with differential input. Figure 15-5 represente a linear active device with two input signals vs and one output signal », each measured with respect to ground. Tn an ideal irr wp the output signal », should be given by = Adler ~ 8) (15-5) where Ay i the gain of the differential amplifier. ‘Thus it is seen that any signal which is common to both inputs will have no effect on the output voltage. However, practical nirr amp cannot be deseribed by Eq. (15-5), because, in general, the output depends not only upon the difference signal vg of the two signals, but also upon the average level, called the common-mode signal v, where memo and = Ho +m) (15-6) For example, if one signal is +50 x and the second not be exactly the same as if 7) = 1,050 aV and v5 difference v4 = 100 uV is the same in the two eases —50 nV, the output will 1950 uV, even though the The Common-mode Rejection Ratio The foregoing statements are now clarified, and a figure of merit for a difference amplifier is introduced. ‘The output of Fig. 15-5 ean be expressed as a linear combination of the two input voltages ap Avs + Aas as-7) where 4,(4a) is the voltage amplification from input 1(2) to the output under ‘the condition that input 2(1) is grounded. From Eqs. (15-8) wentiw and =o i 58) If these equations are substituted in Eq. (15-7), we obtain b= Ae t Aa (5-9) where Ape HAr— 4A) nd Ae AL As as-10) Fig, 15-5 The output is linear function of »; end ss for an ideal differential amplifier; t= alos — 29)506 / INTEGRATED ELECTRONICS Sec. 15:2 ‘The voltage gain for the difference signal is Ae, and that for the common-mode signal is 4, We can moasuro As directly by setting 11 = —» = 0.5 V, so that 1 = 1'V and, = 0. Under those conditions the measured output volt. age 0 gives the gain Ay for the difference signal [Eq. (16-9)]. Similarly, if wre setm1 = t= 1, thenay = 0,0,=1V, and1 =A. The output voltage now is direct measurement of the common-mode gain A, Clearly, wo should like to have 4g large, whereas ideally, A, should equai zero. A quantity called the common-mode rejection. ratio, which serves as a figure of merit for a p1eP ame, is defined by oun = 9 =| 44} san From Eqs. (15-9) and (15-11) we obtain an expression for the output in the following form: wm do (1422 (1512) ‘From this equation we see that the amplifier should be designed so that » is large compared with the ratio of the common-mode signal to the difference signal. For example, if » = 1,000, % = ImV, andy = 1 pV, the second term: in Eq. (15-12) is equal to the first term. Hence, for an amplifier with « common-mode rejection ratio of 1,000, a 1-nV difference of potential between the two inputs gives the same output as a 1-mV signal applied with the same polarity to both inputs. $$ EXAMPLE (a) Consider the situation referred to above, where the first set of Slamals is ¢) = 4-80 2V and ps = —50 pV and the seeand set is vs = 1,050 xV and % = 950 nV. If the common-mode rejetion ratio is 100, ealeulate the percentaxe difference in outpat voltage obtained forthe two sets of input signals. (8) Repeat part aif p = 10,000. Solution a. In the first case, v= 100 xV and v, = 0, so that, from Eq. (16-12), m= 100d, AY. Tn the seeond ease, x9 = 100 4, the same value as in part a, but now se = +4(1,050 + 850) = 1,000 xV, so that, from Bq. (1512), vex rns(t $8) mas(ie 22) a ‘These two measurements differ by 10 percent. , Por p = 10,000, the seeond set of signals results in an output n= 100A +10 x 10-) AV whereas the frst set of signals gives an output » ‘Wo measurements now differ by only 0.1 percent ——— 0A, KV. ‘Hence theSee. 15:5 OPERATIONAL AMPUFIERS / 507 15-3 THE EMITTER-COUPLED DIFFERENTIAL AMPLIFIER ‘The cireuit of Fig. 16-6 is an excellent prev au ifthe emitter resistance R, is large. This statement ean be justified as follows: If Var = Vw = Vs, then from Eqs. (15-6) and (15-9) we have Ve= Va — Vaz = 0 and Ve= A.V However, if R, = ©, then, because of the symmetry of Fig, 15-6, we obtain Iq = In = 0. Since Lin & Loy then Ig ~ Iq and it follows that Ve = 0. Hence the common-mode gain A, becomes zero, and the common-mode rejec- tion ratio is infinite for Re = © and a symmetrical eirouit We now analyze the emitter-coupled circuit for a finite value of Re Ae can be evaluated by setting Var = Vig = V, and making use of the symmetry of Fig. 1-6. This circuit can be bisected as in Fig. 15-7a. An analysis ofthis circuit (Prob, 15-10), using Eqs. (8-67) to (6-69) and neglecting the term in Ire in Haq, (8-68), yields habe — hy) Re TRC Ty) + Re + hid Dhak FD, (1618) provided that heels <1. Similarly, the difference mode gain Ay ean be obtained by setting Vi = —Vez = V./2. From the symmetry of Fig. 15-6. ‘we see that, if Vay = — Viz then the emitter of each transistor is grounded for small-signal operation. Under these conditions the cireuit of Vig. 15-76 ean be used to obtain 4g. Hence Ag = Ve BeBe MV, OR + he A (as18) provided he <1. ‘The common-mode rejection ratio can now be obtained dosing Eqs. (15-11), (15-18), and (15-14). ‘From Eq, (15-18) itis seen that the common-mode rejection ratio increases with Ra predicted above. ‘There are, however, practical limitations on the ‘magaitude of 2 because of the quiescent de voltage drop across it; the emitter508 / INTEGRATED ELECTRONICS See. 15:9 Fig. 157 Equivalent circuit fore symmetrical differential omplifier uted to determine (2) the common-mode gain ae and (b) the difference goin as @ ® supply Vex must become larger as FR, is increased, in order to maintain the quiescent current at its proper value. If the operating currents of the transis- tors are allowed to decrease, this will lead to higher hi, values and lower values of hye Both of these effects will tend to decrease the eommon-mode rejec- tion ratio. Differential Amplifier Supplied with @ Constant Current Frequently, in practice, Z, is replaced by a transistor cireuit, as in Fig. 15-8, in which Rs, Rs, and Rs ean be adjusted to give the same quiescent conditions for Ql and Q2 as the original circuit of Fig. 15-8. This modified cireuit of Vig. 15-8 presents ‘a very high effective emitter resistance R, for the two transistors QI and Q2. Since 2, is also the effective resistance looking into the eolleetor of transistor Q3, itis given by Eq. (8-70). In See. 8-15 it is verified that R, is hundreds of kilohms even if Rs is as small as 1K. We now verify that transistor Q3 acts as an approximately constant eur 9. 15-8 Differential am- plifier with constant-curr stage inthe emitter circuit Nominally, Rex = RasSec 15:3, OPERATIONAL AMPLIFIERS ; 309 rent source, subject to the condition that the base current of Q3 is negligible. Applying KVI to the base eireuit of Q3, we have Re TsR+ Vans = Vo + (Vax ~ V0) pa, 5.15) where Vo isthe diode voltage, Hense 1 (Verka , VoRs ; Tom tom He (ete + Ree, ~ Von) (15.16) TF the cireuit parameters are chosen so that Vor, Bag, = Yom sap then Vek I hh + RD (15-18) Sinco this eurent is independent ofthe signal voltages Vin and Vay then 8 acts to supply the mire Aap consisting of Ql and Q2 with the constant current To. The above result for Io bas been rendored independent of temperature because of the added diode D. Without D the current would vary with tem- perature because Vaer decreases approximately 2.5 m¥,"°C (See. 5-8). The diode has this same temperature dependence, and hence the two variations cancel each other and Jo does not vary appreciably with temperature. Since the eutin voltage Vn of a diode has approximately the same value as the base- to-emitter voltage Var: of a transistor, then Eq. (15-17) cannot be satisfied with a single diode. Hence two diodes in series are used for Tp (Fig. 15-11) Consider that Q1 and Q2 are identical and that Q3 is» true constant- current source. Under these circumstances we can demonstrate that the ‘common-mode gain is aero, Assume that Vu = Van = Vs, so that rom the symmetry of the circuit, the colleetor current I. (the inerease over the quies- cent value for V, = 0) in QI equals the current Za in Q2. However, since the total current ineroase [a + La = 0 if Jo = constant, then Jey = Za = 0 and Ae = Va'Ve = — Tae Ve = 0. Practical Considerations* In some applications the choice of Vax and Far as the input voltages is not realistic because the resistances Ray and Rey represent the output impedances of the voltage generators Vax and Vix. Tn such a case we use as input voltages the baso-to-ground voltages Viz snd Vis fof Qi and Q2, respectively. Tor the analysis of nonsymmetrical differential circuits the reader is referred to Ref. 4 ‘The differential amplifier is often used in de applications. to design de amplifiers using transistors because of drift due ¢o variations of hee, Vos, and Tooo with temperature. A shift in any of these quantities changes the output voltage and cannot be distinguished Srom a change in‘510 / INTEGRATED BECTRONICS See 15-4 input-signal voltage. Using the techniques of integrated cireuits (Chap. 7), it is possible to construct « pier axp with QI and Q2 having almost identical characteristics. Under these conditions any parameter changes due to tem- perature will eancel and the output will not vary Differential amplifiers may be eaéaded to obtain larger amplifications for the difference signal. Outputs Va. and Vsz ate taken from each collector Gig. 15-8) and are coupled dircetly t6 the two bases, respectively, of the next stage (Fig. 15-11). ‘Finally, the differential amplifier may be used as un emitter-coupled phase inverter. For this application the signal is applied to one base, whereas the second buse is not excited (but is, of course, properly biased). ‘The output voltages taken from the collectors are equal in magnitude and 180° out of hase 15-4 TRANSFER CHARACTERISTICS OF A DIFFERENTIAL AMPLIFIER It is important to examine the transfer characteristiot (Ie versus Vai ~ Vrs) of the piv aut of Fig. 15-8 to understand its advantages and limitations. We first consider this circuit qualitatively. When Vas is below the outoff point of @1, all the current Zo flows through Q2 (assume for this discussion that, Vaz js constant). As Vox carries QI above eutoff, the current in Ql increases, while the current in Q2 decreases, and the sum of the currents in the two transistors remain constant and equal to Ja, The total range AV» over » the output ean follow the input is ReTo and is therefore adjustable through an adjustment of Io, From Fig. 15-8 we have Tus + Ins = ~Io Lond ; pe" [et Inveking 04 ‘mil @ R 2% Fig. 15-11 The Motorola MC1530 operationcl amplifier. In the analysis ell base currents are neglected. ‘The output V4 of the emitter follower is Va = Vane = Vaws — Vers = 452 — 0.7 = 3.82V ‘The Output Stage The last stage provides level translation and a sym- ‘metrical output swing (at low impedance) with respect to ground, When the differential input voltage Vis zero, the output V, should be zero. Of eourse, due to mismatch of Vie and hep, there will be some nonzero output voltage, which we consider in See. 15-7 ‘The voltage Vie = 3.82 V must be reduced to zero at the amplifieroutput while de coupling is maintained. We shall now demonstrate that this level translation ean be accomplished with the eireuit parameter values in Fig. 15-11. Note that Q7 is biased by D3 in the manner explained in See, 9-7. Hence, following our discussion in See. 9-7 with respect to Fig. 9-114, we find = Vor _ 6.0 -07 Te ra = 156 mA‘516 / INTEGRATED ELECTRONICS See, 15.5 = Veal Vi Fig. 15-12 The output stage of the MC1530, ‘The voltage from the base of QS to ground is Vows = Vows + Vou~ Vex = 0.7 +07 —6 = —4.60V ‘The currents in Ry and He are Vane — Vans _ 382 + 4.60 15 = enn = Var 8894 4.00 1.49 a Tor — Ty 56 — 140 = 0.16 mA . Finally, the de output voltage is Vo = Views + Treltso = ~4.60 + (0.16)(80) = 0.20 V ‘This calculated value for Vo is not to be taken too seriously, because we obtained Iye as the difforenee between two almost equal numbers, Such a subtraction can result i a large error in the small difference. Note that if Tre were 0.158 (instead of 0.16), then Vo = 0 (instead of 0.2 V). Also, Tiss greatly affected by small changes in the circuit, parameter values. Hence a. balancing technique (Sec. 19-6) is used to ensure that Vo = 0 for Vs = 0. To consider the output stage under conditions of an applied excitation, refer to Fig, 15-12, where vg represents the signal voltage at the emitter of Q8, Vans is the de voltage at this emitter, and Icy is the constant current supplied by Q7. The signal 0 is amplified by Q8 and is transmitted to the lotem-poleSee. 156 ‘OPERATIONAL AMPLIFIERS / 517 arrangement of QO and Q10. Tf v% is positive, then the current in Q9 is decreased and that in Q10 is increased, and current is taken from the load whieh is across the output and a, decreases. Similarly, if v is negative, the ‘current in Q9 is increased, that in @10 is decreased, current is delivered to the Toad, and u, increases. ‘For a very large positive v4, Q9 is eut off and Q10 is driven into saturation. Under these circumstances «= —Ver + Verse = —6 + 0.2 =— 538 V. Similarly, for » very large negative v, Q10 is cut off and QQ is driven into saturation, so that y= Vee — Versa = 6—0.2= +5,8V, ‘The maximum peak-to-peak output swing is 11.6 V. Note that the output stage is stabilized by means of the voltage-shunt feedback supplied by resistors Ry and Hue. Common-mode Voltage Swing We are going to show now that Views ‘and Vews set a limit on the input common-mode voltage swing View. Thi parameter is defined as the maximum peak input voltage that ean be applied to either input terminal without eausing abnormal operation or damage. The positive limit of Vicw depends on the collector voltage of the input stage; that is, Vows = Vane = 2.2 V. If View exceeds 2.2 V, then the eollector-to-base junetion of Q2 will become forward biased and Q2 may saturate, On the ‘other hand, if View becomes more negative than Vani + Voss = —3:14+0.7 = —2.44V then the collector of Q1 will become forward biased, and this will result in abnormal operation, ‘Therefore, when the power supplies are +6 V, the common-mode voltage swing for this amplifier should not exceed $2 V 15-6 OFFSET ERROR VOLTAGES AND CURRENTS In Seo, 15-1 we observe that the ideal operational amplifier shown in Fig, 15-1a is perfectly balanced, thet is, Ve= 0 when Vi = Vs. A real operational amplifier exhibits an unbalance eauised by a mismatch of the input transistors, ‘This mismatch results in unequal bias currents flowing through the input terminals, and also requires that an input offset voltage be applied between the two input terminals to balance the amplifier output. In this section we are concerned with the de error voltages and currents that ean be measured at the input and output terminals, Input Bias Current The input bias current is one-half the sum of the separate eurrents entering the two input terminals of « balanced amplifier, at shown in Fig. 15-13a. Since the input stage is that shown in Fig. 15-8, the input bias current is Ta = (Tax + Ins)/2 when Ve = 0.518 / INTEGRATED ELECTRONICS See. 156 Fig. 15-13 (a) Input offset voltage. (b) Output offset voltage. Input Offset Current The input offset current Jy is the difference between the separate currents entoring the input terminals of a balanced amplifier. As shown in Fig, 15-13a, we have Iw = Inj ~ Ins when V. = 0. Input Offset Current Drift The input offset current drift Als,/AT is the ratio of the change of input offset current to the change of temperature. Input Offset Voltage ‘The input offset voltage Vs is that voltage which ‘must be applied between the input terminals to balance the amplifier, as shown in Fig, 15-130 Input Offset Voltage Drift The input offset voltage drift AVu/AT is the ratio of the change of input offset voltage to the change in temperature. Output Offset Voltage ‘The output offset voltage is the difference between the de voltages present at the two output terminals (or at the output terminal and ground for an smplifier with one output) when the two input terminals are grounded (Fig, 15-198). Power Supply Rejection Ratio The power supply rejection ratio (SRR) is the ratio of the change in input offset voltage to the corresponding change in one power supply voltage, with all remaining power supply voltages held constant, Slew Rate The slew rate is the time rate of change of the closed-loop amplifier output voltage under largo-signsl conditions, ‘The various parameters of a typical monolithic operational amplifier are given in Table 15-1,See. 156 OPERATIONAL AMPUFIERS / $19 TABLE 15-1 Typicol parameters of monolithic ‘operational amplifier Openctoop gain Aa.siossee+s-+ + 80,000 Input oftes voltage Vie. 1m Input offeet ourrent Io : 100A put bias current J» 100 na Common-mode rejection ratio». 100 aB PORK. 7 20. a er s ornare Veo ait A 10 ,V/°C Slew rate, a 1Vie Universal Balancing Techniques When we use an operational amplifier, is often necessary to balance the offset voltage. ‘This means that we must apply a small de voltage in the input so as to cause the de output voltage to become zero. ‘The techniques shown hare allow offset-voltage balancing with- out regard to the internal circuitry of the amplifier. ‘The eireuit shown in Fig. 15-14a supplies a small voltage effectively in series with the noninverting my Fig. 15-14 Universal offset-voltage balancing circuits for (o) inverting and (b) noninverting operational ‘amplifiers.‘520 ,' INTEGRATED ELECTRONICS See. 157 input terminal in the range + VUts/(R: + Ra] 5 mV if +15-V supplies areused and R, = 200K, Rs = 1009. ‘Thus this circuit is useful for balancing inverting amplifiers even when the feedback clement Ry is a capacitor or a nonlinear element. If the operational amplifier is used as a noninverting ‘amplifier, the circuit of Fig, 15-148 is used for balancing the offset voltage. 15:7 TEMPERATURE DRIFT OF INPUT OFFSET VOLTAGE ‘AND CURRENT ‘The most critical influence on the operation ‘of the operational amplifier is exercised by the input differential stage because the equivalent error effects of the subsequent stages are reduced by the gain provided by the first stage. In this seetion we examine the input error signals and thermal drifts of the input differential stage, shown in Fig. 15-8, Trom Fig. 15-8 we see that the input offset voltage is Var = Vins — Vors (15-28) where Vee: and Ves correspond to Tei = Tex. It is possible to fabricate matched integrated transistor pairs, where the baso-to-emitter voltage differ- ence is approximately one millivolt. ‘The input offset voltage drift ean be found using Eqs. (15-26) and (19-02): GV _ Vans _ dVans _ Voi ~ Vans ar i or BV _ Ve ed a527) From the differential equation (15-27) we find Vo = CT (15-28) where C is a constant, ‘Thus we see that the input offset voltage drift is independent of temperature, If we assume that Vs. = I mV at room tempern- ture, then d¥a,d7 = 101/300 = 3.3 zV,°C, as compared with aVye/AT = —2.5 mV/°C for a single common-emitter transistor. ‘The input offset bias eurrent has been defined as Ty = In — Tos, and if In. # Tas, even with equal source resistances a differential input error voltage will be produced at the input of the first stage. Ideally, we would like to have In, = Ias = 0, and it is for this reason primarily that very high input-resis- tance differential stages are used (See. 15-5). Sinee Jey _ Ios lenSee. 15-8 ‘OPERATIONAL AMPLIFIERS 521 Ter = Ics, is given by de 1 4p; 1 da: Ae = (28) (Br san Las _ [00080 > 25°C gan (Moose 7 c250 ‘The dst exprmion now besomes de (La on ~ - Gar) 45-30) It is possible to reduce the input bias cmmrent and the corresponding eurrent drift by using Darlington pairs instead of Q1 and Q2 in Fig. 15-8. However, because of the added pair of emitter junetion voltages, there is en inerease in the input offset voltage and voltage ditt. 15-8 MEASUREMENT OF OPERATIONAL AMPLIFIER PARAMETERS. In this section we describe practical methods of measuring some of the impor tant parameters of operational amplifiers. Specifically, we examine (1) open- Toop voltage gain Ay, (2) output resistance Re without feedback, (3) differenti Input resistance Ry, (4) input offset voltage V«, (5) input bias current x and input offset current Zu, (6) common-mode rejection ratio, and (7) slewing rate. Opei-loop Differential Voltage Gain Ay = Ay The open-loop voltage gain is defined as the ratio of the output signal voltage to the input differential signal voltage V.. Figure 15-15 shows a technique of measuring this param- ter. It is essential that the effect of the input offset voltage be canceled as shown in the figure, since otherwise the high amplification of this voltage will rosult in output saturation. ‘The input excitation V, is an ae signal; by varying its frequency we ean obtain the frequency response Ay. The input attenuator is essential so that V; can be at a sufficiently low level for output swings no sgroater than about 30 percent of the output voltage rating (to ensure linear operation). Output Resistance R, ‘The output resistance R, of the operational ampli- fier can be obtained using the circuit of Ig. 15-15 and measuring the decrease in the low-frequency gain Ay eaused by a lond resistance Rz. ‘Then, from Fig 5b522 / INTEGRATED ELECTRONICS See 15.8 Fig. 15:15 Circuit for measuring Ay, Ry, ond Ric and (é:-1)r assy where A, and Ay are the openoop gains with R,= © and Ry # =, respectively. Differential Input Resistance R; ‘The differential input resistance R, ean be measured by forming a voltage divider st the input of the amplifier in Fig, 15-15. This is done by inserting two equal resistors R at points A and B in series with the inverting and noninverting terminals. ‘The new output is “impr oRY where V, is the value measured with R = 0, ‘Two resistors instead of one are used s0 that any stray coupling from the output will generate equal signals at the inverting and noninverting terminals, These equal stray input signals ‘will be prevented from reaching the output by the common-mode rejection, Often a eapacitor C is placed across each of the resistors R to reduce high- frequeney noise From the above equation we solve for Rs. If the capacitors C are employed, the input signal frequeney must be much Tess than 1/(@eRC). If Reis very high, as with FET input differential stages, then V, = V;, and the measurement is not practicalSoe. 15:8 (OPERATIONAL AMPLIFIERS / 523 Fig. 15-16 Mecsurement of input offset voltage Vee Input Offset Voltage Vu ‘The simple closed-loop cireuit of Fig. 15-16 ‘can.be used for this measurement. We have from Eq. (15-4) R+R R vi Y= (15-83) If R = 100 @ and R’ = 100 K, the small input offset voltage is multiplied at ‘the output by a factor of 1,001, and thus it is eusily measured. Input Bios Current In Fig. 15-17 we allow the input bias currents Tn: and Zy3 to flow through the two large resistors Rs > 10 M, while the amplifier is connected as a unity-gain noninverting amplifier. If resistors Ry are selected so that IpRe > Viq then the voltages ereated by the bias eurrents fare much larger than Vi. Hf we connect terminals A and B, the measured output will be Ve = Inia; similarly, the measured output will be V, = —Ig2Rn if we connect terminals Cand D. The large resistors Ry are bypassed with 0.01-uI expacitors to reduce high-frequency noise. The bias current Zp is defined in Sec. 15-6 as the average of In: and Is, while the input offset current Z, is the difference In — Ins of the individual base eurrents. ‘Common-mode Rejection Ratio ‘The common-mode rejection ratio p is defined in Eq, (15-11) by Fig. 15-17 Measurement of bias currents.524 ,' INTEGRATED ELECTRONICS See. 15.9 % Fig. 15.18 Meosurement of common- mode rejection ratio, where de voltage guin, and 4, isthe common-mode voltage ain. Por the cirouit of Fig. 15-18, the signal at point A or B is essentially the common-mode signal Y., where Ry Roy. Yeone hE Yn assuming that Ry > Ry and R’ > R. If the resistors are matched (R = Ry and R’ = Ri), then V; = V, = 0, provided that 4, = 0. Since A, # 0, there isan output orror voltage Vand thus n differential input voltage V, = Vo/ dy ‘Thus Ag Val ¥i Ve A.” VV." Vi Since V, = Vs. then Vis effectively eros: R and ', = [(R + R)/RIVe R+RY, eae (a5-34) It is found that A. = V./V, is a nonlinear function of the magnitude of V. For this reason it is important to make the above measurement at the rated common-mode voltage swing, Sewing Rate? ‘The maximum rate of change of the output voltage when supplying the rated output is defined in Sec, 15-6 us the slewing rate, This rate dV',/dt can be measured using the noninverting circuit of Vig, 15-4, with R= « and R’ =, since this usually represents the worst ase. If the amplifier has a single-ended input, then the cireuit of Pig. 15-2a is used, with Z= R= 1KandZ! = R= 10K. The input Vina high-frequency square wave, and the slopes with respect to time of the leuding and trailing edges of the output signal are measured. It is common to specify the slower of the two rates as the slewing rate of the device. 15:9 FREQUENCY RESPONSE OF OPERATIONAL AMPLIFIERS ‘The typical operational amplifier diseussed in See. 15-5 consists of four stages, asshown in Fig. 15-11, If we assume that the anvplifier is driven by two signalSee. 15.9 (OPERATIONAL AMPLIFIERS. / 525 soareos which are equal and opposite in phase, there are only true difference signals present. ‘Thus we need consider only half of each differential pair for fan analysis of the frequency response. This response ean be obtained by considering a eascade of two common-emitter stages, an emitter follower and the output stage. ‘The general method of obtaining the high-frequency response of such a chain of interesting stages was presented in Secs. 12-10 and 12-11. The computational complexity is so great that computer-aided analysis i required. ‘The response may also be obtained by laboratory measurements. ‘The open-loop gain of the or aMP has a transfer function with several poles and with eros at much higher frequencies than the poles. Experi- mentally, the poles can be found from the amplitude response eurve (the plot of the magnitude of gain in decibels versus log f). Tangent to this curve are dravn straight lines whose slopes are 0, —20 dB per decade, —40 dB per decade, . . . , as indicated in Figs. 12-4 and 12-6, ‘The pole frequencies f, 2, «are then obtained from the corer frequencies, the values of f at ‘hich adjacent lines intersect. ‘The poles and seros of A(jf) are normally specified by the manufacturer in data sheets provided with commereial operational amplifiers. In Fig. 15-19 ve show the open-loop gain and phase response of a typical oP aatr (A702), using the straight-line Bode approximation. We see that the transfer fanetion has three poles, one at 1 MHz, asecond at 4 MHz, and a third at 40 MHz, For the MC1530 the manufacturer gives the first three poles at J, 6, and 22 MHz. Stobility of an or amp For the inverting or amp of Fig. 16-24, with Z = R,Z' = R,and Ri = ©, we obtain from Bq, (15-2)526 / INTEGRATED ECTRONICS . Sec 15.9 Yo Ay V.~ R+R T= RAv/RF BY ‘This equation may also be obtained by using the feedback concepts of Chap. 13, tas we now demonstrate, ‘The topology corresponds to voltage-shunt feedback, and it is found (Prob. 15-24) that. Ay 1 ARR Ruy Ben Run Any = Bae (15-36) Using the feedback formula (Bq. (13-4)] Ruy = 2M MO TF BR and Eqs. (15-86), the expression for Ay, in Bq. (15-88) is obtained, ‘The condition for oscillation is Ry = = 1/180° (57) Similarly, for the noninverting amplifier of Fig. 15-4, we find v, — Ay Ano VT TR + RIAe es) Wo so from Eq, (15-98) that Ba, (16-87) represents the slabilty eieron for both the inverting and noninverting operational amplifrs, Te is important to point out that for negative feedback the guin Ay ropraonte a negative real number a low Srequensas, Hence xe observe that if the product [R/(R + R']|Av| becomes unity when the phase shift of —Ay reaches 180°, the amplifier will oscillate. From the open-loop gain and phase Shift of the .A7024' shown in Fig. 1519, we find that at the frequency of J'~ 125 Mula, where the phase shift of ~ Ay equale 180" the magnitude of 4y is 36 dB. Thus, from Hq. (15-37) we have 20 log fp + 20 log [Av| = 20 log 1 = 0 (15-38) R logge = ~% Rk 1 RFR md For 45° phase margin we find, from Pig. 15-19, 20 log |v] = 60 4B, and from Bag. (15-89) we obtain 20 log [R/(R +R?) = ~50 dB, or R/R’ ~ shy Since the closed-loop voltage gain is approximately Ayy = —R'/R, we se that the low-frequency gain of the inverting feedback amplifier cannot be less than 316 in magnitude for a phase margin of atleast 45°.Sec. 18:10 ‘OPERATIONAL AMPLIFIERS / $27 15-10 DOMINANT-POLE COMPENSATION. In the preceding section we observed that the zAT02A oF amp will be unstable if sufficient feedbuek: is used to obtain a low-frequency gain with feedback less than 62. By adding poles and zeros to the frequeney response of the loop gain, ‘we can compensate the phuse shift introduced by 8 and/or Ay to ensure stabil~ ity, limit any peaking in the closed-loop frequency response, and even reduce overshoot and ringing if a square wave is applied to the closed-loop operational amplifier. Our disoussion in Sec. 14-11 on compensation of a feedback ampli- fier is equally applicable to an oP aur, ‘Thus we ean cause the gain Ay to decrease as a function of frequency by inserting a single capacitor to shunt the signal path to ground. The capacitance is chosen such that it creates a dominant pole in Ay low enough in frequeney so that the magnitude of the Joop gain beeomes less than unity at a frequeney where the amplifier introduces negligible phase shift. Since the eapacitor adds a phase shift smaller than 90° the circuit will be stable, A possible point to which to connect such a com- pensating capacitor in Fig, 16-11 is from pin 5, the output point, to ground. ‘This is done primarily to suppress internally generated broadband noise volt ages. ‘The more desirable location® for the compensation capacitor is between ins 9 and 10, since the slew rate decreases with inereasing capacitance. A. larger eapacitance (For the same roll-off pole) is required at the output pin 5, due to the lower resistanee seen by the capacitor at this node than between pins 9 and 10. Figure 15-202 shows the open-loop voltage gain Ay versus frequency for three different values of roll-off capacitance between pins 9 and 10 for the 3MIC1590 or aur, Figure 15-20b shows the decreasing slew rate with increasing ‘compensating capacitance for the same amplifier. Figure 15-2la shows the closed-loop voltage gain with frequency for Ay, = 100, 10, and 1 for the “Tea ” : a ae = 0) i : 2 ie cy | ® oo 10 10K 10K 1K WM 10M “oo oor on 10, fe cua? @ ® Fig. 15:20 (0) The MC1520 open-loop voltage gain Ay versus f for three C+ Cy. From Fig. 12-22, with Cw # 0, we obtain the voltage gain 4’, of the first, stage after the compensating capacitor C, has been added. Ln naRs Avs = Ty jaghCs FC car From Eqs, (16-85) and (15-46) is obtained goal + S/S, gual + 5/1) T+IU/R) + IU/ha) 1+ 50h) oe where the compensated pole of the first stage fue is given by Ain and Cy is chosen s0 that fic fe. Note that the effect of the compensating capacitor Cy is to change the pole of the first stage from f. to a much smaller value fic ande-to add to the gain function of the first stage a zero which exactly equals the pole of the second stage. Hence there is a pole-zero cancellation, and the overall gain Ay of the twvo stages is ndR Aver T+50Mfie) ‘The relative positions offic fy and fe are indicated in Fig. 15-286, where the Bode plots ofboth stages Av are shown, uncompensuted and compensated Since the compensated response has a slope of —20 dB per deeade when it crosses the O-dB line, the amplifier is unconditionally stable. Ay = Abdys = (15-48) 15:12 LEAD COMPENSATION Lead compensation is generally provided by modifying the 8 network, spe- cifically, by shunting resistor R’ with a capacitance C’, as shown in Fig, 15-24, so that the new loop gain will have an added positive phase shift in the fre- queney range near the unity-loop-gain crossover point, Equation (15-37)592 INTEGRATED ELECTRONICS Sec. 15:12 Fig. 15-24 Lead-compensoted opera: gives the loop gain for the uncompensated amplifier, If we substitute for R’ ‘an impedance 2’, which is the parallel combination of R’ and C", Eq. (15-37) becomes, 1s? = = 52 (15-49) where we find that is given by alti’ i 4= gn (15-50) and jf, = 2th (5-51) E always higher than the frequeney of the zero. Note tliat the pole frequeney EXAMPLE Design the amplifier of Fig. 15:24 with the A702A, u feedback at low frequencies. Find C* for a phase margin of 45°. 1g 82 dB of, Solution Figure 15-19 shows the open-loop gain Ay of the 4A702A, from which ‘we sae that with 32 dB of feedback, the phase margin is zero and the cireuit will oscillate. By ndding C’, we introduce a phase lead due to the eompensating eer, fn thus we may shape the phase-shift curve so as to obtain the 45° phase margin desired. Optimum valuos for J, and J, must be found graphically from the Bode plot. OF course, fg eannot be placed independently off, sinee they are related by Bq. (15:51) ‘To find the ratio fy we must calculate (R + R),R. Since a desensitivity D of 82 dB at low frequencies is desired, then 20 10g, D = 20 log, | + Bitar] = 20 lox |B, 15.82) or using the values of 6 and Ruy from Eg. (15-38) and nating that 20 log [A 68 iB, from Fig. 16-19, we have 20 og =, + 20 log [A & TR 20 og gE + 08 = 92 15-59) from which wo find & if 83 and f= 63, (15-64) [Note that the pole is located at a very much higher frequeney than the zero.See 15:12 ‘OPERATIONAL AMPLIERS / 533, he fh by Traict A 2 “ e {ay| ory ® ¥ } ase of “A g 9 2258) Phase ot iy g 2p eapernty i » Psat =a * » “+0 Bvt Ss SPhase of — Ay ° lal T . atseite oem MGM Tom ime Fig. 15-25 Magnitude and phase response of leed-compensated operational complifier (4%, = AAs). In Fig. 15-25 in indicated the idealized Bode plot for the open-loop gain Ay of the wA7O2A o” anee, the transfer funetion A of the compensating network, fan the product of these two, namaly, Ay = Ady. The magnitude of Ay ie indicated by solid heavy lines, of A by solid Hightweight lines, and of af by solid dashed Iiues. The phase lines are drawn in a corresponding manner, except that they are shaded. The magnitude and phase of Ay are identical with the corre- sponding Bode plots in Fig. 15-19. Since J,>>, then the pole has practically no influence on the resultant sain Al, in the neighborhood of the phase of — 180°. Hence we must locate f bby trial and error a that the overall raponse AY satisfies the design requirement of 45° phase margin at 82 dB of low-frequency feodback. It takes only a few trials to settle upon f, = 100 Mts. ‘The plots in Fig. 15-25 correspond to this value of the zero (and to J, = 68f, = 63 MFiz), and we see that the desived specifi- ‘ation is satisfied. ‘To determine the value of ( we may arbitrarily choose R, and from Eq. (15-54) R’ = 628, and then C’ is given by Eq. (1S61). For example, for R= 1K, then R= 62 K, and we find o = 025 pF 1 -,-__1___s Defak! ~ TRB 10" x BD x 108 Since this value of C’ is impractically small, we choose R = 100 9, R’ = 6.2K, and then C? = 2.5 pP. [Note thot since the input to the oF aap terminals is a virtual ground, the impedance seeu by the signal source Vin Fig. 15-24 is only 100 2.584 / INTEGRATED ELECTRONICS See. 15.13 Lead compensation can also be provided by modifying the open-loop voltage gain of the basic amplifier, provided that appropriate leads are avail- able from the IC chip. For example, a eapacitar C’ ean be connected between terminals 7 and 8 of the IC op amp shown in Fig. 15-11. If resistor Ry is paralleled by a capacitor O' then the RsC" parallel combination has an imped ance Zs = Ry/(1 + sC"R,). ‘The voltage gain of the output driver becomes V/V = ~Rry/Zs = —Ry(l + sC'Rs)/Ry and, thus, a zero i introduced in the open-loop voltage gain transfer funetion of the basic amplifier. 1513 STEP RESPONSE OF OPERATIONAL AMPLIFIERS. In Chap. 14 it is demonstrated that many feedback amplifiers have a single dominant pole or two dominant poles, with all other poles at least two octaves away. If an oP AuP is represented by a two-pole transfer funetion, the small- signal response is that discussed in Sec. 14-2 and plotted in Fig. 147. Large-signal Step Response If the output voltage exceeds 1 V, the transient response is altered by nonlinear operation such as bias disturbances and the slewing-rate® limit determined by the circuit capacitances. If we conneet, for example, a compensation capacitor Cy from eolleetor to collector of the first differential stage, this capacitor must charge during the large-signal transient response, and the maximum available current is 2c, where Io is the de current of either transistor. ‘Thus aVe _ We Fe -% (15-55) and this limit distorts the large output signal. In general, the nonlinear oper- ation and slewing-rate limit incroaso the settling time (Fig. 14-6). In practice, the selection of the compensation capacitor is greatly aided by observing the amplifier step response with a square-wave input and varying the compensating capacitance at various signal levels to obtain satisfactory ‘compensation. REFERENCES 1. Widlar, R, J.: Design Techniques for Monolithic Operational Ampligers, [EEK J. Solid-sale Cireits, vol. SC-4, pp. 184-191, August, 1969, 2, Rimbinder, J.: ‘Designing with Linear Integrated Circuits,” pp. 19-31, John Wiley ‘& Sons, Ine,, New York, 1969. 3. Tobey, M., et al. (eds), Burr-Brown Research Corp.: “Operational Amplifiers Design and Applications,” McGraw-Hill Book Company, New York, 1971See 15.13 OPERATIONAL AMPLIFIERS / 335, 4, Giacoletto, L. J.: "Differential Amplifiers,” Wiley-Interseienee, « Division of John Wiley & Sons, Ine., New York, 1970. 5, “RCA Linear Integrated Cireuits,” pp. 28-43, Radio Corporation of America, Harrison, NJ. 1967. 6 Wissernan, I., and J. J. Robertson: High Performance Integrated Operational Amplifiers, Motorola Semioondustor Products, Ine,, Application Nowe AN-208 7 Wilson, G. Re: A Monolithic Junction FET—n-p-n Operational Amplifier, [RBE J. vol. SC-8, pp. 841-348, December, 1968 8, Searle, C. L, A. R. Bootheoyd, H. J, Angelo, Jr, PB. Gray, and D. 0. Pederson: “Plementary Cireuit Properties of Traxsistors," pp- 142-143, John Wiley & Sons, Ine., New York, 1964 9. Hearn, W. Bu; Fast Slewing Movolithie Operational Amplif Circuits, vol. SC-4, pp. 20-24, February, 1971 TE J. Solid-state REVIEW QUESTIONS 15-1 (a) Draw the schematic block diagram of the basie oP aate with inverting and aoniaverting inputs, (2) Indicate its equivalent eireut 15.2 List six charaoterstes of the ideal ov ame. 15-3. (a) Draw the schematic diagram of an ideal inverting oP au with voltages shunt feedback impedances Z and Z'. (9) Tndicate the virtual-grownd model for eal evlating the gain, 15-4 For the op aMP of Rev. 15-8, assume finite A, and Ry and nonsero R, Draw the equivalent cireuit using Milles theorem. 15.5 (a) Draw the schematic diagram of an ideal noninverting oF aM with voltage-shunt feedback. (8) Derive the expression for the voltage gai 15-6 (a) Define an ideal orrr ase. (@) Define difference signal ez and con mode signal t 157 (a), Draw the circuit af an emitter-coupled pir ane. @) Explain why the CMRR— © for a symmetrical eiouit with Re ©: 15.8 (a) Draw the equivalent cireuit from which to caleuate A, for the emitter- coupled pier ance. (8) Repeat for A. 159 (a) Why is R, in an emitter-coupled irr aur replaced by a constant current souree? @) Draw such a cirouit, (€) Explain why the network replacing Re fcts as an approximately constant current Zo. (2 Bxplain how Jo is made to be independent of temperature. 15-10 Explain why the CMRR is infinite if a true constant-ourrent souree is ‘used in a symmetrical emister-coupled over an. 15.11 (a) Sketch the transfer charucteristis of « perr any, (6) Over what dit ferential voltage isthe pir¥ ance a good limiter? (2) Over what differential voltage is the transfer characteristic quite linear? {d) How docs the transeonductanee vary (qualitatively) with differential voltage? (2) Explain why AGC is possible with the 15412 (@) Draw an IC oF aur in block-diagram form, (@) Tdentity each stage by function.536 / INTEGRATED ELECTRONICS See. 15.13 15-19 Define (a) inpuc bias curent, (6) émputofet curren, (0) input offset solage, (4) output aftet voltage, (@) power supply rejection ratio, and (f) slew ate tor an o” ant, 15-14 Show the balancing arrangement for (a) an inverting nnd (6) a noninvert. ing o7 ance. 15-15. Show the cireuit and explain how to measure (a) Av, (®) Ry, and (¢) Ry of an oP ast, 1516 Repeat Rev. 1518 for Vs, 15.17 Repeat Rev. 15-15 for lu 1518 Repeat Rev. 15-15 for CMRR ~ p, 1519 Repeat Rev. 15-15 for the slewing rate, 15-20 Explain how the poles of an or axe may be determined experimentally. 1521 Discus dominant-pole compensstion of an o” ax. 15-22 Indicate three methods of implementing pole-zero compensation of an 15-23 (a) Draw the circuit whieh applies lead compensation to an inverting oF ance, @) Verity that a phase lead is introduced by the cireuit element adde