Non-Volatile Memory:
A review of past and present concepts and applications
Hokchhay Tann
ABSTRACT
The evolution of non-volatile memory (NVM) has
been at a very fast pace in the past five decades.
Many new concepts have been introduced, yet
only some of them reached the market. Ongoing
studies focus on the search for cheaper and faster
memory. In this paper, the basic physical and
operating principles, and challenges and oppor-
tunities of three NVM technologies (EPROM,
Flash, and Memristor) will be introduced.
Keywords
Non-volatile memory, EPROM, Flash, Memristor
I. INTRODUCTION
NVM is a form of storage device which re-
tains data written to it even when the power supplied
is off. This type of memory, commonly known as
read-only memory (ROM) is often used as second-
ary storage device due to its slow read/write speed
compared to that of a volatile memory, which is usu-
ally termed as Random Access Memory (RAM).
Over the past three decades, the share for NVM has
been growing significantly, and many studies are
continuing to improve the read/write speed while
increasing the density of cells per chip.
Various types of non-volatile memories
have been developed over the past years. However,
in this review paper, we will only focus on three
types of NVM, which reflect the evolution that spans
over four decades. Our choices include the erasable
and programmable read-only memory (EPROM),
flash memory, and the recently developed resistive-
switching memory known as RRAM/Memristor.
EPROM was first developed in the 1970s by
Intel® [1] by arranging arrays of floating gate tran-
sistors on a silicon wafer. Although it is electrically
programmable via channel hot electron (CHE) injec-
1
tion, the memory is erased by exposure to strong UV
light source [2]. EPROM, therefore, cannot be
erased in single bit manner but as a whole array.
Figure 1 shows an EPROM memory cell, which is
basically a floating gate transistor. The inconven-
ience of bulk erasing and high cost of production of
EPROMs led to investigations into new types of
memory which would be more flexible and cheaper.
Flash memory was supposed to replaced
EPROM at the end of the 1980s [2]. Figure (2)
shows a flash memory cell. Although figures (1) and
(2) look similar, some technological and geometrical
differences exist between the two cells. For instance,
the gate oxide between the silicon and the floating
gate is thinner for the flash memory. The source and
drain diffusions are also different between the two.
These differences allow flash memory to be pro-
grammed and erased electrically [3]. Furthermore,
flash memory can be erased in blocks of different
sizes with single power supply [2]. These huge ad-
vantages encouraged new applications of flash
memory technology and widened the markets of this
new NVM. According to Paulo Pavan et al. [2], ‘in
1996, it was forecasted that the memory market is
going to be about half of the total integrated circuit
market by the year 2000.’ In the late 1990s, some
important applications of flash memory were fore-
casted to be in the logic system (microprocessor) and
the solid state hard drive through large scale integra-
tions of flash memory cell arrays. These ideas can be
seen in todays’ USB flash drives and many other
electronic devices. However, flash technology is
being replaced with the new resistance switching
memory technology due to its relatively slow
read/write speed, short data retention time (~10
years), low-density, and some reliability issues. For
instance, the theoretical minimum oxide thickness to
guarantee a reasonable retention of the stored infor-
 show the evolution of storage devices over the past
five decades. First, an overview and the underlying
principle of operations of EPROM will be discussed.
This discussion is followed by the discussion on
similar topics with Flash memory. And last, Memris-
tor concepts and challenges will be discussed.

II. EPROM TECHNOLOGY

Non-volatile and reprogrammable memory
known as EPROM was developed to allow users to
write and update new storage information. By 1991,
the density of the mass produced dielectric Si MOS
EPROMs, discussed in this section, reached 4Mbit
per chip [6].

1. How the device works

In an EPROM cell (figure 1), information is
stored as electrons on the p-doped poly Si floating
gate (FG). In reading mode, a voltage is placed on
the control gate (CG) of the cell, and the sense am-
plifier current detector will decide whether the cell is
in ON (1) state or OFF (0) state depending on the
current or the lack of current. When there are excess
electrons on the p-doped floating gate, the gate acts
as an insulator, so no current flow through, and
mation is about 5 nm, however, intrinsic defects in
the gate oxide and the oxide degradation due to the hence the cell is in a ‘0’ state. Otherwise if there is
programming and erasing operations could result in
single bit failure with an erratic occurrence [4].
Known as one of the best technology break-
throughs of 2008 by Wired.com, memristor is ex-
pected to be the next generation non-volatile
memory. This new technology has garnered much
interest due to its numerous advantages such as the
simple cell structure, low operational voltage, fast
switching speed, and high integration density [5]. At
the time of writing, there are still difficulties that
keep memristor only practical at the laboratory level.
However, this technology is expected to be marketed
in the next few years replacing the traditional flash
memory chips. The success of memristor will revo-
lutionize the way computers work such as instant
startup and human-like memorization.
This paper is focused on the three memory
technologies (EPROM, Flash, and Memristor) which

2
no excess electron, the gate is conductive, and hence
it is in a ‘1’ state [3]. The charge/state of FG is re-
tained by the surrounding SiO2 insulator for more
than 10 years [6].
To program the device, four electrons injec-
tion-extractions methods via three transport mecha-
nisms (photoemission, tunneling, and injection over
the insulating layer between FG and CG or between
FG and Si substrate) have been used to positively or
negatively charge or to discharge the FG [6]. The
four injection-extraction methods are labeled in fig-
ure 4(a) and (b) along with their appropriate biases.
In figure 4(a), three injections methods are (i) chan-
nel hot electron injection (CHEI) over Si/SiO2 barri-
er, a medium speed process (~10µs), (ii) avalanche
electron injection (AEI), a medium speed process
(~10µs), and (iii) Fowler-Noidheim tunneling elec-
tron injection (FN-TEI), a slow to medium speed
process. In figure 4(b), the two extraction methods
are (i) FN- tunneling electron extraction, similar
speed to FN-TEI, and (ii) UV-light photoemission
electron extraction (UV-PEE), a slow process (~5
minutes). The preferred methods in manufacturing
are the AEI and UV-PEE [6], which will be dis-
cussed in this section.
3
2. Programming a UV-EPROM cell
The first UV-EPROM was invented by
Frohman-Bentchkowski at Intel in 1971 (see figure
5). This model is a p-MOS transistor cell with a
poly-Si floating gate. The floating gate is surrounded
by unshielded SiO2 insulator to allow UV-light erase,
so there are only three terminals (source, drain, and
the n-Si substrate). During programming, electrons
are injected into the floating gate via avalanche elec-
tron injection (AEI) with the path shown on figure 5.
In this process, an internal field is produced between
the more positive floating gate and the drain junction
space-charge region, VFG ~  | VD / 2 | 14V ;
 | VD | 28V [6]. The carriers (electrons), which
are traversing along the source-drain path, experi-
ence high electrical field at the pinch off region near
the drain. These carriers reach the energy states
which are considerably higher than the equilibrium
thermal energy in the semiconductor lattices and are
called hot-carriers. For those carriers with energies
above the impact-ionization threshold (~1.6eV) can
generate electron-hole pairs through pact-ionization
[7]. Some of the carriers with large enough energies
enter the oxide region along the AEI trajectory. The

energy barrier is ~3.2eV for electron injections, and
~4.8ev for holes [7]. The exact barrier at any given
point along the path is determined by the field
strength at that location due to Schottsky effect.
Some of the carriers get injected into the SiO2 layer
and contribute to the gate current, however, a portion
of them get trapped in the oxide interface due to par-
ticular defects presence. The trapped charges shorten
the lifetime of the device by modulating the surface
potential and carrier mobility at the Si/SiO2 interface
[8]. This caused a serious concern over the life-time
of the CMOS circuits.
3. Erasing a UV-EPROM cell
Deletion in UV-EPROM happens under the
cell exposure to UV-light. Here, similar mechanism
as programming but without application of electrical
field is applied. Under exposure to UV-light, the
electrons stored in the floating gate are excited to
higher energy levels (~>4.5eV) which are higher
than the energy of the Si/SiO2 barrier
[  (Si)   (SiO2 )  4.02  0.9  3.12eV ] [6].
This energy difference allows electrons to be re-
leased into the n-Si substrate. This process usually
takes about 5 minutes [6].
This erasing process can be tedious when
only part of the stored information needs to be modi-
fied. This process is also done manually, which is
not suitable for mass storage when many chips are
combined. The search for a more convenient storage,
therefore, goes to automatic and block-by-block
4
erasing EPROM, which is presented in the next sec-
tion.
III. FLASH MEMORY TECHNOLOGY
By 1991, Gordon Moore, former chairman
of Intel, publicized the cease in the production of
EPROMs due to its inconvenience in erase [6]. By
this time, a novel technology, the electrically erasa-
ble and programmable ROM (EEPROM/Flash) was
introduced. As shown in figure 2, the structure of a
flash memory cell is very similar to that of an
EPROM. The differences are (1) flash cell has a
thinner oxide layer between FG and Si substrate
100Å instead of 200Å), (2) the FG is no longer ex-
posed but covered by an additional thin layer of SiO2
and a control gate (CG) on top, and (3) the n+ source
junction is diffused deeper than that of the drain
junction [6]. Since Fowler-Nordheim (FN) tunneling
happens between control gate (CG) and floating gate
(FG), the insulating layer between them is not just
SiO2, but a triple layer of oxide-nitride-oxide (ONO)
[9].
One downside of flash memory cells is that
they cannot be as densely packed as those in
EPROM. Some cells are made with two transistors
[3]. For this reason, various architectures such as
NAND, NOR, AND, and DINOR were designed for
different purposes to yield the trade-off between
speed and cell density. However, due to today’s in-
dustry standard chip structures, only NAND and
NOR flash memories will be discussed.
The electrical programming operation of
flash cell is similar to that of EPROM. Electrons are
injected on to the FG via hot electron injection or the
Fowler-Nordheim tunneling with VG=VPP=+12V,
VD=+9V, and VS=VX=0V (figure 4(a)). However, to
erase a flash cell, electrons are removed from the FG
to the source junction via Fowler-Nordheim tunnel-
ing [3], which does not need any to UV-light. Eras-
ing is setting the cells to logic 1 and can only be
done by blocks, which could vary in sizes on a sin-
gle chip [9]. In both programming and erasing pro-
cesses, electrons are preferred to holes as the charge
carriers to be injected or removed due to electrons’
lower energy barrier (~1.4eV for Si/SiO2 with 9-nm
thick oxide layer). Previous study [9] shows that at
10.5MV/cm of oxide field, electrons injections are
about 100 times less effective as holes in causing
oxide breakdown.
To read a flash memory cell, a threshold
voltage (VT) is determined on the FG. This is done
fastest by reading the current driven by the cell at a
fixed bias applied on the CG [10]. Once a certain
amount of charge and the corresponding ΔVT are
determined for FG as shown in figure 6, it is possi-
ble to apply fix reading bias on the CG in a way that
there is high current (tens of mA) for logic ‘1’ and
no current for logic ‘0’ [10]. So a logic ‘1’ can be
thought of as no charge on the FG while logic ‘0’
means there is charge stored on the FG. For multi-
level storage, instead of just depending on the pres-
ence or non-presence of current, current strength is
sensed. Therefore, the ability to precisely control the
amount of charge injected to or removed from the
5
FG is needed in order to set the VT for different bits
combinations on a single cell. A cell with 2n VT dis-
tributions is capable of storing n bits [10]. An exam-
ple of a 2-bit per cell VT division can be seen in fig-
ure 7. Notice, 2 bits translates into 22 = 4 VT divi-
sions.
1. The NOR Architecture of Flash Memory
Developed in mid 1980s, NOR Flash was
the leading NVM technology in various applications
throughout the 1990s [4]. This success came from its
incredible improvements comparing to EPROM
technology. NOR Flash has the ability to store data
at multilevel, which means more than one bit per cell
allowing larger storage capability and lower cost. It
also has a very fast random access reading speed
suitable for in-place code-execution, so NOR Flash
was a suitable cost-competitive solution for both
data and code storage [4]. However, comparing to
volatile memories such as the SRAMs and DRAMs,
NOR Flash is still slow for code execution for in-
tense computations in computers, so NOR Flash is
only used as code-data package in small electronic
devices such as cell phones and music players.
Figure 8 shows the cell array of a block in a
NOR Flash memory. This architecture is named after
its NOR behavior; one side of the cell transistor is
connected directly to the ground, the other to a bit
line, and the control gate to the word line. When the
word line is pulled high (logic 1), the bit line is
pulled off (logic 0), and when the word line is logic
0, the bit line is logic 1.
A NOR flash is programmed by CHE injec-
tions onto the FG at the drain side and erased by FN
tunneling from the FG to the Si substrate [10].
2. The NAND Architecture of Flash Memory
NAND Architecture was also developed in
the mid-1980s, yet the technology matured slower
than the NOR Flash [4]. NAND technology was de-
veloped as an alternative high-density, smaller chip
size, and lower cost-per-bit memory. Although
NAND’s writing and erasing speed is very fast due
to programming by blocks, its dense structure loses
the capability of random-access which translates into
a slow reading speed, not suitable for in-place code
execution [11]. However, this high cell density per
chip makes NAND memory the cheapest solution in
today’s mass storage applications such as the USB
Drives.
As shown in figure 9, a block in NAND
Flash is formed by connecting 8 cell transistors in
series. This serial connection has a NAND logic be-
havior; if all word lines and select gates are on, the
output on the bit line is off, and if one word line or
select gate is off, the bit line is on. This cell ar-
rangement allows for the elimination of all the con-
tact between word lines and, hence, reduces the
block area by ~40% as shown in figure 10. A draw-
back with this configuration is the signal sensed by
6
the signal amplifier in reading mode is lower than
that in NOR Flash because several transistors are in
series [3].
Programming NAND Flash can be done in a
bit-by-bit manner or a whole page fashion which
helps speeds up the process. In programming mode,
18V bias is applied to the selected CG and 10V to
other gates [2]. When a ‘0’ is to be stored on a cell,
the bit line, source and drain are grounded, and a
strong electric field is formed between the CG of the
selected cell and the substrate [2]. This field allows
electron tunneling from the substrate to the FG in-
creasing the VT. When a ‘1’ is to be stored, the bit
line is biased to 10V; there is no tunneling and VT
stays negative [2]. On the other hand, erasing NAND
Flash is done by grounding the selected CG biasing
the p-substrate, source and drain to 20V [2]. The
voltage difference creates a field which releases the
electrons from the FG to the substrate through tun-
neling.
The reading processes of a NAND and NOR
Flash are somewhat different. NAND’s reading op-
eration is done by apply 5V bias to all the CGs ex-
cept the selected one, which is grounded. Now the
two select gates and other transistors in the array are
conductive and connect the bit line to ground. The
bit line is pre-charged, so if the bit stored is ‘1’ (neg-
ative VT) the selected cell is conductive and dis-
charge the bit line; if the bit stored is ‘0’, the cell in
non-conductive and the charge is retained on the bit
line [2].
The fast reading speed, low cost-per-bit, and
reliability of NAND Flash have significantly wid-
ened its market over the past two decade. In fact,
NAND Flash is the most widely used storage device
in today’s electronic. However, technology is not
slowing down; many new concepts have been im-
plemented over the past ten years, yet none of these
is ready for manufacturing yet as there are still many
reliability and material availability issues. In the next
section, a new concept, which is still at laboratory
level, is presented.
HfO2 sandwiched between two metal electrodes in a
metal-insulator-metal (MIM) configuration [5]. The
metal-oxide base switches are the most extensively
studied due to its compatibility with the fabrication
processes of the CMOS integrated circuits [13]. Un-
like resistor, memristor exhibits non-linear internal
resistance of the insulating layer, which depends on
the time integral of the external bias applied between
the two metal plates. Memristor remembers its last
resistance value when the applied voltage is turned
off until a new bias is applied [14].
A simple model of memristor made from p-
doped (see figure 11) semiconductor can be used
explain the behavior of the iv-characteristic, which is
a hysteretic Lissajous figure when the input signal is
sinusoidal [15]. As a potential difference is applied
between the two terminals, the dopants drift due to

IV. MEMRISTOR TECHNOLOGY

The concept of resistance switching device
was first introduced as the fourth basic circuit ele-
ment by Prof. Leon Chau in 1971 [12]. Chau based
his principle on the undefined relationship between

the charge ( q( )   id ) and the magnetic flux


(  ( )   vd ) which, he claimed, could not be real-


ized from the three existing basic elements (resistor,

capacitor and inductor). The proposed non-linear
relationship between magnetic flux and charge was
d  Mdq (see figure 3), where the constant M is
the memristance of the memristor. However, at the
time, no physical model was discovered yet. Until
now, this technology remains at laboratory level, yet
researchers at the HP labs hope to bring it to the
consumer market in the next few years.
The most popular structure of memristor
consists of metal oxide such as NiO, TiO2, CuO, and

7
an internal electrical field. For a basic Ohmic system thresholds can be determined to store n bits of data
with charge mobility V , we have [15]: on a single cell making memristor even cheaper.

 w(t )  w(t )  
v(t )   RON  ROFF 1    i (t ) Challenges
D  
(1)
 D  Despite the above mentioned properties and
dw(t ) RON capabilities, there are still many challenges to over-
 V i(t ) (2)
come before this technology can be commercialized,
dt D
R including switching endurance, device yield, operat-
 w(t )  V ON q(t ) (3) ing energy, electroforming, device nonlinearity and
D
some issues related to integration [13].
Replacing (1) into (3) for RON<<ROFF:
The switching endurance refers to the device
V (t )   R 
 M (q)   ROFF  1  V 2ON q(t )  life cycle, how many switching before the memory’s
i(t )  D  properties are deteriorated. Previous studies have
As we can see, the memristance has a non-linear shown that this degradation can happen anywhere

characteristic (1/D2) and is dependent on the previ-
ous switching value (D) while also changing with
the input q(t). This characteristic of the response is
dependent on the input signal frequency as shown in
figure 12. At low frequency, the hysteresis is fairly
obvious as the dopants get drifted for each period.
However, at high frequency, the hysteresis is sup-
pressed, hence, no change in memristance. Therefore,
an optimum frequency needs to be determined in
order to achieve a significant change in memristance.
With this property, a threshold value for the
memristance can be used to distinguish between a ‘0’
or ‘1’ bit stored. In a similar manner as figure 7, 2n
between ten to a million switching cycles [13],
which is not enough for computing and storage ap-
plication. However, Lee et al. recently found that,
using Ta2O5−x/TaO2−x as the switching material,
they can achieve up to 1012 switching cycles [17].
Different solutions have been proposed to
solve issues with memristor. However, each of the
proposed answer is still too specific for certain is-
sues [13]. In order to commercialize memristor tech-
nology, there needs to be a reliable, universal solu-
tion which will ensure its functional life-time. A bet-
ter understanding of the nano-scale level and operat-
ing mechanism of memristor should lead to the
needed universal solution.

8
V. CONCLUSION
Three different memory technologies have
been reviewed. EPROM is rarely seen in used in
electronic today due to its inconvenience in erasing
process and a rather slow read/write speed. Flash, on
the other hand, is the most widely used NVM nowa-
days due its electrical erasability and a relatively low
price. Two main architectures (NAND and NOR) are
seen in most manufactured Flash drives. There is a
trade-off between the two; NAND is cheaper due to
its high density cell, but its structure disables the
random access which makes NAND’s reading speed
slower than NOR. Therefore, the two architectures
are manufactured for different applications. Memris-
tor is the newest concept among the three. Although
it was proposed in 1971, there has not been material
realization for the device until recently. So far, metal
oxides as memristor material such as TiO2 and CuO
are the most extensively studied. There are still
many challenges which delays memristor from being
commercialized. Although many solutions have been
proposed by researchers, a universal one is needed to
bring memristor out of laboratory.
If we consider the storage capability per
memory chip as a function of time, we see that the
size doubles every 1.8 years, which means the densi-
ty of cells per chip also doubles every 1.8 years. To
keep up with this trend, we need some technology
breakthrough. In fact, manufacturers are moving
away from the scaling down cell size and looking
into new concepts. For instance, HP is collaborating
Hynix and promises to bring out their first memris-
tor-based computer in 2014. The success of memris-
tor will revolutionize many electronic applications.
Not only will memristor be much cheaper than the
current Flash memory, it will also reduce the number
of parts needed inside a computer. There are also
many studies on using memristor as artificial synap-
ses. In the near future, memristor will low-cost com-
puters to have the ability to remember like humans.
9
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