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MOS COMMON-GATE LNA Design Tutorial

J P Silver

E-mail: john@rfic.co.uk

Total equivalent input noise power veq2

1 ABSTRACT F= ≈
Input noise power due to the source only vns 2
This tutorial describes the theory and design on a MOS
Low noise amplifier using the Common Gate topogra-
1 + vn2 + in2Rs2
phy. Common gate circuits have inherently low input =
impedances and make them ideal when trying to match vns 2
to 50 ohm systems with associated NF of ~5dB. Design
theory and the relevant equations are given, with a Ideally F = 1
worked example using Agilent ADS simulation circuits
and plots. As the majority of the noise is thermal current noise
the Noise Figure of the common-gate circuit is given
2 INTRODUCTION TO NOISE MATCHING by:

From the previous article on noise matching we Veq 2 = vns 2 + in 2 Rs 2 where vns 2 = 4kTRs
found that the input of the MOSFET consists of
various noise sources including the thermal noise of Veq 2 = 4kTRs + in 2 Rs 2
the load and FET internal noise sources Vn and in.
The equivalent noise sources is described in the fol-
Veq 2 4kTRs + in 2 Rs 2
lowing way: NF = 2
= Divide top & bottom by 4kTRs
vns 4kTRs
With reference to Figure 1, the total equivalent in-
put noise voltage = Veq 2 4kTRs + in 2 Rs 2 in 2 Rs 2
NF = = ⇒ 1+
vns 2 4kTRs 4kTRs
veq 2 = vns 2 + vn 2 + in 2Rs 2 where vns 2 = 4kTRs
1
For the input match let Rs =
Vn gm
Rs
Therefore,
G
Veq 2 in 2
NF = 2
=1+ 2
vns gm .4kTRs
Vns =
4kT.Rs in
In 2 = 4γkTgm so

in 2 4γkTgm
Figure 1 Noise sources at the input of the NF = 1 + 2
= 1+
gm .4kTRs gm 2 .4kTRs
MOSFET, ie the load noise (thermal) and inter-
nal voltage and current noise sources Vn & in.
γ 1
= 1+ On the input Rs = so
Using the equivalent noise source we can calculate gm.Rs gm
the noise factor (and noise figure = dB (NoiseFac-
tor)
NF= 1 + γ

Typical values of γ (short channels) are 2-3. This

means that the typical NF for the common gate stage
will be 3 – 4dB.
3 COMMON-GATE TOPOGRAPHY 1
The common gate topography for this LNA is fo = and
2π . Co.L L
shown in Figure 2. The noise calculations of the
previous section show that we can match the input
directly to 50 ohms by making 1/gm = 50. The in- gm.Q LOAD
AV =
ductors L1 & L2 provide a DC return for the source Co.2π .fo
and drains respectively, they are designed to reso-
nate with the source capacitance and drain capaci-
5 DESIGN EXAMPLE
tance Co. The aim of this example is to design step-by-step a narrow
band C-G LNA (Low noise amplifier) to work over the
Bluetooth frequency band. A summary of the required
specification for the LNA is given in Table 1.
RLOAD L2
L1 Parameter Specification Units
Frequency 2.45 to 2.85 GHz
source drain Noise Figure <5 dB
Voltage Gain >15 dB
Co Power consumption <50 mW
Vin Vout Source/load impedance 50 ohms

gate
Table 1 Required specification for the Bluetooth
front end LNA.

Gate bias
For this design we will be using the Agilent CMOS20
0.5um process that allows a minimum gate length of
0.6um.
Figure 2 Common Gate LNA topography (sin-
gle ended version shown).
5.1 CALCULATION OF GM
4 BROADBAND OR NARROWBAND? We find that the input resistance is given by:
The load on the drain determines the bandwidth of
the amplifier. If we require a broad-bandwidth then VIN Vgs 1
we can use a resistive load where the gain will be: R IN = = = = ID λ
IIN gmVgs gm
Av = gm.R Load
So for a 50-ohm load applied to the gate,

Using R LOAD on chip 1 1

R IN = 50 Ω = ∴ gm = = 20 mS
gm 50
gm.R LOAD
Av =
R LOAD . jωCo With the required gm we can use the following
equation to determine the W/L ratio. For the calcula-
Where CO = Cgd2+Cbd1+Cbd2+CL tions we use the CN20 process model parameters.
ie Kn = 4.5494 x 10-5
Normally, the load capacitor (CL) will be the gate-
source of the following stage and will dominate Co. 5.2 CALCULATION OF WIDTH
For the purposes of calculations this can be esti-
mated to be ~ 0.5pF.
W
If we require a narrow band design (with potentially gm = 2.Kn.ID .
L
more gain) we can replace the Load resistor (RLOAD)
with an inductor (L2). The inductor (L2) will pre- So we pick a bias current say 1mA, we know we
sent a large impedance at the operating frequency want gm = 20mS and for this process let Lmin =
but won’t cause a large voltage drop: 1um.
Therefore, we rearrange to get W: Calculatio n of L1
1
fo = rearrange to get L1
gm 2 .Lmin 2π. L 1 .Cgs
W=
2.Kn.ID
2 2
⎛ 1 ⎞ ⎛ 1 ⎞
−3 2
(20E ) .1E -6 ⎜ ⎟ ⎜ 9
⎟
W= = 4390um ⎝ 2π .fo ⎠ ⎝ 2π.2.4E ⎠
L1 = = = 8.9nH
2. 4.5494 E -5 .1E -3 Cgs 0.48E −12

This is clearly too large so we have to increase the

current say by a factor of 10 to 10mA where we will 5.3.2 Calculation of L2
now get: The placing of an inductor in the L2 position allows
the amplifier to be tuned to the center frequency and
gm 2 .Lmin use the maximum potential gain of the stage namely
W= +gm.Rds.
2.Kn.ID

For the calculation of L2 we need to calculate the

(20E −3 ) 2 .1E - 6 output capacitance at the drain and also add the load
W= = 439um
2. 4.5494 E -5 .10E -3 capacitor (normally the Cgs of the next stage say ~
0.5pF, CGBO = 4.0921E-10F/m & CGDO =
A more realistic value for W! 2.8518E-10F/m.

Co = Cgb + Cgd + CLOAD

5.3 CALCULATION OF INDUCTORS
The input inductor L1 provide a DC path to ground
for the FET source but is open circuit at RF. We Cgb = CGBO(Leff )
need to resonate this inductor with the source-gate
capacitance given by: Cgd = CGDO(Weff )

5.3.1 Calculation of L1 Leff = L - 2(LD) and Weff = W - 2(WD)

For saturation:
Where LD = diffussion length (Process dependant)
CGS = CGSO(Weff)+0.67Cox(Weff.Leff) WD = diffusion width (Process dependant)

For the purposes of this calculation we will take We take Leff = 1um & Weff = 439um; CLOAD = 0.5pF
Leff = 1um and Weff = 439um. CGSO = 2.8518E-
( )
10
F/m. Co = 4.0921E - 10x1E -6 + (2.8518E −10 x439E −6 ) + 0.5pF
εox = εox . εo
Co = 0.6pF
Where
εs = dielectric constant for silicon = 3.9 and Therefore L2 =

εo = dielectric constant for free space = 8.854E F/cm -14

2 2
⎛ 1 ⎞ ⎛ 1 ⎞
⎜ ⎟ ⎜ ⎟
εox 3.9 x 8.854E -14 ⎝ 2π fo ⎠ ⎝ 2π x 2 .4E 9 ⎠
= = 7.3nH
Cox = = = 3.419E -3 pF/um 2 Co 0 .6E −12
Tox 1.01E -8

Cgs = C GSO (W eff ) + 0.67Cox(W eff .L eff )

Cgs = 2.8518E -10 (439E - 6 ) + 0.67Cox(43 9E - 6 .1E - 6 )

Cgs = 0.125pF + 0.36pF = 0.48pF

 dB(AC.vout)
m1
5.3.3 Voltage Gain (Av) 12.0
With the output capacitance estimated at 0.6pF we
can now calculate the voltage gain of the stage from: 11.5
gm.QL
Av =
Co.2 π .fo 11.0 m1
freq=2.400GHz
Assuming an on - chip spiral inductor Q of 3 Av = 10.5 dB(AC.vout)=11.949
10.0
DC.ID.i
1 10.17mA
.3
Av = 50 = 6.6 9.5
0.6E .2π .x2.4E 9
-12

2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8

(in dB) = 20log(11) = 16 .4 dB freq, GHz

5.4 ADS SIMULATIONS

Now we have calculated the circuit elements for the
C-S LNA we can now begin to simulate the circuit
to check performance against our specification
shown in Table 1.
The simulation shown in Figure 2 shows the LNA
complete with bias and setup for AC analysis. Note
that as the design is a C-S LNA the gate MUST be
RF ground and is achieved using a small value shunt
capacitor.
Figure 4 Result of the simulation shown in Figure 3.
To simulate the noise figure & input return loss, we
have to use the S-parameter simulator and two noise
sources formed using 50-ohm loads. Note that S21
transmission gain is a bit misleading as this circuit
provides voltage gain, not power gain but the noise
figure analysis using 50-ohm terminations will still
be valid. These 50-ohm terminations are set as input
and output noise sources, under the noise heading in
the S-parameter simulation box.

I_Probe V_DC
ID SRC1
Vdc=2.5 V
AC
I_Probe V_DC
I_DC AC ID SRC1
I_DC
SRC3 AC1 INDQ SRC3
Vdc=2.5 V
Idc=Ibias mA Start=2 GHz L2 INDQ
Idc=Ibias mA
Stop=2.8 GHz L=7.3 nH L2
MOSFET_NMOS Q=3.0 L=9 nH
MOSFET3 F=2400 MHz Var VAR Q=5.0 C
Eqn
Model=cmosn Mode=proportional to freq VAR2 F=2400 MHz C1
Length=L um Rdc=0.0 Ohm MOSFET_NMOS Ibias=1 Mode=proportional to freq C=0.40 pF
DC Rdc=0.0 Ohm
Width=(W/20) um MOSFET3
vout
Temp=27 Model=cmosn Var VAR
DC Eqn

DC1 C Length=L um VAR1

C1 Width=(W/17) um L=1 Term
C=0.5 pF Temp=27 W=439 Term2
Num=2
Z=50 Ohm
INDQ
C L1
MOSFET_NMOS
VAR C2 L=8.9 nH
Var
MOSFET2
Eqn
VAR2 C=10 pF Q=3.0 INDQ
Model=cmosn
Ibias=1 F=2400 MHz C L1
Length=L um MOSFET_NMOS
Mode=proportional to freq C2 L=9 nH
Width=W um MOSFET2
Rdc=0.0 Ohm C=100 pF Q=5.0
Temp=27 Model=cmosn
LEVEL2_Model F=2400 MHz
Length=L um
cmosn Mode=proportional to freq
Width=W um
NMOS=yes Tox=4.3500e-08 Rdc=0.0 Ohm
Vto=0.8756 Nsub=3.3160e+15 Temp=27
LEVEL2_Model
Kp=4.5494e-05 Nfs=8.1800e+12 cmosn DC
Gamma=0.4179 Tpg=1 DC_Block
DC_Block1 NMOS=yes Tox=4.3500e-08
Phi=0.600000 Xj=0.200000 um Vto=0.8756 Nsub=3.3160e+15 DC
Lambda=2.9330e-02Ld=2.3950e-07 Kp=4.5494e-05 Nfs=8.1800e+12 DC1
Pb=0.800000 Uo=573.1 Var
Eqn
VAR Gamma=0.4179 Tpg=1
Cgso=2.8518e-10 Ucrit=5.9160e+04 V_AC VAR1 Phi=0.600000 Xj=0.200000 um
Cgdo=2.8518e-10 Uexp=1.5920e-01 SRC4 L=1
Lambda=2.9330e-02 Ld=2.3950e-07
Cgbo=4.0921e-10 Vmax=6.0280e+04 Vdc= W=439 Pb=0.800000 Uo=573.1
Rsh=1.0310e+01 Delta=8.5650e+00 Vac=1 V Cgso=2.8518e-10 Ucrit=5.9160e+04 S-PARAMETERS
Cj=1.0375e-04 Tnom=27 Term
Freq=freq Cgdo=2.8518e-10 Uexp=1.5920e-01 Term1
Mj=0.6604 Cgbo=4.0921e-10 Vmax=6.0280e+04
S_Param
Cjsw=2.1694e-10 Num=1 SP1
Rsh=1.0310e+01 Delta=8.5650e+00 Z=50 Ohm
Mjsw=0.178543 Cj=1.0375e-04 Tnom=27 Start=2 GHz
Stop=2.8 GHz
Mj=0.6604
NoiseInputPort=1
Cjsw =2.1694e-10
Figure 3 ADS simulation setup for the C-S Mjsw =0.178543
NoiseOutputPort=2

LNA to provide an AC analysis of the circuit.

The 10pF capacitor on the gate of MOSFET2 is
Figure 5 S-parameter ADS setup to simulate
required to ensure an RF ground.
the noise figure of the LNA
The resulting plot from the simulation of Figure 5 is
shown in Figure 6 and Figure 7.
4.3
m1
freq=2.649GHz Parameter Specification Prediction Units
4.2
nf(2)=4.118
nf(2) m1 Frequency 2.45 to 2.85 2.45 to 2.85 GHz
Noise Figure <5 <4.3 dB
4.1 Voltage Gain >10 >13 dB
Power con- <50 27.5 mW
4.0 sumption
DC.ID.i
Source/load 50 50 ohms
10.38mA
impedance
3.9 Input return >12 >14 dB
2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 loss
freq, GHz
Table 2 Summary of simulated device per-
formance.
Figure 6 Noise figure prediction for the Com-
mon-gate LNA
7 REFERENCES
-14.0
[1] P.E Allen & D.R Holberg, “CMOS Analogue
-14.5
m1 Circuit Design”, Oxford University Press, ISBN 0
freq=2.652GHz 19 511644 5, page 85.
dB(S(1,1))=-15.408
-15.0
m1 [2] T.H Lee, “The Design of CMOS Radio Fre-
-15.5 quency Integrated Circuits”, Cambridge University
dB(S(1,1)) Press, ISBN 0 521 63922 0, Chapter 2.
-16.0

-16.5
2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85

freq, GHz

Figure 7 Predicted Input return loss of the C-G

LNA

6 SUMMARY
This tutorial gave the design equations to design an
LNA using the common-gate topography with on-
chip inductors. The use of the common-gate topog-
raphy allowed the LNA to be designed with an input
impedance of 50 ohms by setting the gm of the de-
vice to 20mS (ie 1/50).

A design example of a ‘bluetooth’ LNA was given,

with the associated step-by-step design process to
meet a given specification. ADS simulations were
performed to predict each parameter to check for
compliance against the design specification. The
predictions of the various circuit parameters of gain,
noise figure, power consumption and input return
loss, have been summarized in Table 2.