www.DataSheet.in NEC NEC Electronics Inc. Description ‘The uPD78310 and yPD78312 microcomputers are designed for use in process control. They perform all the usual process controlfunctions andare particularly ‘well-suited for driving de motors In servo loops and stepping motors. The processor Includes on-chip ‘memory, timers, input/output registers, anda powerful interrupt handling facility. The wPO78S10/312 is constructed of high-speed CMOS circultry and ‘operates trom a +8 V power supply ‘The input frequency (maximum 12 MHz) is derived from an external crystal or an extemal oscillator. The Internat processor clock is two-pt machine states are executed at arate o ‘shortest instructions roquir three states, making the ‘minimum time 800 ns. The CPU contains a three-byte instruction prefetch queue which allows a subsequent Instruction to be fetched during execution of an Instruction that does not reference memory. Program memory is 8K bytes of mask-programmable OM (uPD783%2 only), and data memory is 256 bytes Of static RAM. The /PD78310 Is the ROM-less version. APOTEPSI, avalabo in. 3088 aproteyping chip for ‘DPOTESIa It hes an on-chip OK EPROM insoad of ¢ rast ROM 1D Complete single-chip microcomputer = 16-bit ALU: 8K ROM (4P078312 only) — 256 bytes RAM — bit and 8-bitlogie 1D Instruction prefetch queue 16-bit unsigned multiply and divide {String instructions Momary expansion 1D — 8085A bus-compatibie — Total 64K address space Large 1/0 capacity, = Up to 32 0 port tines 1 Extensive timer/counter system it up/down counters timers —Free running counter with two 16-bit capture registors —Pulse-width modulated outputs = Timobase counter 1D Four-channel 8-bit A/D converter 1D Two 4-bit real-time output ports Two nonmaskable interrupts 1 Eight hardware priority interrupt levels #PD78310/312 8-BIT, SINGLE-CHIP CMOS MICROCOMPUTERS, REAL-TIME CONTROL ORIENTED T=49-19-0% 1D Macro service factly for interrupts — Gives the effect of 8 DMA channels 1 Bidirectional serial port — Either UART or interface mode = Dedicated baud rate generator 'D Watchdog timer 1 Refresh output for psoudostatic RAM {D Programmable HALT and STOP modes D One-byte cal instruction 1D On-chip clock generator 'D.GMOS siticon gate technology 148 power supply Pin Configurations 64-Pin Ol Seance be rsa rss 44175www.DataSheet.in . uPD78310/312 : 7 Pin Configurations (opnt) 64-Pin mntet NEC TSP1T-O8 Pin Identification (cont) Somat Fes rays TT port iar send np i Ratresh output F/G Upown cout Opa P/CTHID —_Up/down cout 0 conoligut Face down coir Tnpat agra Up/down enone ¥ con pat Xi Berl expt Extra cock pat @ —reral esta its ower eum ‘igi ArD converte aps Nace Ao eee vo es Aalog ground FalPUi VO prtvPuce wat modes ope FZg(PHnIt WO pat Pe wie modulated ouput ‘x CLRO/TOO 10 por 3ourte 0 cer pT 00 eq /OLRITTON 10 pot Gaur tear ipa Tiner Foutut ‘aiaiAgg VO port sigh adress yt utat a xtra cae onl ipa Exora eset np ead strobe out ‘Wet tobe ouput information ed Petage Tet ‘eon sie srnk OF aoreoc ore Pe OTE Pores 20-8 sores (oTes120-18 POTESIOL pore ‘atte Tae ‘tin plaste iat Tae eens Tae Pin Identification ‘Sata ope ry Ope onmasabi arnt WO port 2/Srt cock outgut ower spay Pin Functions 0p-PO7 [Port 0}, Port consists of 8bits, individually programmable for inpuvoutput or two 4-bit real-time (timer controlled) output ports. Pto-Ptz [Port 1] Port consis of bits individually programmable for Inpuvoutput. P2g/NMt Port P2q|s dedicated to NMI thenonmaskable external Interrupt request. P2y-P2y/INTEO-INTE2 Ports P2;-P2s are dedicated to INTEO, INTE, and INTE2, the maskabte external interrupt requests.www.DataSheet.in NEG — 6427525 N E C ELECTRONICS INC PaytxD 2; a an VO port bit or the transmited saial data output P2s/RixD 2 isan VO port bit or the recelved sora dat P29/SCK 2g an VO port bit or P27/6TS 27 Is an 1/0 por bit or clear-to-send Input (extornal Serial transmission control) in the asynchronous ‘communication mode. In the serial I/O interface mode, It becomes the serial receive clock 1/0 pin: FSH RFSHlis the retrech pulse outputto be used for external seudostatic DRAM. Pag/cio Port Pas dedicated to C0, the external count input {or up/down counter 0. input. 1 soral shift clock output, Pay/CTRLO Port P34 is dedicated to CTRLO, the external control input for up/down counter 0. Pop/clt Port P32 s dedicated to Clt, the external count input for up/down counter 1, P99/CTRLA Port Pa is dedicated to CTRL!, the extemal control Input for up/down counter 1. ‘generate the system clack, The system clock frequency {is half the input frequency. x2 X2 isthe second connection for an external crystal Vss gg s the power supply return, normally ground. uPD78310/312 > 980 13464 ‘ANgrANa TF SF19-0F8 ANorANy ate the four program selectable input channels forthe A/D converter. Aner ‘Aver Is the reference voltage input for the A/D ‘converter. AVss, ‘Ags 8 the analog ground pin Pay/PwMO 3g is an 1/0 port bit or the pulse-width modulated output. P3g/PWH 3, is an 1/0 port bt or the pulse-width modulated output 1 P3e/CLRO/TOO 3g is an 1/0 port bit, or the clear input for up/down ‘counter 0, or the timer Ofip-lop output. PRy/CLRI/TON 'P3; I an /O port bit, oF the clear Input for up/down ‘counter 1, or the timer 1 flip-flop output. P5e-P5z/As-A1s [Port 5] PortS consists ofBbits, individually programmable for Input or output, or the high-order address bits for external memory. Under control ofthe memory mask register, bits P5-P5s are used for 4K memory pansion, bits P5-PSs are used for 16K memory pansion, or bits PSy-PS are used for S6K memory ‘expansion. EA [External Access] On wPD78SI2, a low on ER onablos use of extrnal memory in place of on-chip ROM. The EA pin must be tow on wPoreat0. ESET ‘This pins usod for tho extornal reset input. A low level sets all registrs to their specified reset values. aD AD isthe read strobe output Its tobe used by external ‘memory (or data registers) to place data on the /O bus. during a read operation. 477HPD78310/312 : wa WA is the write strobe output. It Is to be used by ‘oxternal memory (oF data registers) to latch data trom the /0 bus during a write operation. ALE ALE Is the address latch enable, It is to be used by ‘external circultry to latch the low-order 8 address bits during the fist part of a read or write cycle. Block Diagram www.DataSheet. in Port 4 consists of inputor output, ora the mult if external memory of external ite Used, The port Is controlled by the memory mapping register. Voo Yoo Is the positive power supply input. eres Sef recy ted si=h1| ee ane —| fee o 2 Lam x a Ee a SL ie =] |||}Es oa la= re \ a78www.DataSheet.in NEU uPD78310/312 4 TYVL9-OF Functional Description (On-chip features designed to facilitate process control Include two 16-bittimere, two 16-bitup/down counters, two pulse-width modulated outputs, a free-running ‘counter with two capture register, two 4-bit real-time {Qimer controlled) output ports, an 8-bit A/D converter with 4 input channels, a timebase counter to generate widely spaced interrupts, and a watchdog timer to ‘guard against infinite program loops, Inaddition there Isa serial /O port which can be used in elther an Interface mode’ or an asynchronous ‘communication mode, HALT and STOP modes are provided to conserve power at times when theaction of the CPU isnot required, ‘All VO, timer, and control registers are defined as ‘special function registers and assigned addresses in the top 256 bytes of memory. The special function registers may be operated on directly by many of the arithmetic, ogic, and move instructions of the CPU. Table 2 at the end of the Functional Description doscrites the registers, ‘The uPD78310/312 features 1-byte addressing of the ‘special function registers and 1-byteaddressing ofthe Internal RAM. There are nine modes of addressing ‘main memory, Including autoincrement, autodecre- ‘ment, indexing, and double Indexing. There are 6- and 16-bit immediate operands. External Memory External memory (ligure 1) Is supported by 1/0 port 4, fan €-bit multiplexed adéress/data bus. The memory ‘mapping register controls the sizeof external memory as wal as the number of addtional walt states, High- order address bits are taken from I/O port 5 a8 required. No bits are required for 258 bytes of extornal its PSp-P53 are used for 4K bytes, PSo-PSs {for 18K bytes, and PS9-P5;for58K bytes, Any remaining ort § bits are available for /0. Refresh ‘They/PD78310/312has arefresh signal for use with the pseudostatic RAM. The refresh cycle can be set to one. Of four intervals ranging from 2.67 to 21.3 us. The refresh Is timed to follow a read or write operation £0. ‘that the CPU does not have to wait. General Registers ‘The CPU has 16-bit registers (figure 2) that can also be used In pairs to function as 16-bit registers. A complete set of 16 general registers Is mapped into ‘each of 8 program-solectable register banks, stored in RAM. Three bits in the PSW specity which of the register banksisactiveat any given imo, Each register bank has two program-selectable accumulators. Figure 1. Memory Map Figure 2._ Register Designation and Storage 4179"WE C ELECTRONICS INC 98 DEJ 427S25 oova4E? 2 6427525 NEC ELECTRONICS INC > uPD78310/312 Program Status Word : Following is the program status word format. 98D EC TeYP-19-08 Figure 3._Pulse-Width Modulated Output The inputsto these timers may be the internal clock divided by 6 or by 128, Each timer has an associated modulus register tostorethe timer count. The timer counts down tozero, sets.tlag, reloads from the modulus register, and then ‘counts down again. The timer flags can be used under 6 8 0 [ree [res [reo[ o [ o |e [0 u : 0 Ass] ac | ur | pv [sup] cv RBz-RBp Active register bank number te Interrupt enable 8 Sign (Vif last result was negative) Zz + Zero (1 If ast result was 2670) ss Fogister set select aS ao Auxillary carry (carry out of 3 bit) UF User flag “The PD78310/912 has two 16-bit Pv Parity or arithmetic overtiow SUB Subtract (1 If ast operation was subtract) oy Carry Input/Output Allports may be used fo either latched output orhigh- Impedance input. All ports except port 4 aro bit- programmable for input or output. Port 0 Is used for Teal-time or normal /0. Port 1 Is used for normal /O. ‘The low nibble of ports 2 and 9 Is always used for ‘control and the high nibble for control or normal 1/0. Port 4 Is used for the external address/data bus or byte-programmable VO. Portis usod for thehigh bits Real-Time Output Port “The real-time output port shares pine with 1/0 porto. ‘Tho high and low nibbles are treated separat together. Data is transferred from a buffer to the port latches on either a timer or software command, Serial Port ‘The serial port can operate in UART or interface mode with the baud rate and byte format under program al port also includes a dedicated baud Pulse-Width Modulated Outputs “The two Independent pulse-width modulated outputs fare controlled by two 16-bit modulus rogistors and ‘counters. There. are four programmable ropetition ‘ates ranging from 91.6 Hz to 23.4 kHz. Figure shows ‘one of these outputs. program control to generate interrupt requests and/or ‘2 square-wave output. TMO also functions optionally ‘8 two one-shot timers Figure 4s a diagram ofthe interval timers. “Theresa free-running counter that counts the internal clock divided by 4 or by 16. The counter has two 16-bit ‘capture registers. Capture is triggerd by an external Interrupt request or by the up/down counter clock. ‘The timebase counter generates.asignal atone of four intervals ranging from 170s 0 175ms. The signal can be used to generate an Interrupt request and/or an up/down counter capture. Up/Down Counters ‘The uPD78S10/312 has two 16-bit up/down counters, each of which has two capture/compare registers. ‘There are three modes of operation: compare and interrupt, capture on external commend, and capture ‘ontimebase counter command, Thereare ive sources ‘of counts: the internal clock divided by , the exte ‘lock, external independent up and down inpt ‘external clock with direction control, andexternal clock ‘with automatic up/down discrimination. Figures shows an up/down counter.NE C ELECTRONICS INC 48 DEM e4e7s25 Ooaues 3 NEC ‘Figure 4. Timer Block Diagram r 6427525 NE C ELECTRONICS INC >> #PD78310/312 98D 13468 —— Standby Modes HALT and STOP modes conserve power when CPU ‘action is not required. In HALT mode, the CPU stops ‘and the clock continues to run, Maskable interrupts ‘can restart the CPU. InSTOP mode, the CPU and clock are boih stopped. A ESET pulse or the nonmaskable external interrupt required to restart thom, ‘Theres also the option ofslowing the system clock by 8 factor of four. The standby control register controle the standby modes ands e protected location written to only by a special instruction. Watchdog Timer ‘The watchdog timer protects agains inadvertent program loops. A nonmaskable interrupt occurs ifthe timer is not resot bofore a timeout occurs. There are {our program-soloctable intervale ranging from ~6.5 ims10849.3 ms. The watchdog timer can be disabled by software. The watchdog timer mode register contro the watchdog timer and isa protected location written to by a special instruction ‘A/D Converter ‘The A/D converter has four input channels and can ‘operate in either scan or select mode. The A/D Converter performs 8-bit successive approximation conversions, has a 308 conversion time, and is triggered either internally or externally. The A/D converter includesan on-chipsampleandholdampiiie, 41816427525 N E C ELECTRONICS INC uPD78310/312 Figure 5. Up/Down Counter Block Diagram NE C ELECTRONICS INC 98 DEM G427525 oOLIuLS 5 r 13469 NEC T-VICP-O8 > 280 : 4 : Interrupts ‘There are two nonmaskable interrupt sources: the external nonmaskable interrupt and the watchdog timer. Their relative priorities are software selectable. “Thore are elght haidware priority interrupt levels, level Ohaving the highest priority and evel 7thelowest. The fifteen maskable interrupt sources (table 1) are divided Into five groups, and each group can, under program ‘control, Be assigned to any one ofthe priority levels. Interrupts may be serviced by routines entered either bby veotoring oFby context switching. Context switching automatically saves all the general registers, the ‘program status word, andthe program counter. Figure B illustrates the mechanism of context switching, Finally, there is an optional macro service function that transfers data between any one special function register and memory without program intervention. 4-182 Macro Service ‘The macro service controller can be programmed to perform word or byte transfers. It can transfer data from a special function register to memory or from ‘memory toa special function register. Transfer events fare triggered by Interrupt requests and take place ‘without software Intervention. ‘There are eight macro service channels; channel ‘control information Ie stored in RAM. This information (figure 7) consists of a 16-bit memory address (optionally incremented at each transfer), an 8-bit ‘special function register designator, and an é-bit ‘ranster counter (decrementodat each transfer.) When ‘the count equals 0, @ contoxt switch or vectored Interrupt occurs,NE C ELECTRONICS INC 48 DEB eu275es ooLau70 3 6427525 N E C ELECTRONICS INC fn | 98D 13470 uPD78310/312 7 ¥9. are Tablet. Interupt Sources and Vector Addresses aoe, Dota ry Tarr a ara Sree Yer ionasabi ineropts = ‘a oak nsrucion to ‘woo = ta Enteral anastatle inert te (act S wor Watchdog tier to roa irate aap 7 ‘cae Up/down enue Yee oa 1 ‘ce Uprdown courte to ‘nice 2 RED Upidown enue J anes 5 et Uprdewn enter to at 7 BOD Eceralterapt Yes ‘oar 5 uF steal ieterpt 1 Ye (ost 6 Bre Eteralteapt2 Yes oat 7 TF Yes ‘aoe 6 Wet Ye ‘oon & M2 ve coat 0 ca ‘Sera part ear Yo ‘waa " Se ‘Seal part eave ute. Yes (oat 2 StF al prt ve at e 30 ‘AD converter done fag Yes ‘wat i {oF $ibase cot tag te oct RESET Extent moat Figure 6. Hardware Context Switehing Figure?._uPD78912Macro Service Pointer Addresses 4183NE C ELECTRONICS INC 98 DEB} Gue7525 O0L3472 3 C 7499-19-08 NE uPD78310/312 - 6427525 N E C ELECTRONICS INC D> 98D 13471 Table 2. Spoctal Function Registers : fei? isa Tea ios Font wie Tria su roar Topo RW We Trane irom Topo t Pt RW No Unde rear Open % mW noice) Unified Fr Wogan Fa aww No(Netet) Undine Fro Wopons Pe aw te Uncen res opens 3 iW te Undine Freee Capurelcomparrepiter00 coo RW Yer Undine Fra é cn “ Fran Capture compar reir OF non aw Taine Frc ao Frac ‘aptrelcaare eit 1 rm aw ve reeves roo rank Freee Capure/conpar register care aw Ye rates Fru car Fro Tapas vier rom FRC) ra aw ve Trane Feit CrrOH : Frav Capture ves ¥ rom FRG) ww Trasnst Fr Ger Fw Pu rete aaron) Pao. aww ve Trae Frist Pao Fer Pun ager (arson) Pai aw ver Tadeo Fa Pat Fria estab pldown caaiorD ‘oot aw ve oan a eae frien Presetabl up/down count oct iW Ve Triste FFP oct Fram Pot mode eit Pa Fa Few ort med eter Pa Fi Fran ort? de egitar Pie FH aw Port mde estar Pa lw te Fa ra Prt mod egitr Pa are te FF Fra ort 2 md contol aia Putz rw We OF co ert mde onl eater Pcs a Ne OF Fr ean tpt por conan ATP oo Ne 4104NE C ELECTRONICS INC 98 NEC bua7ses OOLa472 § uPD78310/312 6427525 NE C ELECTRONICS INC _"D 980 13472 Table 2. Special Function Regltere (cont) T2YP-19-08 ta 108 Tet set fxn a ee en Fen irr 2) iL a to Tadted Fa A an te ct Frage “Memory mapping register co WW No _ Fra ~"Rettash mode register AFM AW No ra aie ner node a wai ci ie aa Sindy con ie sree wi ae ira Tass deri i an iret Tirade ea i ai iran sev ery ei is an rae CF coo werd ca an Fro ‘Serial communication mode repister = ‘SoM aw Fra ‘Serial communication control register ‘s0C aw FSH ‘Baud rate generator ‘BAG Rw ~ ia Sera ema ae Be [a " Unde iran Serial comet vant ae 1 w Undine ire Ta a ‘ai rea cri ar cl io naw ‘ai ‘Freon AID converter mode register ADM mw co FrGAN AID converter result register ‘ADCR a = ‘Undefined irr os tio med ei cat 7 te irra down oe ea rir ‘ace wa te irra Capuron eli ce iw to ‘Freon ‘Timer 0 control register TMC RW Wo Co ‘Fro “Timer + control register Twcr aw No co ina Tine To mW Yer atid Fast Te FROAH “Modulus/timer register 0 ‘w0oL aw Yes, “Undeting Fah tom Frac Timer “TL aw Yes ‘Undefined Fat - mk ‘FreEH ‘Modulus register 1 ‘MOIL wes ‘Undefined rae ton iat Eieralawa iow fr 4105“TNE € ELECTRONICS INC 98 DEM bu27S2s oo1a473 7 uPD78310/312 Ni KE Cc 6427525 NEC ELECTRONICS INC | D gen 13473 Table 2. Special Funcion Registers (cont) FY F-19-08 fear Toon © hue ewe fc smneie imate ‘i Feat aa ara a a FFG ace ee et Tider Ci WW ___"no aed Fa rep atl “recite no OH West Thiers cour o8GHD AW to FFOSH Macro service control 10 “Upldown counter ‘CRMSIO AW 2 ‘Undefined ‘FFOGH Interrupt contrat 11 Upidewn owner ONICTT RW Wo aH ‘FFCBH —_EXIFO interrupt control External interrupt EXD RI Wo. aH FF Dima svi coal ential 8060 Won fea 01F nwa cont sat x a ‘FFCOH EXIF macro service control External interrupt oust RW No Undetined FFCoH Ene nterut cont Enteral itrugt XI “wo am FFE DaFa mac seven coil ‘irae es? a ro) fetches Tir. “tics aw a FFCFH ——‘TMFO macro service control Timor flag TNs RW Wo “Undefined FON TFT coe Tinta Ti ‘wea FO Tama ev ct Tinea ‘wisn FF TH con Tina ice _——aw tea FTO TW mar seve Tie Tse An Fon earn cota swale set awa [FFOCH Receive interrupt control Serial pot ‘SAIC RW No ae Fon vrai comel apo sia fino FFDEH Transmit interupt control ‘Serial port sTie RW ‘No aH FORK Tra ar sven tal Swat smi ‘to ant FFE AD ava reo Ae wean FFEIH A/D converter macro service contrat ‘AOS RW Wo Undetined FFE Ties cuir tr cml 7 7a “ie FFF Saccpoe i) ce Yen ein eo Se _ Frei ryan saa wad ie TW ae fa rs oe (1) Bs 08 ot por 2 and pont are eee (2) POH and PL ee 4b tar ragltre td to store dts oe laaded int the igh an low ila of he eshte output (PO), (0) 849 ofthe STE knot afected by RESET (n= 00r8), (a) Exora realtors inraces wh thee adrerts canbe acceead by speci! urtion register adresing (6) SP and Paw do not have real SFR adereses end canbe accossed ony by speci instructions. i 4-186NE € ELECTRONICS INC 4 NEC - 6427525 N E C ELECTRONICS INC Instruction Set The instruction set for the wPD78310/812 has &- and ‘16-bit arithmetic instructions including a 16 x 16-bit Unsigned multiply with @ 32-bit product and a 32 by 16-bit unsigned divide with a 92-bit quotient and a 46-bit remainder, The instruction set also exoutes an S-bit and a 16-bit shift and rotate by count, and -bit logic, and 1, 2-, and 3-byte call instructions. String ‘manipulation instructions are also included. ‘There are four addressing modes for unconditional branching. Branch instructions exist to test single bit inthe program status word, the 16-bitaccumiulator, the function registers, and internal RAM, ‘The Instruction set also includes multiple register PUSH ‘and POP instructions, Following ‘are several tables explaining symbols, designations, and codes inthe Instruction Set. Machine Codes are omitted from the instructions but they are in ‘the User's Manual 8 vey bye7ses Oo1ay7y 9 = P13 ay H#PD78310/312 D> 98D 13474 — Symblin the Open and Oporton Comms in Tt ae ism aa we 2 ‘io brs fot — BRP ra on Beam eae a apap erie necat sepa sir eel tee Poy reurn pe (OE BEL La (E+ A) FL + 8,06 +9), 0H +, +06, (VP +H; baceindex nde (OE. be) HL yt) (VP + bye) (UP + bt, (SP +b) base moe Wed (word) ors 06, word Ly: nex mode FO} FFFHEimmdiat yt acbeses on yt RAM, ‘riba ‘adirp FRADE FFTFIC mae ye ORO =O) adresses oe word n RaM “Wits of immediate data is of meats data we ne {sap it to's conplenant dlplaanent Gnade Gat ‘it Sb of metas data poston in byt, or abel — 2 Sbis ofinmedae dig ‘Gr Oma FEFF 6 inaaa aes pw FFF MO nto) inde Son FEFRH: 6-1 cba anc adress Gmdiate data) ‘Sadia ah wane (POI) ‘Gr OSE OFF OOH (1- ineedneaan), Or aba 5468 00a 00TEH coHOH +2 (I mea abs), or tae 4187NE C ELECTRONICS INC 98 uPD78310/312 DEB eue7ses 0023475 0 T NEC and} neat ta aden seemed at or 6427525 N E C ELECTRONICS INC »> 98D 13475 Symbols inthe Operendand Operation Columns (cont) Flag Indicators i gg POL co - | ier ne restr a c C register — £ ‘Set or cleared according to result eo hater e v ithmetic avertiow « v Undefined ~ t ~ Restored from saved PSW _ Exécuton Tins of tmory Reference Instueton: umber f Processor Saas ad ar ae rs we ee APO-AP? Register pait O7 ~ Pe Program counter — 5 ‘ eae — we ‘User stack point xr Amen 7 8 8 FSW ‘Program status word conan mem, cary tag a a ‘Raxllary carry tag ‘AN, 08, xon_™2™A 7 8 Zz Zero fag CMP ‘Amen . 7 7 T eT won s Sign t iy eae Memory Adrssng Modes rr aa oe TT TE TO ee igor tar SS Register set ag tates isan Buse oo EAE) ee WA wa 06 coco gr ey roa Seo ‘Wow ichéog Umer mode rep SA ty LB) (UP byte) _word (8) 1) Cones ate ocaion iseaeraaie wo TT (wrs-0e|_ (rb) = a eroenad before sed ontans fe mayen dtd bye contents fe ection dete by he guanylate 57 Headecnat umber XHAL__igh-order 8 bis and low-order 8 bits of oO * ep and rp cescrite the same regi, out ganeate ateront Imschine code, 4-188 cyt intvtions deiad by spell opeads and mam ony.NE C ELECTRONICS INC 98 DEB} bye7S25 OOL347E @ T 7-99-15 -08 #PD78310/312 NEC — 8427525 NEC ELECTRONICS INC _p> Gonera! Registor Designations an a w 98D 13476 Tanna a aan -eceeiayg Eeeoenels| 70 fr 2 =210) 5, % 2 ‘s | 4-189NE C ELECTRONTCS INC 48 DEB eue7ses aona477 4 Of i HPD78310/312 NE ¢ 6427525 N E C ELECTRONICS INC > 98D 13477 | —— a YF-19-0% ‘Mneranle Sparen Operation Sates Byles z x or ino, re =e 22 (e260 = (di ee es ase Rom A= (nea (em) =A mem.A (en = co A= (ad i (cae “Rawars A= (oie) i “aan aga Faw — bye ee ee FW = byte i FWA PNA a N= eae an iam a a oe A a “Aiatap) A eae (sed) — (eae * A paca instrcion suse io we to STBC and WDM (ee below. * One-bjt move nection, 4-190We € ELECTRONICS I 0023478 & NE C ELECTRONICS INC 48 DEB) bNe7S2S OOLa4 T NEC Jporesieroe — €427525 NEC ELECTRONICS INC = _pD 980 13478 {Instruction Set (cont) Tine Mme __Opeand yetee suse Sa ov ep tword ot word as adr vor (sed) = war rE! “sip vod p= word a4 z met eat = Risiip X= atte s 2 TO (Gain) — AX s 2 a (cad) = (689) oa neh 72 sig AK se aw aK en) ._ 2 = A st 3 = (sei 3 = i io ade ar ‘em YA Un “pan AY = ma) FA 73a on Aare AG Av bye + ane i ye Gf ere et ees ea a0) >be CY 7a se ‘ACY As Gad 3 AC Asa +OF 3 (ead, CY — . a (ead + ade oF AY =—As (non) + Y erie SR ane Eg WRENN (an), OF = (nan) FAT 78 ed kK KV 4191SS LL | WE € ELECTRONICS INC 58 DEB G427S25 OOLZN7A B t | #PD78310/312 NE Cc 6427525 N EC ELECTRONICS INC > 980 13479 Instruction Set cont) Z-YP-19-OR cuts part Sra sway oo ‘At ‘ot Abe aa V1 x sed. oe (ase, (aaa x 0 — sr et x nor a x OYA (ah ae ee x CEE eax x ev wake Kv Goh = Ase 79a 04 SAGX SS NEV SEES ESE ee \ 32 a a a oo {sade = bte— cv ai Poe sists —bye=o nA no=r= rio ae XV x “haley «#0 ae eX AGP Ar sk OF @ sx x * V1 x 7,0 = ose Kx leet) esto Rem ae CE ‘mam. A (em), CF = (men m™ m4 x xX xX Voi ino om A= ANDO aa x XP er (ead — (a Ae oa sty t= srr a tran 3 2 * x . o AE AA Goats) of * x JU oo AAAS ss x x« vu PO 0 I est = Wal Aoi) SSSI O09 NS Kin x oe URN i 2 =A on ea p24 aN Ket x ADEE PCE OEE | ‘ova = ond AA Ta 34k a A= AV aoe ee UP ‘sacar, ye {ead — (ead) V ye 7 ax v oO ‘ir foe str = str byte 7 x v Oa +L ke rae oe ‘Asai REA Gaal Fe Kate A= AVst osx xP ia) eta Vindsy 8X i K=AV en aU 0 | (nnd (oon WA 7x ue 0 i t 192 |NE C ELECTRONICS INC 98° DEB Gua7ses OOvavao 4 Bf T19-9-0% NE Cc eee ~~ 6427525 N EC ELECTRONICS INC D 98D 13480 — {Instruction Sat (cont) ae Meaney opand purton a a ion Ate AV bie a2 x UP ao ‘sr oe (cata — (ati oe ieee oe x UOT sete simsit fe aa 7 rae See 9 ener aed eNO ‘Raid A= all See =o xe ee ere Co ES ‘sr attr att = (wear wale 6K ‘Aan [A= Aa oom) xX xu Pee ema (ean) = (mare OES EE ST our Ate ‘Abie ste a x SX KES Vee sate ne alte aa Sone ety ene aE Reade AS nit) a8 het eee Oe ees ea VV ‘a (sedan (ea) See mses gees vg AGES Vile ‘Aman A (om epoca rere Xe VRE ‘aan A (am=k Yt oow XO AG word ea os aU ee ae scar, rar (audi) 0 —(adereword 8 xx yx so. teord ai. Y= sp + word Sx xv Vek evi ie cc WS WTO EX sate 1,07 = A+ 6) ee ene XO Veo sip RG OFA stp re eae UR VOR a a a (caer car) Saw er RK OF — AX Word CE SS : sadn avoid abe, OY — Gade word BX SD i ESO OV oe = woe 6 RENE FRA UNV TP \ sap RO AC oy) EE OES OSX GNX UE Veen Ti 52 SES A, = IX ap se SRN NSE XW SV “sar s06h— este — (sao) aden) aad AX word sxx ove “satay, word {sadarp) — word ee eee ee ceeaeeeme ‘so, tword ip — word ee ‘wut or ee Asp [AX (aoe) eae sto Cen 73 xx “tai, a6 (cacy) (ep) 4-193uPD78310/312 6427525 N E C ELECTRONICS INC dD NE € ELECTRONICS INC 38 DEP y27ses 0013483 & aC NEC 98D 13481 ——— TEVH-(9-OF Hanile tyrant Spsrton sues oye aaa waa ARH 2 owe a WX (Gtets ena) — SSC aiken ww i 7 ig Oso ah, a2 (Bt Ue Oger 1 - Pix _ at ‘HOE Oven. wT Pemainda het ie a aenty ate ee VO ‘ir (eat) ea rans tN Yew NV im a ne ia uae Nx Sv ‘aa (aig eaia-t CC itaw rH a eT zt ‘it (Gaidr) — Goan 1 . 3 meen ew ae eet at ‘act (coe) — 080) ss —__ or ra (Oh =e im) Figet et 8 ior rr Figg 1a) aac we r= is cr a a : nye Hottie) moe Tha an ae x DP foe Hogs tte) x9 Sm ce mre cr rs z tot Hyatt a Ta ae ee aw ohn ie KCK ‘8 (matted x8 aw = is cr a a "0 ‘m1 Pe) one wo Foo Cia, * 2 xo Po (ota Ae (cto O04 oa ‘oon Fag Co -« a a (ihe g eas (iota (08-0 ie Tecinal Adistacaundatoe CT e104NE C ELECTRONICS INC 98 DEM) B427s25 OoLauae 8 TP? NEC ieancet 6427525 N E C ELECTRONICS INC =D 98D 13482 Instruction Set (cont) ene an Aperton Sater oye z aa oF won yess oY = ser +3 ¥ Cresta r= steit ee : Cr, Ab Ani oe oy, xb EB an eee 60 ge oy, Pama = Pav emeeae! x YL x= tm cme OT x sei OF acon) — OF os “set sbi OF rama ‘ADL OF ee xbi=Gy SS ‘Pawan oF Psat oF (samme _ ‘PowLn.cy—__Paiiean—cy SS | Biot ‘Y, saaarbit CY = OF A (sade) oe a iisaiecot Yor aimaien CC ST se Y= cr Aart . 3 x Oy,Abt «YA ie ae 2 eee x Crab Y= cvAABT s 2 x i I. A eo 2 ‘wat 62 SC, Pn eR CY. CAPO ce 0 NT “Desrswnien ev Cr APM o 2 — De powLon ever. ee Cyst = Cra RaW a 2 om ry, sie Y= eaaer cman ¥ Cisne OVC (oa ee 6ST SI! ct Woe ee 9 greg Gite Omovverak Want ev=orvann SS x “Cyaan vcr o 2 x ‘Ween ev ervai SS x wor ov evvEor ieee aes x Wy. rewitt ev crv Fea (i Gy /eswiot er YVESyBE He Wy, Powe CY = CVV PSI Bt eee x Al 4-195WE C ELECTRONICS INC 8 DEM bue7s2s 0013483 0 HPD78310/312 TYP-19-08 NEC . _— 6427525 N E C ELECTRONICS INC 98D 13483 Instruction Set (cont) emore <—_ oped Syren oar (oy sect Gr = OF acai craton y= vast OAD OAD am v= ova Ki [A Ce “O.RoWLbh Cer POWL sr sadicbit ‘ead a) = 1 “aot == ee Os nS Rb cea xen Xo Tema Fant ewLat rant om ‘sara (ex ‘aon 5 A S07 2S S00 ri uano owe Fao 72 —___ iim ‘eae (codon) — Gad o 3 “eo edit se 73 M “Adit — Re ae CSD Femina Santon awn aay o ore eaa st o am or wo at o tori or ane ot x oa Tater e704 Oe . 3 -3— CCI: Fo aeare, eased ca saat (ey 0or A 72 2 (S0-2— +2; Po agent: eed Ca) e-9=Pot Te wt (e-9—po+ ny Poy TPEADEO as +1 ' Poy = PPE + ast secre 4-108NE € ELECTRONICS INC 98 DEM G427s2s voiaya4 1 i NEC IS 9-08 4PD78310/312 —— 6427525 NEC ELECTRONICS INC |= D 98D 13484 —— Instruction Set (cont) fa Mowe onan son seus _ 0 eat Caigeeaant == HT alga Ga per a Simin recat Sete wn E-9= (the WF G3 erat reson nae im == Fm ca ‘aut fe-3— pet n. frog — pea nt fee rei ar are @ = Oh coe en ogra en FL GM rr FO) — (+ 1, roll "ie Wh (83 Spat geet es—0 mam vest asa post = a wee ane wate Bxe. iw ot (ost — m2 (Beet + SraSerann a 5 Fh = Salo ares ‘pon = OF, ee =e 9, ann ina Ford i z 4 now # eer ecw sr eae 4197WE C ELECTRONICS INC 98 DEM b427s2s an23uas 3 6427525 N EC ELECTRONICS INC => 98D 13485 uPD78310/312 NEC T7919 -OF Instruction Set eon) Tar termes “oni ain sumo 3 i ro r= a8 7? wt Fore . ies ot) Pon (the eecae __ faa re air Taal aC ‘sedari6 PC = aderie CY = 1 73) = a i aa nae aaa me : oz ait az air eo eat a2 a ing ae eo waist co ate wv ‘sa0erie 8 2 ~ te : aw are ae ey EI iar re nwaren=7 m2 - wr ‘sade ~ PO adaribnS=0 78) 2 vei ars rem aaiion Ova VESO 90) 3 ace sees rem aires 0 068 at feos ro= aarnrves=1 68) 8 : ate toe rem aaron eNeSNE=T 08 BH ‘Sadar PC = acdrie itz + CY =O 18) 3 = ani ss ren acirsnzvor=t 898 ar a 3 “tak 0506 a “na a 3 oi 3 3 3 oF : —_ ‘Abit Sedirt6 2 ~ Xo ei 3 Pini fais __po=-edarePSMDI=O THO) <__Fevton, eerie Fe —aearenFoMot=0 HO Brean sn a wm Beare FE a we — Tate Fe — associat ~ ferrets AI 4198NE C ELECTRONICS INC 98 DEBfeverses UULS¥BE 5 Tr 7YP-79 08 NEC uPD78310/312 ~~ 6427525 N EC ELECTRONICS INc 2D 98D 13486 Inston St eon) Ban iat eia re aapion=] ——ay —S i Toit Fa ae Rea Taya iO a Fe PTT a ata aba =e aT Sado a a on Shand ra Ta ea TS Tada a a Basa = Fem ais — Pe aT GSO Saad OWL. Sadsr16 PO adert6 I PSW, ba =O aeeeeeeae bat aa $e we F Sard ane 7 mana = ma a ine as Res tt, ten pantie ao io ae coer Toe ron Bea K a Pee ewte-0 ise een im a ae -_ OE) Oo 2402 teh on me me wean ee ae Conn endtc=0 4-199WE C ELECTRONICS INC 48 DEB buerses ULa4ee + of #PD78310/312 Ni TF Cc 6427525 NEC ELECTRONICS INC 98D 19487 Inetruction Set (cont) 59-09-08 a vt ee foo es.) aie 2 PEE ono oie) ae 2 faerie aarie ETA we iensnenourz~o oar or oe-& CSE Nensc=oorz=0 arene EN. LAT oe, Lee Et recoez=s i tim 2 eee WG € ee Nennc~oorz=0 urns EH Ge ea Ke Bei enanc=oorz=1 =a pey-k Cm CLEA eoaitc=verz=1 arene EN, AT wena, tie 2k KR WOT Xx Geb endnc=oorz=t oa. Tita 2 ee WT oars OER gee ee ee A waa Hk am 2 ‘Bape EH. AT (Ger He, tin @ eee WOT © Ce Nene nc =oercy=0 Corre oe-¢ Ss Poe Nemue=oercr <0 Gane EA Ee eee eee cena ea “ae BO Ct crane ooroy ara OE. HE (DEF) = LY, cia ges eee eee Ce ensinc=oorcy=1 TE Pew 7X = 6 End ior Sra ie ae 7 CU Dn eS Ot IN 6 nae = = as R55 TES aaa ie ian 0, ames eesasee esses emer ceteeeecaaiaaaaanaaaaaaliaessss1212 Seeeeeeeeeeemeneeee ‘aa, AT 58-1 een 3820 —n ie io Operation zt z TE = 1 (Ertl ert) yt ~ am TE (Dsl rot st 4-200