Designing Multi-Stage Logic

Dinesh Sharma
Microelectronics group
EE Department, IIT Bombay
August 29, 2017

We have seen how to design single stage logic in different design styles. However, typ-
ical designs need multi-stage combinational logic. We shall now discuss the considerations
underlying the design of multi-stage logic.

1 Stage Delay and Sizing

We have earlier derived expressions of the type
KτL V2 dV
Z
=
CL V1 f (V )

where τL is the time taken to charge/discharge the load capacitor CL from V1 to V2 and K is
the conductance factor given by µCox W
L
.

The right hand side of this equation is a definite integral. It will evaluate to some constant
depending on the voltages defining the ’High’ and ‘Low’ logic levels, turn on voltages, drain
saturation voltage etc. In digital design, we shall keep the channel length at its minimum
value, so L is a constant. Let us initially ignore the parasitic capacitances. We can see that
W τL CL
= Constant so τL ∝
CL W
This tells us that the delay associated with a gate charging a load capacitor scales directly
with CL and inversely with W , the width of the charging/discharging transistor.

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2 Tapered Buffer
As an example of multi-stage logic, let us take the case when a large capacitor is to be driven
by a CMOS circuit. A minimum sized inverter will take too long to charge this capacitor.
Therefore, we would like to scale up an inverter (multiply all transistor width by a scale
factor) in order to drive it. However, the input capacitance of this scaled up inverter may be
too large for a minimum sized inverter to drive. Therefore, we need a medium sized inverter
to drive the large final inverter. We keep adding inverters, till the first inverter in the chain
is small enough to be driven by standard CMOS logic. This kind of buffering is referred to
as a tapered buffer.
Tapered buffer
s1 s2 si sn-1 sn
CL

How do we decide the number of inverters to include in this chain? And what should be the
scale factors for each successive stage to minimize the total delay?

Let the i’th inverter in the chain be scaled up by a factor si compared to a minimum sized
inverter. Let the delay of a minimum sized inverter driving another minimum sized inverter
be τ . Then the i’th inverter provides charging currents which are si times the minimum sized
inverter. However, the load it sees is si+1 times the input capacitance of a minimum inverter.
Therefore the delay associated with the i’th stage is si+1 si
τ . The total delay of the inverter
chain is given by
n n
X si+1 X si+1
dtotal = τ =τ
1 si 1 si
In order to minimize the total delay, we should put the partial derivative with respect to each
of the si equal to zero. Therefore,
!
d s2 si si+1
τ +···+ + +··· = 0
dsi s1 si−1 si

Only two terms in the sum contain si . The derivative of all the rest of the terms is 0.
Therefore,
1 si+1 si si+1
− 2 =0 Which gives: =
si−1 si si−1 si
This means that the stage ratio, which is the factor by which an inverter is larger than the
previous one, is the same for all stages.

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 Let the stage ratio for the tapered buffer be ρ. The delay contributed by the i’th stage is
si+1
si
τ= ρτ . The total delay of n stages is then nρτ . The first stage is a unit inverter. Each
subsequent stage has a drive capability which is ρ times the drive capability of the previous
stage. Since the drive capability is being stepped up by ρ in n stages, we should have
1/n
CL CL

n
ρ = so ρ =
Cin Cin
We define the ratio H ≡ CL /Cin .

ln H
ρn = H So n ln ρ = ln H and therefore, n=
ln ρ
The total delay is then given by
ln H ρ
dtotal = nρτ = ρτ = τ ln H
ln ρ ln ρ
To minimize the total delay, we set its derivative with respect to ρ to 0.
!
1 ρ 1
0 = τ ln H −
ln ρ (ln ρ)2 ρ

This gives
ln ρ − 1
=0 or ln ρ = 1 So ρ=e
(ln ρ)2
Correspondingly, the number of stages is given by
ln H CL
n= = ln
ln ρ Cin
Thus we have the result that the optimum stage ratio for a tapered buffer is e, while the
optimum number of stages in the buffer is given by ln(Cout /Cin ).

These results were computed for a situation where capacitors were driven only by invert-
ers. Also, self loading due to transistors in the gate was ignored. Let us see what are the
consequences of removing these restrictions.

First, Let us see what happens if we replace inverters in the tapered buffer with static
CMOS logic gates.

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3 Using Logic Gates Other Than Inverters
We can scale transistor sizes in a gate to take care of
1. Difference in mobility of PMOS and NMOS. For example, we may scale the width of
PMOS transistors to be double that of NMOS transistors in the same configuration.

2. If there are n series connected transistors, their widths should be scaled up by n. This
makes the output drive of the logic gate equivalent to an unscaled inverter.
VDD VDD VDD
In1 In2 In2
2/1 2/1 2/1 4/1
In Out Out In1
4/1
Out
2/1
1/1
1/1 1/1
2/1

Inverter NAND NOR

However, this has an an impact on the capacitive loading placed on the previous stage. As
we can see from the figure, while an inverter scaled as given above places a load of 3 units
on the previous gate, a NAND gate with the same output drive loads the previous stage with
a capacitance of 4 units and a NOR gate loads the previous stage with a capacitance of 5 units.

Thus we must account for a loading factor for different gate types when optimizing multi-
stage logic. The ratio of 4/3 for a NAND gate and of 5/3 for a NOR gate is independent
of eventual scaling for drive capability. A NAND gate scaled to provide the same drive as a
scaled up inverter will also present a load which is 4/3 times higher on the previous stage.
The same can be said for the NOR gate or in fact, for any other CMOS gate.

This correction factor of 4/3 for NAND or 5/3 for a NOR gate is called the logical effort
of this gate time. This factor should be multiplied with the scale factor of this gate (which is
given by the ratio of output to input capacitance).

4 Considering the Effects of Self-Loading

If we consider the effects of self-loading, the logic has to drive some additional capacitance
coming from the drain capacitance and Miller capacitance associated with the driver transis-
tor. This additional capacitance is proportional to W . Thus,

CL = Cext + W Cp

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Where Cp is the parasitic capacitance per unit width of driver transistors. Therefore the delay
of the stage is
CL Cext + W Cp Cext
τL ∝ = Which gives τL ∝ + Cp
W W W
Thus the parasitic delay associated with self-loading is scale independent.

These refinements to the considerations used while designing an inverter chain are encap-
sulated in the idea of “Logical Effort”.