A Precise Current Subtractor Design

Chun Wei Lin*, Yu Huan Wu, Sheng Feng Lin

Department of Electronic Engineering,
National Yunlin University of Science & Technology, Yunlin 64002, Taiwan
linwei@yuntech.edu.tw

Abstract. In this work, we present a continuous time subtractor exercising precise current subtraction in
quite a wide operation range. Through utilizing balanced input stages with its feedback loop, we enhance the
stability of operation point of circuit and reduce mismatching DC error as well. In addition, cascode and
shunt feedback structure of output and input stage respectively enable the expected property of high output
resistance and low input resistance which benefits the accuracy of subtraction. With TSMC 0.35μm CMOS
technology, the proposed subtractor demonstrates very good performance that average subtraction error is
merely 0.00155% within the operation range from 1μA to 200μA. Furthermore, with 17Ω and 62MΩ
input and output resistor respectively, the results show the practicability of using proposed design as building
block of current mode application.
Keywords: subtractor, current subtraction, mismatching DC error, cascode, shunt feedback.

1. Introduction
Over past few years, current mode signal processing circuits have been focused considerable attention
because of its superior driving and noise rejection capability. However, due to difficulty on realizing accurate
current operation, most of circuits were operated in voltage mode. In many analogue systems and signal
processing applications, current mode circuits are considered as alternative of improving performance of
systems. According to prior literatures [1-5], several structures of current subtraction hade been proposed to
deal with requisite operation. Nevertheless, the detail discussion on performance of current subtraction is still
absent. The fundamental concept of current subtraction could be expressed in Fig. 1 [1]. Under the same
aspect ratio and well controlled gate voltage, the output current is ideally equal to subtraction of two input
currents, i.e. I out ≅ I in 2 − I in1 . If we take account of channel length modulation, the difference of drain
voltage on current mirror results in an error term, ε = λ p (VDS 3 − VDS 4 ) − λn (VDS1 − VDS 2 ) . In addition, input
currents can not be transferred into circuit effectively and equally because the input impedance of two input
nodes are different [6-7].
VDD

M3 M4
I in1
I out
N out
M1 M2
I in 2
GND
Fig. 1: Fundamental concept of current subtraction.

To deal with error terms of current subtraction, a current subtractor with balanced input stages was
proposed for the application of nonlinear switched-current circuit [2]. With balanced low input impedance,
the input currents are transferred into circuit equally which effectively reduce subtraction error. However, the
mismatching drain-source voltage of current mirror originated from channel length modulation is still
evident that degenerates the accuracy of subtraction [8]. If the subtraction error is out of tolerance of
application, the faulty occurrence may affect the performance and bring the system into collapse the worst.
We thus require a precise current subtractor to enhance the reliability of its application.
The remainder of the paper is organized as follows. Section 2 describes the principle and architecture of
proposed current subtractor. The detailed techniques of accuracy improvement are also stated in this section.
The simulation results are then reported in section 3 and finally summarize the conclusion in section 4.

2. The Proposed Current Subtractor

As mentioned above, the fundamental concept of current subtraction could be expressed in Fig. 1. The
critical factor to accomplish precise subtraction is straight current duplication from elements M1 and M3 to
M2 and M4. That is, the voltage value of node N out must be almost invariable and the channel length
modulation effect is consequently minimized. Nevertheless, the voltage on node N out is highly relative to the
input current. In other words, the subtraction error is not fixed or within certain limits but varies with input
current. The practicability of current subtraction is therefore restricted since the subtraction error may
unacceptable under the situation of larger input current.
To implement precise current subtraction, we propose a novel current subtractor as shown in Fig. 2. The
key factor to obtain precise subtraction is accurate current duplication [9-12] composed of 4 current mirrors.
The input stages, M 1 ~ M 4 and M 5 ~ M 8 , are equivalent which result in balanced input impedance. The
flipped voltage follower consists of M 5 , M 7 and I BIAS further reduces the input impedance expressing as:

1
Rin =
g m5 g m7 ro7
,where g mi is transconductance of M i and ro7 is output resistor of M 7 .

In the same way, the voltage follower consists of M 2 , M 3 and I BIAS similarly reduces the input impedance
which effectively transfers input current into subtraction circuit. Moreover, the current on M 5 and M 6 may
still different if we consider about the channel length modulation effect. The voltage difference across drain
of these two elements causes inaccuracy of current duplication. In order to reduce this effect, a high gain
operational amplifier op2 with M 8 are inserted to be a follower between drain of M 5 and M 6 . This
feedback loop clips the drain voltage on M 5 to M 6 and effectively reduces the channel length modulation.
Another merit, the compliance voltage of this design is only VDS .saturation which almost the minimum
required voltage for the operation of current mirror. Similarly, the feedback loops consist of op1 , M 4 , op3
and M 10 do likewise and result in accurate subtraction at node N sub expressing as:
I sub = I in 2 + I BIAS − ( I in1 + I BIAS ) = I in 2 − I in1

M 10
M9
I out
I BIAS I BIAS
I sub op3 M 13
N sub
VB 2 VB 1 op5
M4 op1 M3 M7 op2 M8

I in2 I in1 op4 VB 3

M1 M2 M5 M6 M11 M 12

Fig. 2: The proposed current subtractor.

 The current which flows out of node N sub is ideally equal to subtraction of two inputs current. However,
if we take account of loading effect at node N sub , the elements connecting with this node may fall into
wrong operation region and raise the error of current subtraction. The elements M 1 , M 6 , M 9 and M 10 may
operate in triode region due to overly voltage variation caused by loading effect. Moreover, undesired
periodic ripple of input current also may drive these elements into triode region because quite large
impedance at node N sub is sufficient to incur overly voltage variation. For this reason, we have to reduce the
voltage variation at node N sub . If we represent the impedance of this node as:
ΔVsub
Rsub =
ΔI sub
The voltage variation at this node can be reduced indirectly through decreasing its impedance. We
accordingly introduce a active-input regulated-cascode current mirror which composed of M 11 ~ M 13 , op4
and op5 as output stage. This structure combines the active input current mirror and regulated cascode
current mirror [11][13-14] which maintains a constant voltage at node N sub and hence lowering its
impedance and minimizing loading effects on previous stages. In addition, the drain voltage of M 12 is
clipped to a proper reference bias VB3 and the output impedance of whole circuit is increased which can be
expressed as:
Rout = A ⋅ ro12 ⋅ g m13 ⋅ ro13

The proposed current subtractor circuit provides balanced low input impedance and high output
impedance which effectively transfers input current into circuit and delivers lossless current to loading. The
subtraction circuitry consists of four current mirrors further reduces DC mismatching error and accomplishes
extreme precise current subtraction. These characteristics are especially benefit to the stability and reliability
of applications on current signal processing.

3. Experiment Result
In this section, we demonstrate the performance of proposed circuit showing in Fig. 2 by implementing
the circuit through TSMC 0.35 μm CMOS process. The layout of implemented chip is shown in Fig. 3 which
its core size is 600 × 460 μm 2 . The relative results are shown in Fig. 4 to Fig. 7 which reports the subtraction
error, input impedance, output impedance and propagation delay time. Within the difference of input current
from 1μA to 200μA , the subtraction error shown in Fig. 4 is under controlled with its average error is about
0.00155%. This result shows the accuracy of proposed current subtractor. Within the range of input current
from 1μA to 200 μA , the input impedance reported in Fig. 5 is merely 5Ω for minimum and 17Ω for
maximum. It can be seen that the feedback loop of flipped voltage follower structure mentioned above
certainly reduces the input impedance greatly. The output impedance is then reported in Fig. 6. Similarly,
within the same range of input difference, the output impedance is over 62 MΩ which guarantees the
efficiency of current delivery from subtractor to loading. Finally, Fig. 7 shows the delay time of the circuit is
under 4.2ns over the range while feeding a square input signal with its amplitude is from ±10 μA to ±90 μA .
The reported results demonstrate that the proposed design provides accurate current operation which can be
applied to perform precise subtraction between two terminals with varied currents.

Fig. 3: The layout of proposed current subtractor.

 1.9

Subtraction Error (10-3 %)

1.8

1.7

1.6

1.5

1.4

1.3
1 21 41 61 81 101 121 141 161 181
ΔI ( μA)

Fig. 4: The subtraction error with respect to difference of input current.

20

15
Rin(Ω)

10

0
1 21 41 61 81 101 121 141 161 181
Input Current ( μA)

Fig. 5: The input impedance with respect to input current.

200
180
160
Rout(MΩ)

140
120
100
80
60
40
20
0
1 21 41 61 81 101 121 141 161 181

ΔI ( μA)

Fig. 6: The output impedance with respect to difference of input current.

Delay Time (ns)

4.2

4.15

4.1

4.05

4
20 40 60 80 100 120 140 160 180

ΔI ( μA)

Fig. 7: The delay time with respect to difference of input current.

4. Conclusion
In this paper, we have proposed a precise current subtractor. Through utilizing four current mirrors with
specific feedback structure, the DC mismatching error of current subtraction and input impedance reduced.
Moreover, the output impedance also increased by inserting the developed output stage. To evaluate the
performance of proposed circuit, we implement the circuit and analyze the required parameters including
subtraction error, input impedance, output impedance and delay time over a wide operation range. The
results show the precision of proposed current subtraction circuit and the practicability of applying to current
signal processing system.

Acknowledgements
The authors would like to thank National Chip Implementation Center (CIC) for technical support and
chip fabrication.
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