Dual Latero Log Theory

SECTION 1
GENERAL INFORMATION
1.1 INTRODUCTION
This technical manual provides theory of operation and maintenance for the Dual Laterolog - MSFL
Tool (DLLT-B). Study the manual closely to develop a thorough understanding of the equipment
before operating or servicing for the first time. Observe all precautionary notes to minimize the risk
of either personal injury or equipment damage.
Tabbed contents sheets physically divide the manual into six sections.
• Section 1, General Information, discusses the scope and arrangement of the manual, describes
the tool and explains its purpose, and lists equipment specifications.
• Section 2, Theory of Operation, presents the principles of operation of the DLLT-B. It also
includes a functional description of the hardware accompanied by block diagrams and detailed
circuit descriptions.
• Section 3, Disassembly/Assembly, contains step-by-step disassembly and assembly procedures

for the DLLT-B. A list of special tools and equipment required to disassemble and assemble
the DLLT-B is also provided.
• Section 4, Calibration, contains theory of calibration and a list of calibration equipment with
applicable set-up and verification.
• Section 5, Troubleshooting, contains a series of circuit checks complete with corresponding

values (voltage, resistance, etc.). These checks are provided to help isolate
electrical/electronic faults to a repairable level. A list of test equipment along with
appropriate set-up also is provided.
1-1 (Rev. 01/95)

• Section 6, Reference Material, contains material which may be helpful during operation,
maintenance, and troubleshooting of the Dual Laterolog - MSFL Tool. A Reader's Comment
sheet on which you can comment about errors or omissions in the manual is also included.
1.2 EQUIPMENT DESCRIPTION
The DLLT-B (Exhibit 1-1) is a subsurface electric logging tool that provides signals which are
processed to produce four logs: three resistivity logs and a caliper log. The resistivity measurements
are a deep investigation laterolog curve, a shallow investigation laterolog curve, and a micro-
spherically focused log (Rxo) curve.
The signals which the DLLT-B inputs to the telemetry system are voltages representing seven analog
parameters:
• Deep survey current (I0d)

• Deep survey voltage (V0d)
• Shallow survey current (I0s)
• Shallow survey voltage (V0s)
• MSFL survey current (IA)
• MSFL survey voltage (VE)
• Caliper potentiometer voltage (CALP)
The deep and shallow laterolog logs together with the MSFL log provide an indication of true
formation resistivity (Rt). The three logs can be used to determine resistivity profiles around the
borehole, resulting in more accurate determination of Rt when appreciable invasion of drilling-mud
filtrate in the formation is encountered.
The MSFL curve is a measurement of the resistivity of the flushed zone (Rxo), the zone adjacent to the
wellbore, in which drilling-mud filtrate has displaced formation fluids. The deep and shallow apparent
resistivities (LLS and LLD), together with the MSFL measurement of Rxo, are sufficient to determine
the true formation resistivity (Rt) and the depth of invasion. Depth of invasion is obtained using the
invasion correction chart (see Subsection 6.5). Together with the mud-filtrate resistivity, the Rxo
measurement provides an indication of the formation factor and an indication of porosity, through use
of the Archie equation.
(Rev. 01/95) 1-2

Used in conjunction, the three resistivity curves (deep, shallow and Rxo) can indicate the presence of
movable hydrocarbons in the formation. In a water zone, where the resistivity of the mud filtrate is
nearly equal to the resistivity of the formation water, the curves of the deep laterolog, shallow
laterolog, and MSFL are nearly the same. In an oil zone under similar conditions, the MSFL log still
measures resistivity of the zone containing mud filtrate, while the deep and shallow laterolog
investigations are affected by the higher resistivity of the undisturbed oil bearing zone. Delineation
between oil and water zones remains readily apparent so long as the resistivity of the mud filtrate is
no more than three or four times the resistivity of the formation water.
The borehole diameter measurement provided by the caliper survey is used to make borehole effect
corrections for the deep and shallow laterolog curves. The caliper curve is also useful for calculating
cement volume requirements, determining the presence and thickness of mud cake, selecting packer
seats, etc.
1-3 (Rev. 01/95)

Exhibit 1-1: Tool Configuration, DLLT-B
(Rev. 01/95) 1-4

1.3 DLLT-B TOOLSTRING, 3.01134
A typical DLLT-B toolstring consists of the following functional components, listed in descending
order from the top of the string (See Exhibit 1-1):
• Cable Electrode Assembly, 3.6000 (Optional rigid cable electrode 3.10142)
• DSTU-B, 3.34839 (The subsurface telemetry unit is not a part of the DLLT-B, but it is
necessary for tool operation.)
• Optional tools. Any optional survey tools (usually the NGRT-A) that are run with the
DLLT-B are inserted into the toolstring here.
• Power and Telemetry Section Assembly, 3.01132
• Centralizer Equipment, 3.35130 and 3.07055
• Isolation Sub Assembly, 3.39020
• Measurement Section Assembly, 3.01133
• Electrode Sonde Assembly (Laterolog Sonde), 3.10510
• MSFL Mandrel Assembly, 3.33175
The DLLT-B also requires the use of the HLS standard surface reference electrode. This electrode is
commonly referred to as the "N" electrode or "the fish" and should be separate from the SP reference
electrode.
Although not part of the toolstring, the MSFL Calibrator (3.01209) and DLLT-A Dual Formation
Simulator Set (3.34254) are required for DLLT-B - MSFL calibration.
1-5 (Rev. 01/95)

1.3.1 Cable Electrode Assembly, 3.60000 (3.10142 Optional)
The Cable Electrode Assembly is a 90-foot long (the optional rigid cable electrode is 63.5-feet long)
disconnectable, sleeve-insulated assembly. It consists of a connector (called the "torpedo") which
couples the DLLT-B to the seven-conductor (7C) wireline cable running to the surface
instrumentation in the truck, an insulated length of 7C cable containing two electrodes, and a bell
housing that connects it to the DSTU. One of the electrodes serves as the remote current return
electrode for the deep laterolog. The other electrode serves as the SP-survey electrode, if that option
is run.
The Cable Electrode Assembly connects the logging cable mechanically and electrically to the
downhole toolstring consisting of the DSTU, any optional tools, and the DLLT-B at the bottom of
the string. More important, the Cable Electrode Assembly provides sufficient insulation between the
current return electrode and the Laterolog Sonde to minimize distortion of the required current flow
patterns (out in the formation) for the deep laterolog investigation.
The cable electrode bell housing contains a passive notch filter to suppress the shallow frequency
(1050 Hz) component of the DITS telemetry.
The Rigid Cable Electrode (3.10142) is available as an option.
1.3.2 Power and Telemetry Section Assembly, 3.01132
The Power and Telemetry Section Assembly consists of the dc-power supply package, the Remote
Telemetry Unit, the RTU interface (RTU I/F), and the mandrel arms open/close controller. The top
of the Power and Telemetry Section Assembly connects to the bottom of the DSTU. The bottom of
the Power and Telemetry Section Assembly connects to the Isolation Sub.
(Rev. 01/95) 1-6

Power Supply
The power supply package, located in the upper two thirds of the Power and Telemetry Section
Assembly, provides the following voltage supplies:
• Dual 15-Vdc regulated supplies
• +5-Vdc regulated supply
• +40-Vdc unregulated relay supply
Remote Telemetry Unit (RTU)
The Remote Telemetry Unit (RTU) is a standard two-board set: the RTU Control board (3.30920)
and RTU Data board (3.30921). These boards, together with the RTU Interface (RTU I/F), serve as
the digital data communication link between the DSTU and the DLLT-B. The RTU receives
operational commands from the DSTU which place the DLLT-B in its various modes of operation,
and it sends digitized telemetry data up to the DSTU.
RTU Interface
The RTU I/F consists of two circuit board assemblies: the RTU Analog I/F board (3.29786) and RTU
Logic I/F board (3.30477). These boards digitize the measured signal data and pass them to the
RTU. The RTU I/F also passes commands from the logging system to the tool switch position
circuits.
Mandrel Arms Controller
The mandrel arms controller extends (opens) and retracts (closes) the arms on the MSFL Mandrel. If
instrument power is lost, the mandrel arms will retract upon application of 400-Hz power at the
surface.
1-7 (Rev. 01/95)

1.3.3 Isolation Sub Assembly, 3.39020
The Isolation Sub Assembly is installed between the Power and Telemetry Section Assembly and the
Measurement Section Assembly to break electrical continuity between the electronics housings. The
sub has 37-pin connectors at the top and bottom and is wired one-to-one.
1.3.4 Measurement Section Assembly, 3.01133
The Measurement Section Assembly contains the majority of the circuitry to perform the LLD, LLS
and MSFL surveys. The top of this section connects to the bottom of the Isolation Subassembly.
The bottom connects to the top of the Electrode Sonde Assembly (laterolog sonde).
1.3.5 Electrode Sonde Assembly, 3.10510
The Electrode Sonde Assembly (laterolog sonde) consists of a Crossover Sub Assembly (3.39113),
the deep and shallow electrode array, the deep and shallow preamplifiers, and the bellows assemblies.
The laterolog sonde consists of 13 electrodes (Survey, Guard, and Monitor) separated by rubber
insulating material. Table 1-1 lists the 13 electrodes and their functions.
(Rev. 01/95) 1-8

Table 1-1: Laterolog Electrode Array
Electrode Function
A0 Survey-current emitting electrode for both deep and shallow investigations
A3+, A3- Guard electrodes for both deep and shallow investigations
A4+, A4- Guard electrodes for deep investigation and current return electrodes for the shallow
investigation
M1+, M1- Monitor electrodes for both the deep and shallow investigations
M2+, M2- Monitor electrodes for shallow investigation and formation voltage
M3+, M3- Monitor electrodes for deep investigation
A*+, A*- Monitor electrodes for deep investigation
1.3.6 MSFL Mandrel Assembly, 3.33175
The MSFL Mandrel Assembly consists of an upper pressure-equalized section and a lower section
with two retractable arms. The upper section contains the piston-type pressure equalization
mechanism, the arm actuating motor, the caliper potentiometer, and the ball-screw actuator. Pads are
mounted on the arms of the lower section. One of the pads is the MSFL electrode array (5 concentric
rings). Table 1-2 lists the MSFL electrodes. The other pad is a wear shoe. The top of the mandrel
connects to the laterolog sonde. The bottom of the mandrel is the bottom of the tool string.
1.3.7 Centralizer Equipment
Centralization equipment for the DLLT-B toolstring consists of a slip-over centralizer (3.35130) and
a 8-fin rubber standoff (3.07055). The slip-over centralizer is normally installed on the Power and
Telemetry Section above the isolation joint. The 8-fin rubber standoffs are usually installed between
the A4 and A* electrodes on the sonde. A rubber standoff may also be installed in place of the
slip-over centralizer when restrictive borehole conditions are present. The standoffs can be trimmed
to fit various borehole sizes.
1-9 (Rev. 01/95)

Table 1-2: MSFL Pad Array
Electrode Function
A0 Survey-current emitting electrode for the MSFL
M0 Voltage monitor electrode
A1 Focusing electrode
M1 Monitor electrode
M2 Monitor electrode
1.3.8 MSFL Calibrator Box, 3.01209
The MSFL Calibrator Box is used to perform shop calibrations on the MSFL circuitry. The calibrator
connections are made to the pad rings and the mandrel housing with a special contact fixture that is
included with the calibrator box. A switch is used to select from a network of resistors, which
simulate electrical loading of the MSFL pad, corresponding to various resistivities.
1.3.9 Dual Laterolog Formation Simulator Set, 3.34254
The DLLT-A Formation Simulator set is also used for DLLT-B. It consists of five networks that are
used to implement shop calibration of the Dual Laterolog measurements. Each resistor network
simulates a 0.1 ohmmeter (ohm-m), 8-inch diameter borehole resistivity, and a particular formation
resistivity (1, 10, 100, 1,000, or 10,000 ohmmeters). Each resistor network electrically simulates the
corresponding borehole-formation impedance between all electrode pairs.
1.4 SPECIFICATIONS
Please follow this link for the current Tool Technical Specifications data:
http://halworld.halnet.com/hes/hesps/hespslog/hespslog_documents/hespslog_documents_content/hespslog_
tts_dllt_b.pdf.
(Rev. 01/95) 1-10

SECTION 2
THEORY OF OPERATION
2.1 PRINCIPLES OF OPERATION
2.1.1 Nature of the Measurements
Most formations logged for oil and gas are made up of rocks which, when dry, do not conduct electric currents. This
physical property of the formation which impedes (resists) the flow of current is called resistivity. It is the inverse of
conductivity, the physical property of the formation which is a measure of its ability to conduct current. Current flows
through a formation which contains interstitial water (water in the pore spaces) that has been made conductive by salts
in solution.
A laterolog tool investigates formation resistivity by directly measuring the effects of currents focused into the
formation surrounding the borehole. Exhibit 2-1 shows a typical deep laterolog electrode array. Currents flowing out
of electrodes A0, A3+, A3-, A4+, and A4- cause a potential difference (the survey voltage) between the electrode array
and a return electrode (B). The survey voltage (termed V0) is measured by a voltage measuring circuit placed between
a surface voltage reference electrode (N) and a downhole monitor electrode (M2-) on the sonde. The output of this
voltage measuring circuit is called V0. The survey current (termed I0) is sent through the formation via source
electrode A0 and is measured by a current measuring circuit. The apparent resistivity of the formation is calculated by
dividing V0 by I0 and then multiplying by a tool constant (a number mathematically derived from the geometry of the
electrode array). The result is the apparent formation resistivity indicated by
2-1 (Rev. 01/95)

the tool, which yields the true formation resistivity when corrected for invasion and non-standard borehole size, and
when borehole resistivities are small. The equation for apparent resistivity is:
ρ = K (V0/I0)
where:
ρ= Formation resistivity
K= Tool constant
V0= A measure of the survey voltage
I0= A measure of the survey current
The process is complicated by the presence of the borehole in the formation. The current from the source electrode is
conducted by the drilling fluid into the formation and back to return electrodes elsewhere. To minimize the influence
of the highly conductive drilling fluid within the borehole on the measured formation resistivity, guard electrodes focus
the path of the survey current into the formation.
(Rev. 01/95) 2-2

Exhibit 2-1: Principle of Dynamic Focusing
2.1.2 Dynamic Focusing
Exhibit 2-1 illustrates how the laterolog electrode array prevents the deep (LLD) survey current from following the
path of least resistance up and/or down the borehole fluid, by focusing this current into the formation.
• An ac voltage (VA0) applied across the central electrode (A0) and a remote current return electrode (B) causes
survey current I0 to flow through the formation toward the return electrode.
• Similarly, an ac voltage VA4+ is applied between the upper focusing electrode (A4+) and the remote current
return electrode (B).
• Finally, an ac voltage (VA4-) is applied between the lower focusing electrode (A4-) and the remote current
return electrode (B).
2-3 (Rev. 01/95)

The three voltages at A0, A4+, and A4- are applied in phase and have approximately the same magnitude. Since the
voltages are in phase, the focusing currents repel the survey current from the A0 electrode, forcing it to flow in a
relatively thin horizontal layer (approximately 2-feet thick) at right angles to the borehole before it begins to flow
toward the remote current-return electrode (B).
Electrodes A3+ and A3- are also used to focus current into the formation. A vernier voltage is applied to A3+ with
respect to A4+, keeping these two electrodes at approximately the same potential (the vernier voltage is small with
respect to the voltage on A4+ and A3+ with respect to B). Similarly, a small vernier voltage is applied to A3- with
respect to A4-, keeping these two electrodes at the same potential.
To keep electrodes A3+, A3-, A4+, and A4- at the correct potentials (those potentials which keep I0 focused as a relatively
thin horizontal layer) as the tool moves upward through the successive formation beds during logging, sets of monitor
electrodes are used, positioned as shown in Exhibit 2-1. If a potential difference is sensed across a set of monitor
electrodes (M1/M3 or A4/A*), it indicates that current is straying up or down the borehole. The potential of the guard
electrodes is increased or decreased to maintain the focused path of survey current I0 into the formation, maintaining
essentially a zero voltage drop (or gradient) across each of the four pairs of monitor electrodes. If I0 starts to flow up
toward A3+, the voltage at electrode M1+ becomes larger than the voltage at electrode M3+. In this case, the A*
controller increases the voltage applied to A3+ and A4+. These increased potentials tend to push the survey current
down, restoring to zero the potential difference at the M1+/M3+ pair.
If I0 starts to flow down toward A3-, the voltage at electrode M3- becomes smaller than the voltage at electrode M1-. In
this case, the A* Controller increases the potential at A4- and A3- until zero gradient is restored at the M1-/M3- pairs.
If a potential difference is sensed at the A*/A4+ electrode pair, the A3 Controller adjusts the relative potential difference
between A4+ and A3+. Any necessary adjustment of the A4+ and A3+ potential, to keep M1+/M3+ at zero, is
simultaneously performed by the A* Controller.
(Rev. 01/95) 2-4

Similarly, if a potential difference is sensed at the A*- and A4- electrode pair, the A3 Controller adjusts the relative
potential difference between the A4-/A3- electrodes. Simultaneous adjustment, if necessary, is made by the A*
Controller to regulate the M1-/M3- potential difference to zero.
The survey voltage, V0, between a downhole electrode (M2-) and a remote surface electrode (N) is measured to
calculate the resistivity. The voltage is not measured with respect to B because the potential at B, relative to N, is
influenced by the resistivity of the bed opposite B (e.g. Delaware Gradient effect), the proximity of casing, and the mud
resistivity.
The survey current (I0) from the current transformer is emitted from the A0 electrode and is measured by the I0
Amplifier.
2.1.3 DLLT-B Depths of Investigation
The DLLT-B performs resistivity measurements with three different depths of investigation into the formation. These
three resistivities are used to obtain true formation resistivity (Rt) and the invasion diameter (di). The three depths of
investigation are:
• Approximately 5 - 7 feet into the formation (deep laterolog investigation)
• Approximately 2 - 3 feet into the formation (shallow laterolog investigation)
• Flushed zone (Rxo), a few inches into the formation (MSFL investigation)
The deep (LLD) and shallow (LLS) investigations, are performed simultaneously, using common electrodes. The LLD
and LLS share some of their electrodes on a common sonde, but are electrically operated to minimize the effects of one
upon the other. The circuits of the deep investigation operate at a frequency of 131.25 Hz, while the circuits of the
shallow investigation operate at a frequency of 1050 Hz. Operating the electrodes at different frequencies allows
non-interacting measurements of the relatively deep and shallow resistivities. Harmonically related measurement
frequencies provide voltage or current measurement extraction at each separate frequency from a composite two-tone
waveform.
2-5 (Rev. 01/95)

The previous discussion (2.1.2) relates the operation of the LLD, and how dynamic focusing is accomplished to
regulate four focusing-electrode potentials at A3+, A3-, A4+, and A4-.
The shallow investigation functions similar to the deep, but uses two guard electrodes instead of four (see Exhibit 2-2).
The outermost deep guard electrodes (A4+/A4-) are utilized as close-spaced return electrodes for the shallow
investigation.
Exhibit 2-2: Shallow Laterolog Current Flow
(Rev. 01/95) 2-6

The potential at the two LLS guard electrodes A3+ and A3- are controlled by the A3 Controller so that the M1/M2
potential differences at 1050 Hz are regulated to zero. The LLS currents from A0 and the A3 electrodes return to the
A4 electrodes. Since the return electrodes are relatively close to the A0 electrode, less focusing distance into the
formation is achieved. The reduction in the guard electrode length for the LLS, as compared to LLD, produces a
shallower investigation.
The use of voltage monitoring electrodes (which do not emit current and separate current-emitting electrodes), in
combination with the precision feedback control, minimizes the adverse effects due to electro-chemical reaction at the
electrode surfaces. This electro-chemical reaction can deteriorate simpler guarding arrangements (e.g. M904 Dual
Guard). The shallow investigation is performed by moving the current return close to the guarded electrodes. This
arrangement retains borehole guarding to a greater degree than can be obtained with a shallow guard measurement
system where the degree of focusing alone is decreased to provide a shallow investigation means.
2.1.4 MSFL Investigation
The Micro-Spherically Focused Log (MSFL) investigation is made by pad-mounted current electrodes to achieve a
spherically focused survey current that is dynamically maintained (see Exhibit 2-3). The MSFL measurement involves
only the first few inches of the formation adjacent to the borehole (the flushed zone), in which drilling fluid has
displaced all formation fluids. The MSFL provides a measurement of the flushed zone resistivity (Rxo), with low
mudcake correction. The electrodes for the MSFL device are located on a pad-mounted array, which is in turn is
located on a powered caliper arm at the bottom of the tool.
The MSFL measurement electrode array consists of a survey current electrode (A0), a voltage monitor electrode (M0),
a current electrode A1), and two focus monitor electrodes M1 and M2). These electrodes are configured as five
concentric rectangular rings on the pad. When the flexible pad is pressed against the borehole wall (to minimize the
borehole affects on the resistivity measurement), the A0 electrode emits current directly into the formation, returning to
the mandrel body (current return) and to the A1) electrode. Only the survey current Is) is measured, although the
focusing current (If) is also emitted from the A0) electrode (returning to A1). Any potential difference between monitor
electrodes M1 and M2 is detected and adjusts the drive amplitude to the A1 electrode to correct for the error, thus
dynamically focusing the survey current around the monitor pair. The focusing monitors (M1 and M2) are located
outside the focusing ring (A1), between the A1 electrode and the current return (mandrel body). The measured voltage
between the M0 electrode and the M1/M2 transformer center tap are on surfaces of equal potential which approximated
hemispherical shape. This voltage measurement excludes the region immediately adjacent to the A0 electrode, thus
minimizing borehole fluid and mudcake influences on this resistivity measurement.
2-7 (Rev. 01/95)

Exhibit 2-3: Focusing, MSFL Investigation
(Rev. 01/95) 2-8

2.2 POWER AND TELEMETRY SECTION OVERVIEW (3.01132)
The Power and Telemetry (P&T) Section (Exhibit 2-4) of the DLLT-B provides low-voltage power to the
measurement section of the tool string. The P&T section also contains signal digitizing circuitry, an RTU, and a
400-Hz control circuit (for the MSFL Mandrel).
60-Hz instrument power from the service unit is applied to the toolstring on conductors 1, 2, 4, and 5 of the
7-conductor cable. The 60-Hz power is applied to conductor 1 with respect to 2 and conductor 4 with respect to
conductor 5. 400-Hz auxiliary power to run the MSFL Mandrel is applied to the tool by driving conductors 1 and 2
against conductors 4 and 5. Transformers T1, T2, and T3 provide low voltage 60-Hz power to the 5-Vdc and 15-Vdc
supplies in the P&T section. Transformer T3 has a center-tapped primary to couple the 400-Hz power from the cable
to the mandrel motor control circuitry (K1, K2, etc.). The 400 Hz over-voltage protection circuit consists of a
saturable reactor (L7), which limits the 400-Hz voltage amplitude present on the logging cable and tool conductors,
when the MSFL mandrel motor switches out of the circuit at the end of travel. The P&T section provides two
independent 15-Vdc supplies and a +5-Vdc supply for operation of the Measurement Section. An unregulated 40-Vdc
supply is used to energize all relays in the Power and Telemetry sections. Unregulated +15-Vdc energizes
Measurement section relays.
Communications between the BCU and the DLLT-B is accomplished with a standard RTU over a serial-data 1553
Bus. The tool order function of the RTU boards is disabled in the DLLT-B.
Analog data from the measurement section is digitized by the RTU Analog Interface. Digitized data is stored by the
RTU Logic Interface, which transmits data to the RTU upon request.
The RTU Logic Interface contains a control register, which stores the last word received by the DLLT-B from the
BCU. This data word is utilized by the DLLT-B to determine the desired mode of operation for the tool (LOG,
OPEN MANDREL, etc.)
Cable conductors 3 and 6 are coupled together in the P&T section through capacitors to form a V0 reference
conductor for the measurement section.
2-9 (Rev. 01/95)

Exhibit 2-4: Block Diagram, Power and Telemetry
(Rev. 01/95) 2-10

2.3 POWER SUPPLY BOARDS BLOCK DESCRIPTION
Power for the DLLT-B is provided by the 60-Hz instrument power. The power supply package,
located in the Power and Telemetry Section, provides the tool with four voltage supplies, as follows:
• Dual 15-Vdc regulated supplies (650 milliamperes)

• +5-Vdc regulated supply (250 milliamperes)
• +40-Vdc unregulated supply (110 milliamperes)
Exhibit 2-5 is the block diagram of the power supply. Except for the unregulated +40 Vdc supply, the
voltage supplies follow the standard design of transformer, rectifier/filter, regulator/filter. One of the
15-Vdc dual supplies is connected in common to the +5-Vdc and the +40-Vdc supplies. The other 15-
Vdc dual supply is independently grounded in the measurement section.
The two 15-Vdc supplies, used to power the laterolog and MSFL measurement circuitry, receive input
power from the secondary winding of transformer T1. Both the positive and negative supplies use the
same regulator structure, with the output of the negative regulator grounded to provide the -15-Vdc.
The +5-Vdc supply, used primarily for logic, receives its input from the secondary winding of
transformer T3. The +40-Vdc supply, used to energizing the K1 and K2 relays (located in the Power
and Telemetry Section 3.42081), receives its input power from a secondary of transformer T3.
2-11 (Rev. 01/95)

Exhibit 2-5: Block Diagram, DLLT-B Power Supplies
(Rev. 01/95) 2-12

2.4 POWER SUPPLY BOARDS CIRCUIT DESCRIPTIONS
The INSTRUMENT configuration supplies instrument power and the AUXILIARY configuration
supplies 400-Hz motor auxiliary power to operate the MSFL Mandrel motor. Instrument power to
transformers T1 and T2 (two R-1163's and an R-1184) appears on pins J1-13, 14, 16, 19 of the 19-pin
connector. J1-16 and J1-19 have 120 VRMS applied between them. An independent 120 VRMS
appears between J1-13 and J1-14. Auxiliary power appears between the pairs J1-13, 14 and J1-16, 19.
The power supply package in the Power and Telemetry Section (3.01132) provides six dc-voltage
supplies: two 15-Vdc regulated, 650-Ma supplies, a +5-Vdc regulated, 250-mA supply, and a +40-Vdc
unregulated, 110-mA supply.
2.4.1 +5-Vdc Rectifier/Filter Board (3.29710)

The +5-Vdc Rectifier/Filter board (3.29710) is used primarily for logic. Exhibit 2-6 is the schematic
for the +5-Vdc Rectifier/Filter board. It receives input power from a secondary winding of transformer
T3 (R-1164). A full-wave bridge, consisting of diodes CR1, CR2, CR3, and CR4, rectifies the ac
voltage. Inductor L3 (C-1137), capacitors C1, C2, C5, and resistor R2 form a choke-input filter to
smooth the rectified ac voltage from CR1-CR4. Voltage regulator Q5 uses the input dc voltage to
maintain a constant 5-Vdc output. Diode CR5 protects Q5 against reverse voltage. Resistor R1
discharges output filter capacitors C3 and C4 and establishes critical load current in the filter inductor.
Exhibit 2-6: Schematic, +5-Vdc Rectifier/Filter Board
2-13 (Rev. 01/95)

2.4.2 Dual ± 15-Vdc Rectifier/Filter Boards (3.29712)
The two 15-Vdc Rectifier/Filter boards power the laterolog instrument sections. Both the positive and
negative supplies utilize the same regulator structure. The output of the negative regulator is grounded
to obtain the -15 volts.
Exhibit 2-7 is the schematic for the 15-Vdc Rectifier/Filter board. The unregulated +15-Vdc circuitry
receives input power from a secondary winding of transformer T1. A full-wave bridge consisting of
diodes CR1, CR2, CR3, and CR4 rectifies the ac voltage. Choke L1 (C-1136) smoothes the rectified
voltage, and capacitors C1, C2, C3, and C4 provide filtering. Resistor R1 establishes critical load
current through the choke L1. The unregulated dc output is used as an input voltage source by the 15-
Vdc Regulator board. The circuitry for the unregulated -15-Vdc supply is identical except that the
output is grounded to obtain the -15-Vdc.
Exhibit 2-7: Schematic, +15-Vdc Rectifier/Filter Board
(Rev. 01/95) 2-14

2.4.3 ± 15-Vdc Regulator Boards (3.29733)
Operation of the two ± 15-Vdc Regulator boards are identical. Exhibit 2-8 is the schematic of the
+15-Vdc Regulator boards. Rectified and filtered dc is supplied to the source (terminal 6) of the
series-pass regulator Q1 (IFR 9130). Conduction of Q1 is controlled by increasing or decreasing the
gate voltage (terminal 1) with respect to the source (terminal 6). This gate/source voltage controlling
Q1 is determined by the current through R6, which is the collector current of transistor Q2
(2N2895A). A resistor/divider network (R10, R16, R12) divides the regulated output voltage.
Op-amp AR2 compares the divided voltage from the resistor/divider string to a precision reference
voltage established by zener diode VR4, diode CR2, and resistor R9. The output of the op-amp
adjusts the base current of transistor Q2 through resistor R7 to control the conduction of Q1 and
regulate its output voltage. Diodes CR4, CR6, and zener diode VR8 act as a voltage reference at
circuit startup. This reference voltage is zero. Capacitors C4 and C5 provide local filtering of both the
input and output of the regulator. Capacitors C8, C10, and resistor R18 provide closed loop
stabilization of the regulator while allowing fast response of the regulator to line or load changes.
Exhibit 2-8: Schematic, +15-Vdc Regulator Board
2-15 (Rev. 01/95)

2.4.4 +40-Vdc Unregulated Board (3.29714)
The Unregulated +40-Vdc board, shown schematically in Exhibit 2-9, receives input power from a
secondary of transformer T3. A full-wave bridge consisting of diodes CR1 through CR4 (1N 5811)
rectifies the input ac voltage. Resistors R1, R2, and capacitor C1 serve as a smoothing filter for the
+40-Vdc output.
Exhibit 2-9: Schematic, +40-Vdc Unregulated Board
(Rev. 01/95) 2-16

2.5 RTU/RTU I/F OVERVIEW
The Remote Telemetry Unit (RTU) and RTU Interface (RTU I/F) combination consists of four PC
boards located in the Power and Telemetry Section of the tool. These boards are:
• RTU Control Board (3.30920)
• RTU Data Board (3.30921)
• RTU Interface Analog Board (3.29786)
• RTU Interface Logic Board (3.30477)
These boards together serve as the digital communication link between the DSTU and the tool.
2-17 (Rev. 01/95)

2.6 REMOTE TELEMETRY UNIT (RTU)
2.6.1 Block Description
Exhibit 2-10 is a functional block diagram of the RTU. The RTU main functional blocks are:
• 1553 bus transformer and transceiver
• Manchester Encoder/Decoder integrated circuit
• Downlink logic
• Uplink logic
• Tool interface conversion and decoding logic:
- Tool address/command decode logic
- Tool bus control logic
- Serial-to-parallel conversion logic for receiving data from the DSTU via the 1553 bus
- Tool status port logic
- Parallel-to-serial conversion logic for transmitting data from the tool to the DSTU via
the 1553 bus
(Rev. 01/95) 2-18

Exhibit 2-10: Block Diagram, Remote Telemetry Unit
Information goes to and from the DLLT-B via the 1553 bus. Data is encoded as Manchester II
bi-phase, where a "logic one" is transmitted as a positive pulse followed by a negative pulse, and a
"logic zero" is transmitted as a negative pulse followed by a positive pulse. This method of encoding
provides either a positive or negative transition for each bit and facilitates the use of isolation
transformers for connection to the 1553 bus. Each encoded word consists of 20 bits (3 for sync, 16 for
data, and 1 for parity) transmitted at a rate of 217.6 kilobits-per-second. Exhibit 2-11 shows the
Manchester II encoding method.
2-19 (Rev. 01/95)

Exhibit 2-11: Manchester Encoding Method
Word Formats
The 1553 data bus uses three types of word formats: Command, Status, and Data (see Exhibit 2-12).
A command word from the DSTU consists of a positive-to-negative sync pulse (three bit times wide),
a T/R bit to indicate whether the RTU is to transmit or receive data, seven bits of remote terminal
address, three subaddress/mode bits, five bits to specify either the word count or the mode code, and a
parity bit. A status word sent back by the addressed RTU consists of a positive-to-negative sync pulse,
an error bit, the RTU address, a busy bit, two unused bits, an RTU order bit, four status bits, and a
parity bit. A data word either to or from an RTU consists of a negative-to-positive sync data pulse, 16
bits of data, and a parity bit.
(Rev. 01/95) 2-20

Exhibit 2-12: Word Formats
Tool Address and Command Functions
Each DITS tool has a unique remote terminal address. The remote terminal address of the DLLT-B is
04 HEX. Through communication with the RTU, the tool can be placed in any of four modes, report
its tool ID, or transmit tool data.
The tool ID function transmits the 16-bit tool ID word to the DSTU. The tool ID word is set by a
series of jumper wires on the RTU I/F logic board. The jumpers are selected so that each tool has a
unique tool ID. The 16-bit ID allows for 65,526 DLLT-B tools, each having a unique tool ID.
2-21 (Rev. 01/95)

The data field for the tool ID function is structured as follows:
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 0
CONFIGURATION REVISION SERIAL NUMBER

LEVEL
Bits 15 and 14 are used for tool configuration, bits 13, 12, and 11 for tool revision level, and bits 10
through 0 for the tool serial number.
Configuration of RTU Control and Data Boards
Although the RTU control and data boards are standard for all DITS compatible tools, the boards must
be configured for each tool with plug-in jumpers, a word-count PROM, and an address decoder
PROM. Specific configuration items for the boards in the DLLT-B are:
• U19 - PROM 3.34552, RTU Data board 3.30921

• U13 - PROM 3.42264, RTU Data board 3.30921
• R4 - 402 ohm resistor, RTU Control board 3.30920
• PROM Header jumpers (see Exhibit 2-13)
Exhibit 2-13: PROM Header Jumpers
(Rev. 01/95) 2-22

2.6.2 Circuit Description
For a description of the Remote Telemetry Unit (RTU) circuits, refer to the DSTU/RTU Maintenance
and Repair Manual (770.00259). Section 8, Reference Material lists the RTU PROMS used for
application in the DLLT-B.
2.7 RTU INTERFACE (RTU I/F)
The 15-channel RTU I/F used in the DLLT-B consists of an analog board and a logic board. The RTU
I/F Analog board (3.29786) receives differential analog inputs and processes them through a pair of
input multiplexers, a differential amplifier, two programmable gain stages, sample and hold, and a
12-bit Analog-to-Digital Converter (ADC). The RTU I/F Logic board (3.30477) controls the analog
input channel selected, the setting of the programmable gain stages, and the timing of sample/hold and
ADC. The logic board provides memory space for the collected data and communicates with the RTU
boards, receiving control words and transmitting ID information data when requested.
Data Organization
For each input channel selected the logic board sequences the analog board through the acquisition
cycle for a gain of 1, gain of 8, and gain of 64. The four bits selecting the gain comprise the address of
the RAM memory, so any given address in RAM will always hold data for the same input channel on
the same gain setting. Each input channel will always be sequenced through all three gain settings.
The number of input channels sampled and the sequence of these channels are controlled by two
factors. A map PROM on the logic board contains several possible input channel sample-sequence
configurations (maps). The particular map active at any given time is determined by the last control
word received from the RTU. The same map is followed when data is transmitted to the RTU.
2-23 (Rev. 01/95)

Operating Mode Peculiarity
The RTU I/F for the DLLT-B is designed to use only one of the two DITS system formats for
downloading operating mode commands. This interface uses the format in which the mode command
has a bit set to indicate that a 16-bit control word will follow. The operating mode is always set by a
16-bit control word. The other format, a 4-bit mode command, CANNOT be used with this tool. The
RTU handles control word buffering and initiates handshaking with the RTU I/F to load the control
word.
Power-Up Reset Sequence
The power-up reset sequence provides the tool with a preset operating mode. The acquisition
sequence also is initiated at the beginning as determined by the map selection present. The DLLT-B
preset is 00E1H (Shallow Cal) and is set by J3 on the RTU I/F Logic board (3.30477).
Receive Control Word Sequence
The RTU initiates handshaking to indicate that it has placed a data word on the bus. This word is used
as a control word by the DLLT-B.
Transmit ID Sequence
The ID is a 16-bit word requested through the RTU that is used to identify the tool attached. The ID
is set by J2 on the RTU I/F Logic board (3.30477).
Transmit Data Sequence
Data is normally requested in a block. The RTU I/F will send data in a sequence as determined by the
MAP in use in the MAP PROM, as selected by bits of the control word. After each data word is sent,
the RAM address is changed to the next data location for access according to the MAP.
(Rev. 01/95) 2-24

Data Control
Whether transmitting data or collecting data, the sequence of channels is controlled by the map PROM
U5, and the sequence of gain setting within each channel is controlled by the control PROM U2. The
control PROM also controls the timing of the functions on the RTU Analog board.
2.7.2 RTU I/F Analog Board Circuit Description
The RTU I/F Analog board performs all of the analog processing for the RTU I/F. The board consists
of an input multiplexer, a differential amplifier, two programmable gain amplifier stages, a sample and
hold amplifier, and an Analog-to-Digital Converter (ADC). (See drawing 3.29786, sheet 4 of 4.)
Input Multiplexer
The input multiplexer consists of 16-channel multiplexers U1 and U2. Analog data appearing at the
multiplexer input (IN1 through IN16) is passed to its output (OutA and OutB) upon application of a
specific channel's address at the address inputs (A0 through A3). For example, the signal tied to IN2
will be passed to OutA and OutB when the binary address 0 0 0 1 is applied to A3, A2, A1, and A0,
respectively. Channel IN1 is permanently tied to ground, providing a ground reference used to obtain
RTU I/F offset readings. During logging, these readings are subtracted from each of the other channel
readings by the surface computer to compensate for any zero drift in the RTU I/F. Two input
multiplexers are used so that differential signals can be processed, single-ended signals can be
accounted for, and small variations in the ground potential of the measurement sections can be
compensated. Table 2-1 shows the channel assignments for the DLLT-B.
2-25 (Rev. 01/95)

Table 2-1: Channel Assignments, DLLT-B
MULTIPLEXER MULTIPLEXER ADDRESS

SIGNAL
CHANNEL
A3 A2 A1 A0
CALIPER IN2 0 0 0 1
MSFL VE IN3 0 0 1 0
MSFL IA IN4 0 0 1 1
V0 SHALLOW IN5 0 1 0 0
I0 SHALLOW IN6 0 1 0 1
V0 DEEP IN7 0 1 1 0
V0 DEEP IN8 0 1 1 1
GROUNDED IN1 0 0 0 0
Differential Amplifiers
Amplifiers AR1, AR2, and AR3 combined, comprise the differential amplifier used to convert the
incoming differential signal to a single-ended signal required by the ADC.
Programmable Gain Stages
Following the differential amplifier are two programmable gain stages, each stage having a selectable
gain of X1 or X8. With the two stages in series, selectable gains of X1, X8, and X64 are available.
The programmable amplifiers are identical, each having a gateable 8:1 attenuator followed by an X8
amplifier. The first stage is comprised of AR4, U3, R7, R8, and R9. With switch 6-7 of U3 closed and
switch 2-3 of U3 open, the stage has a gain of 8 since the input attenuator (R7, R8) is out of the circuit.
With switch 2-3 of U3 closed and switch 6-7 of U3 open, the input attenuator is connected to the
input of AR4, resulting in a gain of one for the stage. The second stage, consisting of AR5, U3, R12,
R13, and R14, functions in the same way as the first. The gain of each stage is controlled by logic
signals GAIN B0, GAIN B0/, GAIN B1, and GAIN B1/. GAIN B0 and GAIN B0/ control the first
stage, and GAIN B1 and GAIN B1/ the second stage. Since the two control signals to each stage
complement each other, only one switch in the stage is closed.
Table 2-2 shows the state of each switch in U3 and the resultant gain of the two stages as a function of
the four control signals.
(Rev. 01/95) 2-26

Table 2-2: State of Switches and Resultant Gain of U3
SIGNAL U3 SWITCHES
B1/ B1 B0/ B0 14-15 10-11 6-7 2-3 GAIN
1 0 1 0 Open Close Open Close 1
0 1 1 0 Close Open Open Close 8
0 1 0 1 Close Open Close Open 64
Sample and Hold Amplifier
Exhibit 2-14 is a simplified circuit diagram of the sample and hold (S/H) amplifier. The S/H amplifier
circuit is unique in that the signal to be digitized (VIN) is amplified by a factor of -0.763 (R18  R17),
and an offset of -3.75 volts [10 x (R18  R19)] is added to it. An input level of -1.000 volt to the S/H
amplifier results in an output of -2.297 volts. This configuration of the S/H amplifier allows the RTU
I/F to process positive signals with some positive offset and also signals that are slightly negative.
Mode selection of the S/H amplifier is controlled by the logic signal SAMPLE/. A logic LOW on this
line closes switch U4, which allows the S/H amplifier output to follow the input signal shown in the
following equation:
VOUT = -3.75 - (0.763 VIN)
With a logic level HIGH on the SAMPLE/ line, the output of the S/H amplifier maintains the level
appearing at its output just prior to SAMPLE/ going HIGH, and no longer follows the input signal.
The S/H amplifier is placed in the HOLD mode (SAMPLE/ = HIGH) just prior to an A/D conversion
and remains in the HOLD state until the conversion is completed.
2-27 (Rev. 01/95)

The ADC (U5) is a 12-bit converter configured for a 5-Vdc signal range. Conversion is initiated with
the signal CONVERT/ by pulsing it LOW. The conversion is completed 12 clock cycles after the time
CONVERT/ is pulsed LOW. An external clock is provided for the ADC so it can run synchronously
with the RTU I/F. The external clock, derived from the RTU I/F master clock, runs at a 200-kHz rate.
This clock rate allows for a conversion to be completed in 60 microseconds.
The RTU I/F Analog board has the capability of digitizing a maximum of 16 differential signals (one
permanently tied to ground) at three different sensitivities. For the DLLT-B, only eight of the input
channels are assigned. Table 3-3 lists the resulting signal ranges for the three gain ranges of the RTU
I/F Analog board.
Table 2-3: Signal Ranges and Resolutions, RTU I/F Analog Board
SIGNAL LIMITS (VOLTS)

GAIN Minimum Maximum RESOLUTION (VOLTS)
X1 -1.628 11.47 3.2 millivolts
X8 -0.205 1.433 400 microvolts
X64 -0.0256 0.179 50 microvolts
Exhibit 2-14: Schematic, Sample and Hold Amplifier
(Rev. 01/95) 2-28

2.7.3 RTU I/F Logic Board Circuit Description
The RTU I/F Logic board consists of seven major circuits:
• Clock generator
• Preset and receive
• Transmit Control
• Control/status registers
• Preset/ID registers
• Acquisition control
• Random access Memory (RAM)
Detailed descriptions of the above listed circuits are discussed first, followed immediately by their
respective timing diagrams. Refer to drawing 3.30477 during the circuit descriptions.
Clock Generator Circuit
Timing for all circuits on the two RTU I/F boards is generated by the clock generator circuit (Exhibit
2-15). The master clock for the clock generator is the 1-MHz clock oscillator U6. The output of U6
is tied to the clock input of binary counter U8, which is configured as a five state counter. Following
the fifth state, the counter returns to its zero state, controlled by the output of U9-6. Clock signals
CLK1 through CLK4 are generated by inverting the outputs of U8. The clock for the ADC
(ADCLOCK) is active only when SAMPLE/ is HIGH, indicating that the S/H amplifier is in the
HOLD mode and that a conversion will be initiated. Clock signal SHCLOCK is not used. Exhibit
2-16 shows the timing of the clock generator and summarizes the sequence of operation of the RTU
I/F Logic board.
2-29 (Rev. 01/95)

Exhibit 2-15: Schematic, Clock Generator
(Rev. 01/95) 2-30

Time
1 CONTROL PROM is enabled (MAP PROM Address Complete).
2 MAP PROM is enabled, completing the RAM address.
3 RAM address is latched; internal coding is enabled.
4 RAM enabled for Read or Write, depending on the write state.
5 RTU Buffers are clocked, if data is being read from RAM. New control states are latched; counters are
incremented if enabled. CONTROL PROM, MAP PROM and RAM are disabled.
Exhibit 2-16: Timing Diagram, RTU I/F Logic Board
2-31 (Rev. 01/95)

Preset and Receive Control Circuit
The preset and receive control circuit (Exhibit 2-17) controls the sequencing of power-up reset, and
the reception of a control word from the RTU. The power-up reset provides the tool with a preset
operating mode and thus prevent the tool from coming up in an undesirable mode. For the DLLT-B,
the preset control word is 00E1. This control word instructs the RTU I/F to use map 01, and places
the tool in the SHALLOW CAL mode.
Exhibit 2-17: Schematic, Preset and Receive Control
(Rev. 01/95) 2-32

Transmit Control Circuit
The transmit control circuit (Exhibit 2-18) initiates transmit data requests from the RTU. The data
requested is either the collected data from the RAM on the RTU I/F Analog board and the RTU I/F
status word, or the ID word of the RTU I/F. If the collected analog data and status word are
requested, the transmit control logic initiates a read cycle; otherwise, an ID cycle is initiated.
For the DLLT-B, a read cycle results in the transmission of the status word followed by 24 data words
corresponding to the digitized eight analog channels on the RTU I/F Analog board for a total of
twenty-five 16-bit words. The read cycle is initiated by the surface computer by transmitting mode
command 8419H to the RTU. An ID cycle is initiated by transmitting the mode command 84E9H.
Exhibit 2-18: Schematic, Transmit Control
2-33 (Rev. 01/95)

Control/Status Register Circuit
Exhibit 2-19 is the circuit diagram for the control register and the status register. The control register
stores the current operating mode of the tool. The register is initially loaded upon power-up with the
control word 00E1, which places the tool in the SHALLOW CAL mode and selects map 01 for the
RTU I/F. The four least significant bits (LSBs), CTRL0 through CTRL3, are used to select the map,
and bits CTRL4 through CTRL8 are used for relay control. The register is reloaded with a control
word when a mode command and associated data word (two-word command) are received by the
RTU. The preset and receive control logic loads the data word into the control register with the logic
signal RECEN. The data word is a binary-coded address that controls the DLLT-B mode selection by
addressing PROMS on the Relay Driver board and the Tool Switch Position board, which in turn
control various relays in the tool.
The status register monitors the operating status of the tool. The status register reflects the current
contents of the control register, since its inputs are tied to the outputs of the control register with
jumpers (J1). The control and status words for the DLLT-B are as follows:
MSB CTRL15/STAT15 = Not used

CTRL14/STAT14 = Not used
CTRL08/STAT08 =
CTRL07/STAT07 =
CTRL06/STAT06 = Address for relay driver PROM
CTRL05/STAT05 =
CTRL04/STAT04 =
CTRL03/STAT03 =
CTRL02/STAT02 = Map address (01 For DLLT-B)
CTRL01/STAT01 =
LSB CTRL00/STAT00 =
(Rev. 01/95) 2-34

Exhibit 2-19: Schematic, Control/Status Register
2-35 (Rev. 01/95)

Preset/ID Register Circuit
Exhibit 2-20 is the circuit diagram for the preset/ID registers circuit, which consists of U30 and U31
(preset register), and U32 and U33 (ID register).
The preset register stores the initial operating mode of the tool when the tool is powered up. The
power-up operating mode is selectable through jumper J3. The selected mode is subsequently loaded
into the control register (U26 and U27) when the tool is powered up with control signals PRESETEN/
and RECEN. The format of the preset word is the same as the format of the control word. The
content of the ID register is set (during manufacture) with a jumper (J2) to uniquely identify each tool
produced. Since each type of tool (Acoustic, Density, DSN, etc.) has a unique RTU address assigned
to it, the 16-bit ID word allows for 65,526 tools per tool type, each having a unique ID. The ID word
is sent to the RTU via logic signal IDENABLE/ when a transmit tool ID command is received from the
surface computer. ID request cycles are controlled on the RTU I/F Logic board by the transmit
control logic (refer to Exhibit 2-18). The format for the ID follows:
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 0
CONFIGURATION REVISION SERIAL NUMBER

LEVEL
(Rev. 01/95) 2-36

Exhibit 2-20: Schematic, Preset/ID Register
2-37 (Rev. 01/95)

Data Acquisition Control Circuit
The data acquisition cycle of the RTU I/F and the transmit data cycle are controlled by the data
acquisition control circuit (Exhibit 2-21), which consists of control PROM U2, map PROM U5,
control PROM counters U18 and U19, map PROM counter U20, control latches U23 and U24, and
counter U22. Acquisition cycles are initiated upon power-up, upon receipt of a new operating mode
data word by the RTU, and upon completion of a read cycle. This allows the surface computer to
immediately collect data following power-up or change the operating mode, and to continue to receive
data from the tool via data requests (read cycles). It is not necessary for the computer to specifically
initiate an acquisition sequence.
The sequencing of the channels is controlled by map PROM U5. Sequencing of the gain settings for
each channel is controlled by the control PROM U2 for both acquisition and read cycles. The control
PROM also controls the function timing on the RTU I/F analog board. Sequencing of the various
functions is accomplished by addressing locations on the map and control PROMs with counters U18,
U19, U20, and U22. Outputs from the PROMs are used to generate RAM memory addresses,
multiplexer addresses, gain settings; control signals SAMPLE/, CONVERT/, and WRITE/, and to
control the sequence of the acquisition control logic.
Locations 000 through 0FEH of control PROM U2 are addressed sequentially for each input channel
selected during an acquisition cycle by control counters U18, U19, and one bit of counter U22. By
sequentially addressing these locations, the control PROM instructs the RTU I/F to sample and hold
the signal for the selected channel with a gain of 1, to initiate an A/D conversion and wait for its
completion, to write the resultant digitized data into RAM, and then to repeat the sequence two more
times for gains of 8 and 64. Thus, for the DLLT-B, in which eight input channels are selected, the
control PROM is addressed through these locations eight times. For read cycles, the control PROM is
sequentially addressed from 100H through 103H for each channel acquired. Each cycle through these
locations results in the X1, X8, and X64 data for the addressed channel being fetched from RAM and
transmitted to the RTU. Table 2-4 describes the format for the 8-bit byte of the control PROM.
(Rev. 01/95) 2-38

Table 2-4: Control PROM Byte Format
BIT SIGNAL NAME FUNCTION

Q0 CONVERT Initiates A/D conversion when set and reset.
Q1 SAMPLE/HOLD Places the sample and hold amplifier in the hold mode when set.
Q2 MASK/ Not used.
Clears latch U24 when LOW, forcing a multiplexer address of 0
Q3 CLRU24/
and a gain of 0 (channel 0 and gain = 0).
Used to write data into RAM when LOW and to read data from
Q4 WRITE/=READ
RAM when HIGH.
Q5 These two bits form the two LSBs of the RAM and address and
GAIN B0,RAM B0
Q6 set the gain of the amplifier on the RTU I/F Analog board.
GAIN B1,RAM B0
Gain format (B1, B0) 00 = X1, 01 = X8, 11 = X64.
When HIGH, this bit clears the control PROM counter (U18,
Q7 COUNT CONTROL
U19) and enables the map counter.
2-39 (Rev. 01/95)

Exhibit 2-21: Schematic, Data Acquisition Control
(Rev. 01/95) 2-40

Addressing of the map PROM is determined by the output of the map PROM counter U20, the map
selected for the RTU I/F (CTRL0 through CTRL3), and Q7 of the control PROM. For both
acquisition and read cycles, the address sequence for the map PROM is the same.
Table 2-5 shows the sequence that occurs for both types of map 01 cycles.
Table 2-5: Map PROM and Multiplexer Address 01
MAP PROM ADDRESS (HEX) MULTIPLEXER CHANNEL ADDRESS

110 0
011 1
111 1
012 2
112 2
013 3
113 3
014 4
114 4
015 5
115 5
016 6
116 6
017 7
117 7
010 0
2-41 (Rev. 01/95)

When map one is selected, the first eight channels are sequentially addressed for each acquisition cycle
and read cycle. Table 2-6 shows the format for the 8-bit byte of the map PROM.
One other signal generated by the acquisition control logic is the BUSY signal. BUSY is generated
from the QA output of counter U22 which is set HIGH upon completion of a READ cycle. The signal
remains HIGH until the next acquisition cycle is completed.
Thus, BUSY indicates the current status of the RTU I/F: HIGH while an acquisition cycle is in
progress, and LOW when the acquisition cycle is complete with the collected data stored in RAM.
Table 2-6: Map PROM Byte Format
BIT SIGNAL NAME FUNCTION

Q0 MUX A0, RAM A2 These four bits form the multiplexer channel address
Q1 MUX A1, RAM A3 and bits A2 through A4 of the RAM address.
Q2 MUX A2, RAM A4
Q3 MUX A3, RAM A5
When HIGH, this bit indicates the end of the cycle for
both acquisition and read cycles. It causes map counter
Q4 CYCLE COMPLETE
U20 to be reset and counter U22 to be incremented.
Q5-Q7 Not used.
Tables 2-7 and 2-8 show the states of the various control signals of the acquisition control circuit.
Table 2-7 shows the acquisition cycles, and Table 2-8 shows the read cycles. Combined, the tables
show the actual sequence of the various operations performed by the RTU I/F during the acquisition
and read cycles.
(Rev. 01/95) 2-42

Table 2-7: Acquisition Control Circuit Control States
2-43 (Rev. 01/95)

Table 2-8: Read Cycle Circuit Control States
(Rev. 01/95) 2-44

Random Access Memory
The Random Access Memory (RAM) stores the digitized data. Exhibit 2-22 is the circuit diagram of
the data RAM, which consists of four 256 x 4 static CMOS RAMS (U35 through U38) that provide a
memory space of 256 16-bit words. The digitized data from the A/D converter is presented to the
memory ICs through U7 and U12, which serve as sockets for a jumper cable interconnecting the
analog and logic boards of the RTU I/F. Control signals SHCLOCK, MASK/, and SEROUT are not
used. The outputs of the RAM memory are appropriately tied to the RTU bus lines, BUS B0 through
BUS B15, to interconnect the RTU I/F with the RTU. Table 2-9 shows the RAM locations where
collected data is stored.
Table 2-9: Stored Data Locations
CHANNEL DATA RAM CHANNEL (HEX)

0 RTU I/F Zero X1, X8, X64 0, 1, 3
1 CALIPER X1, X8, X64 4, 5, 7
2 MSFL VE X1, X8, X64 8, 9, B
3 MSFL IA X1, X8, X64 C, D, F
4 V0 SHALLOW X1, X8, X64 10, 11, 13
5 I0 SHALLOW X1, X8, X64 14, 15, 17
6 V0 DEEP X1, X8, X64 18, 19, 1B
7 I0 DEEP X1, X8, X64 1C, 1D, 1F
2-45 (Rev. 01/95)

Exhibit 2-22: Schematic, Data RAM
Transactions and Timing
The four basic transactions that occur on the RTU I/F boards are the power-up reset sequence, the
receive control word (from RTU) sequence, the transmit ID (to RTU) sequence, and the transmit data
(to RTU) sequence.
The power-up reset sequence provides the tool with a preset operating mode, having NOT received a
control word at this point. The acquisition sequence also is initiated upon power-up as determined by
the map selected by the contents of the preset register.
(Rev. 01/95) 2-46

Exhibit 2-23 is the timing diagram for the power-up reset. Reset Q and reset Q/ are generated at
U14A upon application of 5-Vdc power due to a pulse generated at U16A. These signals remain
active until the first CLK1 occurs. Reset Q controls the data bus through the following control signals:
Signal Response
IDENABLE/ U10A is reset; Q output disables IDENABLE/through U3A
STATUSEN/ U1OB is reset; Q output disables STATUSEN/ through U3B
PRESETEN/ U14B is reset; Q/ output with RESET Q/ through U4C enables PRESETEN/
through U4D
RECEN Enabled by RESET Q/ through U4C
Exhibit 2-23: Timing Diagram, Power-Up Reset
2-47 (Rev. 01/95)

The combination of PRESETEN/ and RECEN loads preset information as determined by J3 onto bus
B0 through bus B15 via preset register U30 and U31 and into the control register U26 and U27.
CLEAR/ is the inverse of RECEN through U15F. This signal clears counters U18-U20 and U22 upon
CLK1, resetting the address sequence of acquisition control and map PROMs U2 and U5. The BUSY
flag is set through U15D when the counters are reset.
The RTU initiates handshaking to indicate that it has placed a data word on the RTU bus. This word is
a control word for the DLLT-B.
Exhibit 2-24 is the timing diagram for the receive control word sequence. When DATA WORD
FLAG from the RTU is present, upon CLK1, RECEN is set through U14B and U4C to enable the
control register (U26 and U27) to load the control word into the register.
Exhibit 2-24: Timing Diagram, Receive Control Word
(Rev. 01/95) 2-48

RD LSB&MSB REC DATA/ is set LOW by RECEN through U4B to notify the RTU that the word is
being received. The RTU then resets DATA WORD FLAG. CLEAR/ is set LOW by RECEN
through U15F to initialize the acquisition sequence.
The ID is a 16-bit word requested through the RTU identifying the tool.
Exhibit 2-25 is the timing diagram for the transmit ID sequence. The RTU sets IDREQUEST and
XMITDATAREQ HIGH to request ID transmission. When IDREQUEST is HIGH, STATUSEN/,
RDDATA/, and RAMS2/ are disabled through U13B, U1A, U3B, U3C, and U1B. This prevents
status or tool data from being placed on the bus.
When CLK1 occurs, IDENABLE/ is set LOW through U10A and U3A. LDXMIT LSB&MSB is
also set LOW by U10A. The contents of ID register U32 and U33 (as set by J2) are placed on the bus
and latched into the RTU buffer on the rising edge of LDXMIT LSB&MSB, which occurs at the next
CLK1.
Exhibit 2-25: Timing Diagram, Transmit ID
2-49 (Rev. 01/95)

Data is normally requested in a block. The RTU Interface sends data in a sequence as determined by
the map in use by the map PROM, as selected by bits of the control word. After each data word is
sent, the RAM address is changed to the next data location for access according to the map.
Exhibit 2-26 is the timing diagram for the transmit data sequence. When the RTU is ready to receive a
data word, it sets XMITDATAREQ HIGH. On CLK1, LDXMIT is set LOW through U10A.
If the RTU I/F is currently involved in data acquisition, the BUSY flag has been set at U15D. In that
case, LDXMIT causes STATUSEN to go LOW because of the state forced on U10B by the BUSY
flag, and the status word is placed on the bus by U25 and U34.
If, on the other hand, the acquisition cycle is complete (as is almost always the case), the BUSY flag
has deactivated. Since the Q output of U10B is set HIGH by BUSY and remains HIGH until the clock
cycle following LD XMIT LSB&MSB going LOW, STATUSEN/ goes LOW during the first clock
cycle, allowing the status word to be placed on the bus by U25 and U34. Thus, the RTU I/F status
word always precedes the data for each read cycle. During the next CLK1, the U10B outputs change
state. On the next occurrence of XMITDATAREQ and CK0LK1, LD XMIT LSB&MSB again goes
LOW, activating RDDATA/ and RAMS2/ through U3C and U1B. RDDATA/ enables the control
PROM counter (U18 and U19), allowing the control PROM to sequence through the data set.
RAMS2/ partially enables the RAM (U35 through U38) to load data onto the bus. CLK3 and CLK4
complete the RAM enable.
Data on the bus is latched into the RTU buffer by the rising edge of LDXMIT, which occurs at the
next CLK1.
(Rev. 01/95) 2-50

Exhibit 2-26: Timing Diagram, Transmit Data
2.7.4 General Comments RTU I/F
When the RTU requests data from the RTU I/F, the first word sent is the RTU I/F's status word
followed by the acquired data stored in RAM. Since a maximum of 49 data words (1 status + 16
channels X 3 words per channel) can be requested from the RTU I/F, two transmit data commands
must be sent to the RTU by the BCU whenever more than 32 data words are being transmitted by the
RTU I/F. When this is done, the second block of data begins where the first block of data leaves off.
The RTU I/F's status word is not included in this second block.
If the RTU requests data from the RTU I/F during an acquisition cycle (BUSY high), it will respond by
sending the auxiliary status word for each data request while busy is high. The time required for
acquisition is 1.275 milliseconds per channel for a maximum of 20.4 milliseconds if all 16 channels are
acquired. Since the number of channels acquired by the RTU I/F is fixed in firmware, it is important
that the correct number of data words be requested by the RTU. If less than the proper number of data
words for a given Map are requested, on subsequent requests the RTU I/F picks up where it left off on
the previous request. Therefore, the RTU I/F will not be in synchronization with the system. If more
than the proper number of data words are requested, the RTU I/F fills in the trailing data words with
it's status word.
2-51 (Rev. 01/95)

Table 2-10 shows the MAP PROM Maps and the channels acquired by each.
Table 2-10: MAP PROM Maps and Channels Acquired
MAP NUMBER CHANNEL(S) ACQUIRED

0 0 through 15
1 0 through 7
2 through 15 0
During logging operations, only Map 1 is used. The contents of the CONTROL PROM and MAP
PROM are provided in Section 8.
(Rev. 01/95) 2-52

2.8 RELAY DRIVER BOARD (3.42022)
Exhibit 2-27 is the block diagram and Exhibit 2-28 is the schematic for the Relay Driver board.
Drawing 3.01132, sheet 2, shows the Relay Driver board and its connecting circuitry.
The Relay Driver board (located in the Power and Telemetry Section) controls the states of the two
400-Hz control relays, K1 and K2. These relays apply or remove 400-Hz power to the MSFL
Mandrel circuitry. Opening and closing of the MSFL Mandrel is controlled by relay K1. Relay K2
disconnects the 400-Hz power from the mandrel motor circuitry when the DLLT-B is not in a motor
operate mode.
The Relay Driver board also contains a PROM (U1) which decodes five bits of the DLLT-B control
word and enables HEXFET relay driver transistors. Five relay driver circuits are located on the board,
but only two (RLY0 and RLY1) are used. Oscillator Y1 enables the PROM to drive the HEXFET to
the proper level.
Exhibit 2-27: Block Diagram, Relay Driver Board
2-53 (Rev. 01/95)

Exhibit 2-28: Schematic, Relay Driver Board
(Rev. 01/95) 2-54

2.9 REFERENCE COUPLING BOARD (3.42065)
Exhibit 2-29 is the schematic for the Reference Coupling board (3.42065). Also refer to drawing
3.42080, sheet 2, zone A-5.
The Reference Coupling board couples logging conductors #3 and #6 to the V0 Measurement board.
Conductors #3 and #6 connect, in the Power Control Panel (DPCP), to the Surface Reference
Electrode (fish). Capacitors on the board isolate dc potentials (head voltage monitor) on cable leads #3
and #6 from the V0 Measurement board.
Exhibit 2-29: Schematic, Reference Coupling Board
2-55 (Rev. 01/95)

2.10 MEASUREMENT SECTION OVERVIEW (3.01133)
The Measurement Section (Exhibit 2-30) contains a majority of the signal processing and measurement
circuitry for the Deep Laterolog (LLD) and Shallow Laterolog (LLS) investigations. To facilitate the
explanation of the DLLT-B circuitry, the 13 DLLT-B electrodes, electrode sonde preamplifiers, bridle
current return, and Surface Reference Electrode (fish) are depicted with the DLLT-B circuits.
The Switch Position board (3.32045) decodes the desired operating mode of the tool into
corresponding control signals and relay states for the various analog switches and relays on the
measurement and controller boards.
The Laterolog Oscillator board (3.33947) generates synchronized 131.25 Hz and 1050 Hz sinusoidal
and square-wave signals. The sinusoidal signals are utilized by the controller boards to generate the
waveforms applied to the A0, A3, and A4 electrodes. The square-wave signals from the Laterolog
Oscillator board are used to drive Phase Sensitive Detectors (PSDs) in the various measurement boards
and monitoring amplifiers.
The Measurement Section contains five Power Amplifiers (3.27280) which drive the A0, A3, and A4
electrodes. The power amplifiers are configured as shown in Exhibit 2-31, to form current supplies for
the electrodes. Transformers T1 - T5 couple the power amplifier outputs to the various electrodes.
(Rev. 01/95) 2-56

Exhibit 2-30: Block Diagram, Measurement Section
2-57 (Rev. 01/95)

Exhibit 2-31: DLLT-B Electrode Current Supplies
The Dual Sonde Preamplifier boards (3.33949), located in the electrode sonde, sense the voltage
gradients at the 131.25-Hz and 1050-Hz frequencies in the vicinity of the monitoring electrodes
M1/M3. The action of the controllers is to adjust the A3 and A4 electrode drives so as to regulate the
sensed potential difference at the M1/M3 electrodes to zero, thereby maintaining the focus of the survey
current from electrode A0. The outputs of the Dual Monitor Preamplifier boards drive the two Dual
Monitor Amplifier boards (3.33945) which convert the sensed potential differences from the M1/M3
electrodes into representative dc levels. The Dual Monitor boards employ band-pass filtering and PSD
circuitry to perform frequency selective measurements of the 131.25-Hz and 1050-Hz components of
the voltage gradient error at the M1, M2, and M3 electrodes.
The 1050-Hz error voltage outputs from the Dual Monitor boards are applied to the A3 Controller
board (3.32047) which establishes the 1050-Hz drive levels to the A3 Power Amplifiers to regulate the
M1/M2 potential difference to zero at the 1050-Hz frequency.
(Rev. 01/95) 2-58

The 131.25-Hz error voltage output from the Dual Monitor boards are applied to the A* Controller
board (3.32057), which establishes the 131.25-Hz drive level applied to the A4 electrodes. The drive
level established at the A4 electrodes, in conjunction with the drive levels established at the 131.25 Hz
at the A3 electrodes, regulate the M1/M3 potential difference at 131.25 Hz to zero.
The Auxiliary Monitor board (3.33943) amplifies any 131.25-Hz component on the voltage between
the A* and A4 electrodes, and converts that amplified component of the signal into a representative dc
voltage. Frequency selective filters and PSDs driven at the 131.25-Hz (LLD) frequency are used to
reject the large amount of 1050-Hz (LLS) components of the voltage appearing across the A*/A4
electrode pairs.
The outputs of the Auxiliary Monitor board are connected to the A3 Controller board, which
establishes the required 131.25-Hz drive level to be applied to the A3 electrodes. The 131.25-Hz drive
and 1050-Hz drive for the A3 electrodes are combined by a summing amplifier (differential amplifier).
The composite two-frequency output from the A3 controller, as mentioned, drive the A3 Power
Amplifier, which supply the A3 electrodes located on the DLLT-B Electrode Sonde.
The A0 Controller board (3.32059) establishes an A0 electrode drive signal, composed of

constant-amplitude 131.25-Hz and 1050-Hz components, to be applied to the A0 Power Amplifier.
The drive level component amplitudes are changed when the DLLT-B is switched from LOG mode to
CAL mode.
The A0 Power Amplifier drives the A0 electrode via transformer T5. Survey current emitted by the A0
electrode into the formation is sensed and measured by the I0 Measurement board (3.32063). The I0
Measurement board employs a current transformer to measure the 131.25-Hz and 1050-Hz current in
the conductor carrying current to the A0 electrode from the A0 Power Amplifier. The I0 Measurement
board employs band-pass filters and PSD circuitry to perform separate measurements of the 131.25-Hz
(LLD) survey current and 1050-Hz (LLS) survey current.
The V0 Measurement board (3.33975) measures the laterolog survey potential between the Remote
Surface Reference Electrode (fish) and the M2- electrode. The V0 Measurement board uses band-pass
filters and PSDs to separate and independently measure the 131.25-Hz and 1050-Hz components of
the laterolog survey voltage V0.
The filters and the PSD circuits also reduce the interfering effects of the telemetry signals appearing on
the cable conductors.
2-59 (Rev. 01/95)

Outputs from the I0 measurement board and V0 Measurement board, representative of the LLD and
LLS survey currents and voltages, are conducted to the P&T section. The current and voltage signals
are digitized and sent uphole to the surface equipment which computes the measured resistivities.
Not shown in Exhibit 2-30, but essential to proper DLLT-B operation, is a telemetry filter connected
to the DSTU line-drive output. This filter, located in the bridle head (or separate sub on earlier tools),
attenuates the telemetry signal in the vicinity of the laterolog shallow investigation frequency. This
unwanted harmonic could couple from conductor #7 to the surface reference conductors (#3 and #6)
and be amplified by the V0 Measurement board.
(Rev. 01/95) 2-60

2.11 TOOL SWITCH POSITION BOARD (3.32045)
Exhibit 2-32 is the block diagram of the Tool Switch Position board which places the DLLT-B
Measurement Section in its various modes of operation. The switch position circuit uses an EPLD
(EP600) to decode the address lines which set the laterolog, caliper, and MSFL circuitry to the ZERO,
CALIBRATE, or LOG modes.
Exhibit 2-32: Block Diagram, Tool Switch Position Board
2-61 (Rev. 01/95)

2.11.2 Switch Position
When a two-word command from the surface computer reaches the switch position controller via the
RTU I/F, a portion of the address is fed to the EPLD (U1), which decodes the address and then drives
the relays and analog switches that place the measurement section electronics in the desired mode. The
EPLD (U1) has sufficient output to drive the analog switches directly, but the relays take more current
and voltage. The decoder drives HEXFET transistors, which actuate their associated relay. As the
EPLD (U1) output goes high, the appropriate transistor turns on and connects one end of the relay coil
to ground, thus allowing current to flow from the +40-Vdc power supply through the relay. When the
U1 output goes low, the transistor shuts off, de-energizing the relay. Table 2-11 lists the driver
assignment for EPLD U1.
Table 2-11: EPLD U1 Driver Assignments
HEXFET
U1 OUTPUT RELAY
EPLD DRIVER SIGNAL ASSIGNMENT
Pin 3 Q1 RD3 K3, IO Measure Board
Pin 4 Q2 RD4 K1, Caliper Measure
Pin 6 Q4 RD7 K1, MSFL VE and IA Amplifier
Pin 8 Q6 RD0 K1, VO Measure Board
Pin 10 Q8 RD5 K2, Caliper Measure
Pin 16 N/A AS2 U2, A* Controller Board
Pin 16 N/A AS1 U3, U4 A3 Controller Board
Pin 17 N/A AS0 U3, A0 Controller Board
(Rev. 01/95) 2-62

Exhibit 2-33 is the schematic for the Tool Switch Position board (3.32045). Data stored in the EPLD
(U1) are relay and analog switch closure states that determine the DLLT-B mode of operation (e.g.,
LOG, CALIBRATE, ZERO).
The five RTU address lines are decoded by the self-latching EPLD (U1). The decoded outputs of U1
are connected directly to the analog switches on the various controller boards and to transistors Q1
through Q8. The drain of each transistor is connected to relays on the measurement boards, and each
sources is connected to ground. The IN459A diodes absorb the inductive kick from the relay coil
which occurs when the coil is de-energized. RLY4 and RLY7 are also passed through the electrode
sonde to the MSFL Relays.
2-63 (Rev. 01/95)

Exhibit 2-33: Schematic, Tool Switch Position Board
(Rev. 01/95) 2-64

2.12 LATEROLOG OSCILLATOR BOARD (3.33947)
Exhibit 2-34 is the block diagram of the 131.25 Hz, 1050 Hz Laterolog Oscillator board (3.33947).
The board generates the constant-amplitude reference sine waves used by the A0, A3, and A*
Controller boards to form the survey and focusing currents. A +15-Vdc reference provides a +6.2-
Vdc power supply for the CMOS digital logic circuits and the crystal oscillator (Y1) which generates
the 1050-Hz and 131.25-Hz square waves. The crystal oscillator generates a 1050-Hz, 6.2-Vdc square
wave which drives the clock input of the binary counter, whose output is a 131.25- Hz square wave.
The 1050-Hz output also drives a second-order Butterworth filter (1050-Hz center frequency) to
generate the 1050-Hz sine wave used by the controllers to produce the shallow investigation survey
current and focusing currents. A comparator circuit generates a 1050-Hz square wave from the
1050-Hz sine wave. The 131.25-Hz counter output drives a second-order Butterworth filter
(131.25-Hz center frequency) to produce the 131.25-Hz sine wave. This 131.25-Hz sine wave is used
by the controllers to produce the deep investigation survey and focusing formation currents. A
comparator circuit generates a 131.25-Hz square wave in sync with the 131.25-Hz sine wave. This
square wave output is utilized by Phase Sensitive Detectors (PSDs) to measure the 131.25-Hz
component, while rejecting the 1050-Hz component, of the two-tone signals. Similarly, the 1050-Hz
square-wave output is used by other PSD circuits to determine the 1050-Hz component, while
rejecting the 131.25-Hz component, of the two-tone signals.
Exhibit 2-34: Block Diagram, Laterolog Oscillator Board
2-65 (Rev. 01/95)

Exhibit 2-35 is the schematic of the Laterolog Oscillator board (3.33947). This board
generates the 131.25-Hz and 1050-Hz sine waves used by the laterolog controllers to
form the survey and focusing currents. The board also generates square-wave signals
for use in driving PSD circuits on the measurement and monitor boards.
Crystal oscillator Y1 generates a +6.2-Vdc, 1050-Hz symmetrical square wave which is

output to the clock input of U1. U1 is a binary counter set up to divide the 1050 Hz by
8, thus producing a 131.25-Hz square wave at its pin 12 output. The 1050-Hz output
on Y1-8 feeds a 1050-Hz second-order Butterworth VCVS band-pass filter (U2). The
output (U2-14) feeds a 1050-Hz second-order Butterworth biquad band-pass filter that
produces the 1050-Hz sine wave at U2-1. The U2-1 output (terminal 5) is the 1050-Hz
sine wave used by the controller boards to produce the shallow investigation survey
and focusing currents. U2-1 also drives a comparator (U4-2) that is set up to provide a
symmetrical 1050-Hz square wave. The U4-2 output (terminals 1 and 2) is used to
drive the shallow-frequency PSDs.
The 131.25-Hz output of the binary counter U1 feeds shaping, filtering, and clipping
circuitry that is functionally identical to the shallow circuitry described in the
preceding paragraph. The 131.25-Hz sine wave (terminal 6) is used by the deep
investigation circuitry and the 131.25-Hz square wave (terminals 3 and 4) is used to
drive the deep-frequency PSDs.
(Rev. 01/95) 2-66

Exhibit 2-35: Schematic, Laterolog Oscillator Board
2-67 (Rev. 01/95)

2.13 POWER AMPLIFIERS
The five Power Amplifiers that supply current to the A0, A3, and A4 electrodes are
nearly identical electrically. Exhibit 2-36 is a simplified schematic of the A4+ power
amplifier. This schematic supports the circuit description of the A4+ Power amplifier
that follows.
The input signal to be amplified is coupled through C8 to a hybrid circuit power

operational amplifier (Q2), which is configured as a non-inverting gain-of-two
amplifier. Resistor R19 provides bias current from ground to Q2. Resistor R20 limits
circuit-fault current into the input of Q2. Resistors R24 and R22 determine the gain of
the amplifier stage. Current flows through R24 and R22 to the inverting input of Q1,
which is maintained at virtual ground potential. The current flowing through R22 is
the input to amplifier Q1, which serves as an inverting amplifier with a gain of two.
The outputs of Q1 and Q2 drive a step-down transformer (T1). Resistor R32 limits dc
current in the transformer primary (the dc level at the outputs of Q1 and Q2 are
non-zero due to op-amp offset voltage and bias current). The secondary of the output
transformer couples the electrode drive current to the DLLT-B electrodes. The
amplitude of the signal across the primary of T1 is four times larger than the
magnitude of the input signal.
Each power op-amp is insulated from the chassis. The case, pin 3, and pin 4 of each
power op-amp are connected together to form the output terminal (see 3.10836, sheet
4).
Exhibit 2-36: Simplified Schematic, A4+ Power Amplifier
(Rev. 01/95) 2-68

Exhibit 2-37 shows how the five power amplifiers in the DLLT-B are interconnected.
Transformers T1 and T4 drive the A4 electrodes at 131.25 Hz, with respect to the
current return. Transformers T2 and T3 drive the A3 electrodes with respect to the A4
electrodes. Transformers T2 and T3 couple both 131.25-Hz and 1050-Hz current to the
A3 electrodes. Transformer T5 drives the A0 electrode, at both 131.25 Hz and 1050 Hz,
with respect to the current return. Resistor R31, in the current return conductor,
reduces the effect of the 1050-Hz current on the bridle current return. The 1050-Hz
current returns primarily to the A4+ and A4- electrodes. The primary winding of the
survey current measurement transformer and a 100-ohm swing resistor (both located
on the I0 measurement board) are connected between the output of the A0 power
amplifier and the A0 electrode.
Exhibit 2-37:
Interconnect Diagram, Laterolog Drive Transformers
2-69 (Rev. 01/95)

2.14 DUAL SONDE PREAMPLIFIER BOARD (3.33949)
Exhibit 2-38 is a block diagram of the Dual Sonde Preamplifier board. Two
preamplifier boards are located inside of the DLLT-B Electrode Sonde (underneath the
A0 electrode. One of the preamplifier boards amplifies the potential difference at the
sonde's upper monitor electrodes (M1+, M2+, and M3+) and the other preamplifier board
amplifies the potential difference at the sonde's lower monitor electrodes (M1-, M2-, and
M3-).
Exhibit 2-38: Block Diagram, Dual Sonde Preamplifiers
(Rev. 01/95) 2-70

Exhibit 2-39 is the schematic for the Dual Sonde Preamplifier board. The two
amplifiers (AR1) in each Dual Sonde Preamplifier board amplify the M1/M3 potential
difference (used for LLD focusing) and the M1/M2 potential difference (used for the LLS
focusing). Each amplifier is isolated via an input transformer, which is connected to
the sonde electrodes by a twisted conductor pair. Two op-amps are used in each
amplifier to produce a differential output. Resistors (499 ohm) are employed to
preserve high-frequency amplifier stability by isolating the op-amp outputs from the
capacitance of the twisted signal pair connecting the differential output to the Dual
Monitor Amplifier input.
The preamplifiers are located in pressure housings to isolate the borehole hydrostatic
pressure from the electronic components. Hermetic connectors are employed to permit
electrical power and signal connections to the preamplifiers.
Exhibit 2-39: Schematic, Dual Sonde Preamplifiers
2-71 (Rev. 01/95)

2.15 DUAL MONITOR AMPLIFIER BOARDS (3.33945)
Exhibit 2-40 is the block diagram of the Dual Monitor Amplifier board (3.33945). Two
boards are used in the DLLT-B. One board senses the upper voltage gradients
associated with sonde electrodes M1+, M2+, and M3+. The other board senses the lower
voltage gradients associated with sonde electrodes M1-, M2-, and M3-.
Each dual monitor amplifier receives as inputs two ac signals from the DLLT-B
electrode sonde preamplifiers. To determine if voltage gradient exists above the A0
electrode, a sonde preamp senses the differential voltage across the upper M1/M3
electrode pair. A separate preamp senses the differential voltage across the upper
M1/M2 electrode pair. The preamplifier output for the M1/M3 error controls the
131.25-Hz (LLD) drive applied to the A4+ electrode. The preamplifier output for the
M1/M2 error controls the 1050-Hz (LLS) drive applied to the A3+ electrode. The dual
monitor amplifier converts the ac sonde preamplifier outputs into dc levels indicative of
the voltage gradient or error at the monitoring electrodes.
The ac error from the M1/M3 sonde preamplifier is applied to an instrument amplifier
(U5). Extraction of the 131.25-Hz component of the ac error is performed by band-pass
filter (U3). A PSD synchronously rectifies the Band-Pass Filter (BPF) output into a dc
level proportional to the magnitude of the in-phase component of the 131.25-Hz BPF
output. An output buffer (U1) performs dc amplification of the PSD output. The
output of the buffer is applied to the A* controller, which in turn controls the 131.25-Hz
drive to the A4 electrode.
The monitoring of the M1/M2 electrode pair gradient error at the shallow investigation
frequency is virtually identical to that discussed for monitoring the M1/M3 deep
frequency error. One difference is the substitution of a 1050-Hz BPF to extract the
shallow frequency error (and reject the 131.25-Hz component). The shallow gradient
error measurements from the dual monitor boards are applied to the A3 controller to
regulate the 1050-Hz drive levels applied to the upper and lower A3 electrodes.
(Rev. 01/95) 2-72

The ac error from the sonde preamplifier, connected to M1/M2, is coupled to instrument
amplifier (U4). A 1050-Hz BPF (U3) extracts the 1050-Hz component of the error while
rejecting the 131.25-Hz component. A PSD and output buffer is employed as on the
M1/M3 monitoring circuit. The shallow gradient error signal is applied to the A3
controller board, which in turn establishes the 1050-Hz drive level applied to A3+.
Exhibit 2-40: Block Diagram, Dual Monitor Amplifier
2-73 (Rev. 01/95)

Operation of the second Dual Monitor board is identical except that separate sonde
preamps drive the instrument amplifiers (U4 and U5). The sonde preamps sense the
voltage gradient at sonde electrodes M1-/M3-.
Exhibit 2-41 is the schematic for the Dual Monitor Amplifier board (3.33945).
Monitoring of sonde electrode pair gradient error M1/M3 (at the deep investigation
frequency) is performed by coupling the amplified potential difference from the sonde
preamplifier output into amplifier U5, via C15 and C16. Amplifier U5 is an
instrumentation amplifier with high common mode rejection. The 131.25-Hz
component of the U5 output is representative of the 131.25-Hz M /M error.
1 3
Also present at the U5 output is a 1050-Hz component, since the shallow investigation
circuitry operates simultaneously with the deep investigation circuitry. This shallow
error is filtered out by a band-pass filter so that only the deep component of the error
signal is measured. Therefore, the instrumentation amplifier is followed by a
131.25-Hz band-pass filter (BPF). Test point TP14 is the output of the BPF. Amplifier
U3-7 is a phase inverter needed for synchronous detection.
Connected to the filter and inverter output is a synchronous detection circuit (PSD)
that rectifies the deep component of the input and rejects to a high degree the shallow
component not removed by the BPF. The synchronous detector consists of a portion of
analog switch U2 (pins 14, 13, 12, and 3). The output at U2-13 appears as a rectified
sine wave when a 131.25-Hz error is present. When the tool is in actual operation and
regulating the gradient error to zero, the error at the electrodes is extremely small, on
the order of a few tens of microvolts. Therefore, the output at pin 13 is correspondingly
small (a few millivolts).
The output of the synchronous detector is applied to a buffer (U1-7), forming a dc-error
voltage, which is then sent to the A* controller.
(Rev. 01/95) 2-74

Exhibit 2-41: Schematic, Dual Monitor Amplifier Board
2-75 (Rev. 01/95)

2.16 A3 CONTROLLER BOARD (3.32047)
The A3 controller looks at dc-error signals originating from the Dual Monitor Amplifier
and Auxiliary Monitor Amplifier boards. The controller increases or decreases the
131.25-Hz or 1050-Hz components on the A3+ and A3- electrodes. If the error is a
positive dc voltage, the control circuit continually increases the drive level going to the
power amplifier. If the error is a negative dc voltage, the control circuit continually
decreases the drive level going to the power amplifier. If the error is zero, the control
circuit does not make any adjustment of the drive level.
Exhibit 2-42 is the block diagram of the A3 Controller board (3.32047). It controls the
amplitude of the A3+ and A3- currents emitted into the formation. This controller
consists of four similar circuits; two control the A3+ (upper A3 electrode) drive and two
control the A3- drive. The integrator response to the lower deep A* error is as follows:
INPUT OUTPUT RESPONSE

Lower deep error > 0 volts Ramps toward -15-Vdc
Lower deep error = 0 volts Maintains current value
Lower deep error < 0 volts Ramps toward +15-Vdc
Similar input/output relations hold for all four integrators in the controller.
(Rev. 01/95) 2-76

Exhibit 2-42: Block Diagram, A3 Controller
Each integrator output is applied to an input of an analog multiplier. The other input
of the multiplier is either a 131.25-Hz or 1050-Hz sinusoid. The output of the
integrator represents (when the circuits are functioning correctly and have settled) the
drive level to be applied to the respective electrode at the 131.25-Hz or 1050-Hz
frequency. The analog multiplier output is a sinusoid whose amplitude increases or
decreases as the dc level from the integrator increases or decreases.
To determine the 131.25-Hz and 1050-Hz components of the A3+ (e.g., drive), two
integrator/multiplier sections are used. Note that the dc signal indicative of the
1050-Hz errors to the integrator come from the Dual Monitor Amplifier board, while the
dc signals indicative of the 131.25-Hz errors originate in the Auxiliary Monitor
Amplifier board.
Integrator outputs in the A3+ (upper) controller circuitry cause 131.25-Hz and 1050-Hz
sinusoids to be developed at the outputs of U5 and U6. The sinusoids are summed
together to form a two-tone composite waveform which is amplified by a power
amplifier and applied to A3+.
2-77 (Rev. 01/95)

The output of the controller circuitry related to the A3- (lower A3) electrode is identical.
Analog switches are used to disconnect and ground the multiplier inputs (resulting in
zero multiplier outputs) when the DLLT-B is not in the LOG mode. This provides
overload protection for the power amplifiers under severe loading (such as are
encountered in casing).
Exhibit 2-43 is the schematic of the A3 Controller board (3.32047). It consists of four
equivalent circuits (an upper pair and a lower pair). The following paragraphs discuss
only the lower controller circuits, but the operation described is similar for each of the
upper controller circuits.
The lower deep A* error originating from the Auxiliary Monitor board is applied to
integrator U1-8. The integrator output from U1-8 is inverted by U2-8 and is applied to
analog multiplier U9, which is also supplied with a 131.25-Hz sinusoid of constant
amplitude via buffer U10-14. The analog output is a 131.25-Hz sinusoid of a
magnitude proportional to the magnitude of the integrator output. Buffer U10-1
couples the 131.25-Hz component of the lower A3 drive to summing amplifier U10-8.
A similar integrator (U1-14) determines the 1050-Hz component of the lower A3 drive.
The integrator input originates in the Dual Monitor Amplifier. An external capacitor (3
microfarad) is used for the shallow gradient error integrator. The dc output from
integrator U1-14 is inverted by U2-14 and applied to analog multiplier U8. The
multiplier is supplied with a constant amplitude 1050-Hz sinusoid from buffer U7-14.
The variable amplitude 1050-Hz sinusoid from U8 is buffered by U10-7. Combining of
the 131.25-Hz and 1050-Hz components of the A3- drive signal occurs in summing
amplifier U10-8. The lower A3 drive signal is applied to a power amplifier whose
output supplies current to sonde electrode A3-.
Analog switches U3 and U4 ground the analog multiplier inputs when not in the LOG
mode. Grounding of the multiplier inputs occurs when the control line is 5-Vdc.
(Rev. 01/95) 2-78

Exhibit 2-43: Schematic, A3 Controller Board
2-79 (Rev. 01/95)

2.17 A* CONTROLLER BOARD (3.32057)
Exhibit 2-44 is the block diagram of the A* Controller Board. The A* Controller board
has no effect on the operation of the shallow (LLS) investigation. The function of the
A* Controller board is to determine and establish the 131.25-Hz drive level to be
applied to the A4+ and A4- electrodes for proper deep (LLD) operation. Primary inputs to
the board are the dc signals indicative of the gradient errors at the sonde electrode
M1/M3 pairs. The dc signals are derived from the cascaded operation of the sonde
preamps and the dual monitor circuitry. Outputs from the A* controller are the 131.25
Hz variable-amplitude sinusoids which are amplified by the A4 Power Amplifiers to
supply excitation current to electrodes A4+ (Measurement Section Housing) and A4-
(MSFL Mandrel Housing).
Exhibit 2-44: Block Diagram, A* Controller Board
(Rev. 01/95) 2-80

Exhibit 2-45 is the schematic of the A* Controller board (3.32057). Operation of the
control circuitry for A4+ is identical to the control circuitry for the A4-. To simplify this
discussion, only the A4+ circuitry is discussed.
The dc signal indicative of the 131.25-Hz error sensed at the upper M1/M3 pair is
applied from the output of the dual monitor board to the P1 input of the A* Controller
board. Integrator U1 increases or decreases the voltage at TP1 (for non-zero gradient
error) to drive the gradient error towards zero. The voltage at TP1 is coupled through
switch U2 to an analog multiplier U3, which is also supplied with the 131.25-Hz
sinusoid from the Laterolog Oscillator board. The output sinusoid from U3, which is
proportional to the magnitude of the voltage at TP1, is buffered by U5-14. The buffer
amplifier drives a power amplifier which supplies the A4+ electrode.
Analog switch U2 grounds the inputs of analog multipliers U3 and U4 when not in the
LOG mode. The multiplier inputs are grounded when terminal P5 (control) is at +5-
Vdc.
2-81 (Rev. 01/95)

Exhibit 2-45: Schematic, A* Controller Board
(Rev. 01/95) 2-82

2.18 A4 CAPACITOR BOARD (3.33941)
See Exhibit 2-46 and drawing 3.32065, sheet 2.
The integrator capacitors are mounted on the A4 Capacitor board, for the two A*
controller integrators.
Exhibit 2-46: Schematic, A4 Capacitor Board
2-83 (Rev. 01/95)

2.19 AUXILIARY MONITOR BOARD (3.33943)
Exhibit 2-47 is the block diagram and Exhibit 2-48 is the schematic of the Auxiliary
Monitor board (3.33943). The board has two identical circuits, upper and lower.
Because the upper and lower circuits are identical, only the upper (A4+/A*+) circuit is
described.
Input to the auxiliary monitor is capacitively coupled to an instrumentation amplifier

U1. The output of this amplifier is a measurement of the voltage across the A*+
electrode and the A4+ electrode. This output is passed through a 131.25-Hz biquad
band-pass filter that attenuates the shallow investigation frequency (1050 Hz)
component of the amplified signal.
Exhibit 2-47: Block Diagram, Auxiliary Monitor Board
(Rev. 01/95) 2-84

The output of the filter (TP4) is buffered and inverted by phase buffer and inverter
U7-7, U7-14. A PSD synchronously rectifies the 131.25-Hz component of the filtered
output, and rejects the 1050-Hz shallow frequency component. The PSD output is
buffered by U9-14. An inverted output (opposite polarity) is available from U9-1, but is
not used on the DLLT-B.
The PSDs for the upper and lower A4/A* monitoring circuits are driven by the
131.25-Hz PSD drive square wave from the Laterolog Oscillator board.
Outputs from the Auxiliary Monitor board are the deep A* errors, which are utilized by
the A3 controller to establish the 131.25-Hz component of the drive to the A3+ and A3-
electrodes.
The Auxiliary Monitor board does not have a functional part in the shallow (LLS)
measurement.
2-85 (Rev. 01/95)

Exhibit 2-48: Schematic, Auxiliary Monitor Board
(Rev. 01/95) 2-86

2.20 A0 CONTROLLER BOARD (3.32059)
Exhibit 2-49 is the block diagram and Exhibit 2-50 is the schematic of the A0 Controller
board.
The A0 controller establishes the 131.25-Hz and 1050-Hz drive levels to the A0 Power
Amplifier, and consequently, to the A0 sonde electrode. In the LOG mode, the output
from the A0 controller is a two-frequency (131.25 Hz/1050 Hz) signal of non-varying
amplitude. When the DLLT-B is switched to the CALIBRATE mode, the amplitude of
the 131.25-Hz and 1050-Hz frequencies, which constitute the output signal, are
changed.
Exhibit 2-49: Block Diagram, A0 Controller Board
2-87 (Rev. 01/95)

Two potentiometers and two voltage dividers provide for four independent voltages
(131.25-Hz CAL and LOG, 1050-Hz CAL and LOG), which are selected by analog
switch U3. Each voltage of the pair selected (LOG or CAL) is supplied to one input of
an analog multiplier, e.g., the 131.25-Hz signal is supplied to the input of U4. The
other input of the analog multiplier is supplied with a sinusoidal reference from the
Laterolog Oscillator board. The outputs of the Multipliers U4 and U5 are proportional
to the dc voltages applied through the analog switch U3. The 131.25-Hz and 1050-Hz
components are summed by AR1, which drives the A0 power amplifier circuitry. Switch
U3 selects the 131.25-Hz and 1050-Hz logging levels if the switch control line is 0-Vdc
and the 131.25-Hz and 1050-Hz CAL levels are selected when the control line is 5-Vdc.
Exhibit 2-50: Schematic, A0 Controller Board
(Rev. 01/95) 2-88

2.21 I0 MEASUREMENT BOARD (3.32063)
Exhibit 2-51 is the block diagram of the I0 measurement circuitry, which measures the
magnitude of the survey current for the deep investigation and for the shallow
investigation. The major component of this circuit is the I0 Measurement board
(3.32063), which measures the secondary current of the A0 coupling power transformer.
This measurement is separated into the deep and shallow components by band-pass
filters. The separate ac measurements are then sent to PSDs to be rectified. The
rectified measurements are filtered and form the deep and shallow survey signals that
are sent to the telemetry system and to the A0 controller. These signals, representative
of currents, are used in measuring the deep and shallow formation resistivities.
Exhibit 2-51: Block Diagram, I0 Measurement Board
2-89 (Rev. 01/95)

The I0 measurement circuitry (Exhibit 2-52) performs measurements of the deep (LLD)
and shallow (LLS) survey current emitted from the A0 electrode during logging and
shop calibration. In the internal calibrate mode, a composite 131.25-Hz/1050-Hz signal
is impressed upon a calibration resistor. The I0 measurement circuits, in a calibration
mode, measure the current through the calibration resistor. A pickoff point on the
calibration resistor is provided for the V0 measurement board to simultaneously read
the resistor voltage.
Composite 131.25-Hz and 1050-Hz current from the A0 power amplifier is coupled
(during logging) through relay K2, K3, and current transformer T1 to resistor R33 and
the A0 electrode. Resistor R33 provides a means of varying the survey voltage as the
resistivity of the survey formation changes. A lower resistance presented by the
formation to the A0 electrode causes an increased voltage drop at both the LLD and
LLS frequencies across R31, resulting in a lower survey voltage V0. Conversely, a high
resistivity (high V0 resistance) formation allows the survey voltage V0 to rise.
Transformer T1 is a 200:1 step-up transformer. The secondary of T1 is connected to a

virtual ground (AR1-2) through capacitor C12. Resistor R2 provides a means of gain
adjustment. Resistor R3 satisfies bias current requirements for AR1.
Following the current amplifier stage of AR1 and T1 are two band-pass filters (BPF)
and a phase inverter. The BPFs separate the 131.25-Hz and 1050-Hz components of
the survey current I0. Switch U1 implements PSDs which synchronously rectify the
131.25-Hz and 1050-Hz components of I0 into dc voltage levels. The outputs of the PSD
circuits are connected to Low-Pass Filters (LPF), each with a dc-voltage gain of 3. The
6-decibel (db) cutoff frequency for the LPFs is 5 Hz. The LPFs smooth the PSD outputs,
attenuating ripple frequencies introduced by the synchronous rectification process.
The LPF outputs from AR3 (I0d and I0s) are sent to the RTU Interface for digitizing and
transmission to the surface equipment.
(Rev. 01/95) 2-90

Relays K1, K2, and K3 are energized by the relay drivers on the Switch Position board.
In the calibration mode, the K1 relay switches the I0 current from the A0 electrode to
the calibration resistors R30 (deep calibration) and R31 (shallow calibration). Relay K2
selects whether the I0 measurement circuit measures the current through the deep
calibration or the shallow calibration resistor. V0 calibrations are measured across
these resistors; therefore, a connection is made from the K2 relay wipers to the V0
measurement circuit via Terminal P10.
The I0d and I0s circuits are driven by the 131.25-Hz and 1050-Hz PSD drive square
waves from the Laterolog Oscillator board.
2-91 (Rev. 01/95)

Exhibit 2-52: Schematic, I0 Measurement Board
(Rev. 01/95) 2-92

2.22 V0 MEASUREMENT BOARD (3.33975)
Exhibit 2-53 is the block diagram of the V0 Measurement board 3.33975. It measures
the survey formation potential for the deep and shallow investigations.
The V0 Measurement board determines the survey potential for both the shallow and
deep investigations across sonde electrode M2- and the surface reference electrode (N
electrode). The signal across these two locations is sensed by an instrumentation
amplifier and is then band-pass filtered into the shallow and deep components. The
separate ac components are then sent to PSDs for synchronous rectification. The dc
outputs from the PSDs are filtered by low-pass filters to obtain Vod and Vos, which are
transferred to the surface equipment.
Exhibit 2-53: Block Diagram, V0 Measurement Board
2-93 (Rev. 01/95)

The survey voltage is measured by the V0 Measurement board (3.33975), which

involves the following components:
• Calibration switch circuit

• Input instrumentation amplifier
• Deep band-pass filter (BPF) and inverter
• Deep synchronous rectifier
• Deep low-pass filter (LPF)
• Shallow BPF and inverter
• Shallow synchronous rectifier
• Shallow low-pass filter
Exhibit 2-54 is the schematic for the V0 measurement board. The shallow and deep
circuits are functionally identical. To simplify this discussion, only the deep circuitry is
discussed.
The input instrumentation amplifier (U1) extracts and measures the 131.25-Hz and
1050-Hz components of the voltage across terminals P1 and P6 (LOG) or the voltage
across terminals P2 and P5 (CAL/ZERO). The calibration relay (K1) switches the input
of the amplifier from the log inputs to the calibration inputs.
The 131.25-Hz BPF (U2-4) extracts the 131.25 Hz (LLD) component of the signal from
U1 and the phase inverter (U2-8) develops a voltage 180-degrees out of phase with the
131.25-Hz BPF output. A PSD (U5) switches between the filter output (U2-4) and the
inverter output (U2-8), selecting the filter output or the inverter output. The deep PSD
drive actuates U5 by connecting pin 10 to pin 11 when the 131.25-Hz PSD drive is zero
and connecting pin 10 to pin 9 when the 131.25-Hz PSD drive is positive. The PSD
output appears as a rectified sine wave. A LPF (U4-1) smoothes the synchronous
rectifier output and outputs the deep (LLD) survey voltage V0d.
(Rev. 01/95) 2-94

Exhibit 2-54: Schematic, V0 Measurement Board
2-95 (Rev. 01/95)

2.23 ELECTRODE SONDE
The Electrode Sonde (3.42100) is constructed of insulating fiberglass upon which the
A0, A*, A3, and M1 - M3 electrodes are mounted. Interior to the sonde are a pair of
pressure-balancing bellows, the two Dual Sonde Preamplifier boards, and the MSFL
electronics assembly (3.10518). The sonde is filled with an insulating silicone oil to
minimize volumetric contraction of the bellows under hydrostatic loading of the sonde,
and to prevent borehole fluid contamination of the electrode wiring.
The majority of the A4+ electrode is provided by the housing of the measurement
section. The majority of the A4- electrode is provided by the MSFL mandrel housing.
Two electrical connections to the A4- electrode are provided via the chassis of the MSFL
electronics.
(Rev. 01/95) 2-96

2.24 MSFL AND CALIPER OVERVIEW
Exhibit 2-55 is a block diagram of the MSFL and caliper circuitry.
2.24.1 General Description
The caliper measurement is performed with a 10K-ohm potentiometer, mechanically

linked to the MSFL Mandrel pad arm. R1 and C1 on the MSFL chassis supply a stable
6.2-Vdc to the potentiometer. The potentiometer wiper voltage is amplified and
buffered by a dc amplifier on the Caliper Measurement board (3.32060), which is
located in the measurement section. Calibration voltages for the amplifier are selected
by relays K1 and K2, in the internal calibrate mode of operation. The output of the
Caliper Measurement board is digitized by the RTU Interface for transmission to the
surface equipment.
The MSFL circuitry, primarily located in the DLLT-B Electrode Sonde, performs pad
voltage and current measurements. The MSFL circuitry supplies the MSFL with a
960-Hz sinusoidal drive current.
The Preamplifier board (3.10506), located in the MSFL pad, serves as an error
amplifier for the potential between the monitor electrodes M1/M2.
2.24.2 Detailed Description
Power and switching controls are derived from the DLLT-B Measurement section and
are passed through the sonde to the MSFL electronics.
The MSFL Oscillator board (3.10467) generates 960-Hz sinusoidal and square-wave
signals. The sinusoidal signals are used by the power amplifier board (3.10500) and
focus controller board (3.10502) to generate waveforms which are applied to the A0 and
A1 electrodes. The square-wave signals drive phase sensitive detectors (PSDs) on the
focus controller board and measurement board (3.10504).
2-97 (Rev. 01/95)

Exhibit 2-55: Block Diagram, MSFL and Caliper Section
(Rev. 01/95) 2-98

2.25 CALIPER MEASUREMENT BOARD (3.02060)
Exhibit 2-56 is the block diagram and Exhibit 2-57 is the circuit diagram for the
Caliper Measurement board.
The caliper sensor, located inside the lower housing of the MSFL Mandrel, is a 10K-
ohm linear potentiometer which senses the distance between the MSFL pad and wear
shoe. The caliper board provides a dc output voltage indicative of the potentiometer
wiper position. A 6.2-Vdc reference voltage from R1 and C1 (mounted on the MSFL
electronics chassis) is applied to the top of the potentiometer. The bottom end of the
potentiometer is tied to circuit ground. The voltage from the potentiometer wiper is
sent to the Caliper Measurement board (located in the measurement section) where
amplifier AR1 senses and amplifies the wiper voltage. The caliper signal output from
AR1 is sent to the P&T section, where it is digitized for transmission to the surface.
Exhibit 2-56: Block Diagram, Caliper Survey
2-99 (Rev. 01/95)

Exhibit 2-57: Schematic, Caliper Measurement Board
(Rev. 01/95) 2-100

2.26 OSCILLATOR BOARD (3.10467)
Exhibit 2-58 is the block diagram for the Oscillator board and Exhibit 2-59 is the
schematic.
The crystal oscillator generates a 960 Hz, 5-Vdc square-wave signal which drives a
second-order Butterworth bandpass filter. The resulting signal drives a second-order
biquad bandpass filter. Two sinusoidal-shaped signals are derived from the biquad
filter, 90-degrees apart, which are used to create the survey and focusing formation
currents. A comparator circuit also uses these signals to generate square waves, also
90-degrees apart, to drive the focusing and measurement PSDs.
Crystal oscillator Y1 generates a 5-Vdc, 960 Hz symmetrical square wave (TP1), which
feeds the Butterworth VCVS bandpass filter (AR1). The filter output (AR1-7) feeds a
960-Hz biquad filter that generates the 960-Hz Sine and Cosine drive signals. These
Sine and Cosine signals also drive comparators (U1), which generate the square-wave
(SQW) and "X" square wave (XSQW) PSD drive signals.
Exhibit 2-58: Block Diagram, Oscillator Board
2-101 (Rev. 01/95)

Exhibit 2-59: Schematic, Oscillator Board
(Rev. 01/95) 2-102

2.27 POWER AMPLIFIER BOARD (3.10500)
There are two MSFL power amplifiers located on the power amplifier board. Each
amplifier consists of two power operational amplifiers that are configured as
differential amplifiers to drive accompanying power transformers.
Exhibit 2-60 is the block diagram for the Power Amplifier board and Exhibit 2-61 is the
schematic.
The Focus and Survey Power Amplifiers are nearly identical, so for simplicity, only the
Focus Power amplifier is discussed. The major difference between the two circuits is
that the input signal to the Survey Power Amplifier is attenuated by the R1/R2 resistor
combination.
The input signal (TP6) is coupled through capacitor C2 to the power op-amp (AR1),
which is configured as a non-inverting gain-of-two amplifier. Resistor R4 provides bias
current from ground to AR1. Resistor R3 limits circuit-fault current into AR1. Resistor
R6 and R8 determine the gain of the amplifier stage. Current flows through R6 and R8
to the inverting input of AR2, which is maintained at virtual ground potential. The
current flowing through R8 is the input to the amplifier (AR2), which serves as an
inverting amplifier with a gain of two. The outputs of AR1 and AR2 drive a step-down
transformer (T2). Resistor R9 limits dc current in the transformer primary (the dc level
at the outputs of AR1 and AR2 are non-zero due to op-amp offset voltage and bias
current). The secondary of the output transformer couples the electrode drive current
to the MSFL electrodes. R19, C9, R20, and C10 prevent circuit oscillation.
Exhibit 2-60: Block Diagram, Power Amplifier Board
2-103 (Rev. 01/95)

Exhibit 2-61: Schematic, Power Amplifier Board
(Rev. 01/95) 2-104

2.28 PREAMPLIFIER BOARD (3.10506)
Exhibit 2-62 is the block diagram for the Preamplifier board and Exhibit 2-63 is the
schematic.
This board amplifies the very small error potential between the M1 and M2 electrodes,
which are located on the MSFL pad. This provides an amplified signal that is less
susceptible to the noise in the mandrel wiring.
The amplifier is isolated via an input transformer (T1), which is connected to the pad
electrodes. Thus, the transformer-coupled input signal is fed to the upper op-amp,
which is configured as a non-inverting, gain-of-26 amplifier. Resistors R6 and R5
determine the gain of the amplifier stage. Current flows through R6 and R5 to the
inverting input of the lower op-amp, which is maintained at virtual ground potential.
The current flowing through R5 is the input to the lower stage and serves as an
inverting amplifier, with a gain of 26. The resulting output is an ac error signal that is
sent to the Focus Controller board.
Resistors R3 and R4 provide signal stability and balance. The primary center tap (P2)
of the input transformer (T1) is used by the V0 measure circuit.
Exhibit 2-62: Block Diagram, Preamplifier Board
2-105 (Rev. 01/95)

Exhibit 2-63: Schematic, Preamplifier Board
(Rev. 01/95) 2-106

2.29 FOCUS CONTROLLER BOARD (3.10502)
Exhibit 2-64 is the block diagram for the Focus Controller board and Exhibit 2-65 is the
schematic.
The Focus Controller Board takes the signal from the preamplifier board and processes
it into a drive signal for the A1 power amplifier. The ac error signal from the M1/M2
preamplifier is applied to an instrumentation amplifier (monitor amp). The 960-Hz
component of the ac error signal is extracted by the Butterworth VCVS bandpass filter
(BPF). The filter output is rectified by the PSDs into dc levels proportional to the
magnitude of the in-phase (R error) and 90-degree (X error) components of the BPF
output. These dc signals are applied to integrators whose outputs represent the drive
level to be applied to the focusing electrode (A1). The integrator response to its inputs
are listed in Table 2-12.
Table 2-12: Integrator Responses
INPUT OUTPUT RESPONSE

Error > 0 volts Ramps toward -15-Vdc
Error = 0 volts Maintains current value
Error < 0 volts Ramps toward +15-Vdc
Exhibit 2-64: Block Diagram, Focus Controller Board
2-107 (Rev. 01/95)

The integrator responses are fed to analog multipliers whose other inputs are the Sine
(for the in-phase signal) or Cosine (for the 90- or X signal) signals from the oscillator
board. The multiplier outputs are sinusoids that increase or decrease in amplitude as
the dc levels from the respective integrators increase or decrease. These signals are
then summed together to form a single A1 drive signal that is sent to the Power
Amplifier board,
(Rev. 01/95) 2-108

Exhibit 2-65: Schematic, Focus Controller Board
2-109 (Rev. 01/95)

2.30 MEASUREMENT BOARD (3.10504)
Exhibit 2-66 is the block diagram of the Measurement board and Exhibit 2-67 is the
schematic.
The Measurement board measures both the survey potential (V0) and the survey
current (I0) of the MSFL. The V0 measurement is made across the M0 electrode and the
M1/M2 transformer center tap. This potential is sensed by an instrumentation
amplifier, bandpass filtered into its ac components, synchronously rectified by the
phase sensitive detector, and filtered by the low-pass filter to produce the dc telemetry
that is transferred to the surface equipment. The I0 measurement is made by the
current transformer in series with the secondary of the A0 drive transformer, before the
addition of the A1 current and after the swing resistor. The signal is sensed by a
current amplifier, bandpass filtered, rectified by the PSD, and low-pass filtered to
produce its dc telemetry signal.
The V0 instrumentation amplifier is defined by AR1. Its output (TP1) drives the
second-order Butterworth VCVS 960 Hz bandpass filter (AR3), which feeds the PSD
(U1). The PSD is driven by the SQW signal from the Oscillator board. The rectified
signal (TP4) enters the low-pass filter (5 Hz Fc) to deliver a smooth dc signal (I0).
Exhibit 2-66: Block Diagram, Measurement Board
(Rev. 01/95) 2-110

Exhibit 2-67: Schematic, Measurement Board
2-111 (Rev. 01/95)

Dual Latero Log Theory

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SECTION 1

• Section 3, Disassembly/Assembly, contains step-by-step disassembly and assembly procedures

• Section 5, Troubleshooting, contains a series of circuit checks complete with corresponding

1-1 (Rev. 01/95)

1.2 EQUIPMENT DESCRIPTION

• Deep survey current (I0d)

(Rev. 01/95) 1-2

1-3 (Rev. 01/95)

(Rev. 01/95) 1-4

• Cable Electrode Assembly, 3.6000 (Optional rigid cable electrode 3.10142)

• Power and Telemetry Section Assembly, 3.01132

• Centralizer Equipment, 3.35130 and 3.07055

• Isolation Sub Assembly, 3.39020

• Measurement Section Assembly, 3.01133

• Electrode Sonde Assembly (Laterolog Sonde), 3.10510

• MSFL Mandrel Assembly, 3.33175

1-5 (Rev. 01/95)

The Rigid Cable Electrode (3.10142) is available as an option.

1.3.2 Power and Telemetry Section Assembly, 3.01132

(Rev. 01/95) 1-6

• Dual 15-Vdc regulated supplies

• +5-Vdc regulated supply

• +40-Vdc unregulated relay supply

Remote Telemetry Unit (RTU)

Mandrel Arms Controller

1-7 (Rev. 01/95)

1.3.4 Measurement Section Assembly, 3.01133

1.3.5 Electrode Sonde Assembly, 3.10510

(Rev. 01/95) 1-8

A0 Survey-current emitting electrode for both deep and shallow investigations

M3+, M3- Monitor electrodes for deep investigation

A*+, A*- Monitor electrodes for deep investigation

1.3.6 MSFL Mandrel Assembly, 3.33175

1.3.7 Centralizer Equipment

1-9 (Rev. 01/95)

A0 Survey-current emitting electrode for the MSFL

M0 Voltage monitor electrode

1.3.8 MSFL Calibrator Box, 3.01209

1.3.9 Dual Laterolog Formation Simulator Set, 3.34254

(Rev. 01/95) 1-10

2.1 PRINCIPLES OF OPERATION

2.1.1 Nature of the Measurements

2-1 (Rev. 01/95)

(Rev. 01/95) 2-2

2.1.2 Dynamic Focusing

2-3 (Rev. 01/95)

(Rev. 01/95) 2-4

2.1.3 DLLT-B Depths of Investigation

• Approximately 5 - 7 feet into the formation (deep laterolog investigation)

• Approximately 2 - 3 feet into the formation (shallow laterolog investigation)

2-5 (Rev. 01/95)

Exhibit 2-2: Shallow Laterolog Current Flow

(Rev. 01/95) 2-6

2.1.4 MSFL Investigation

2-7 (Rev. 01/95)

(Rev. 01/95) 2-8

2-9 (Rev. 01/95)

(Rev. 01/95) 2-10

• Dual 15-Vdc regulated supplies (650 milliamperes)

2-11 (Rev. 01/95)

(Rev. 01/95) 2-12

2.4.1 +5-Vdc Rectifier/Filter Board (3.29710)

Exhibit 2-6: Schematic, +5-Vdc Rectifier/Filter Board

A+, A- Monitor electrodes for deep investigation