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Remake LCR Meter - Elektor Magazine PDF
Remake LCR Meter - Elektor Magazine PDF
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Elektor Labs
Elektor Project Plegde 13% Funded Back this project i
More than 7 years ago, Elektor published my 500 ppm LCR-meter. Since then
I have developed a new LCR meter, sacri cing a little on extreme accuracy for
the sake of extended functionality:
- Test frequency from 50Hz to 2MHz.
- 4 possible test voltages (100mV, 200mV, 500mV and 1V rms).
- Additional DC polarization up to 5V for capacitors and 50mA for inductors.
Particular attention has been paid to its ease of implementation (calibration) and
use (a rotary encoder is used to navigate through the menu and to change the
frequency).
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LCR-meter AU2019
(https://www.elektormagazine.com)
Overview
The impedance (Z) is an important parameter to characterize passive electronic
components (resistance, capacitor, inductance).
It is a complex number which can be represented by a real part (R) and an
imaginary part (X) such that Z = R + jX , or in polar form by the modulus of its
impedance and the phase shift between voltage and current: Z .
To determine an impedance it is therefore necessary to measure at least two
values (in magnitude and in phase), generally the voltage at the terminals of the
component and the current owing through it.
The LCR-meter AU2019 uses, like its predecessor, the self-balanced bridge
method with the use of a simple operational ampli er for the current/voltage
converter (I-V converter, see Figure 1).
The operational ampli ers used (AD8099 from Analog Devices) have a cut-off
frequency of approx. 200 MHz at an output voltage of 2 V p-p and have the
necessary muting control. The switches are PhotoMOS manufactured by
Panasonic with a very low product (ON resistance x output capacitance).
Another important point is the choice of the method of generating the test
frequency. It is easy and inexpensive today to use Direct Frequency Synthesis
(DDS) components, with the advantage that any frequency in the 50 Hz / 2 MHz
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range can be generated. It is, moreover, easy to generate for the synchronous
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detector a signal of the same frequency, but with variable relative phase, thanks
to a second DDS circuit synchronized to the rst.
Main Board
Input Circuit (Figure 2)
The measurement is carried out with a 5-connection con guration [1] to
minimize the in uence of the measuring cables. Connectors J4 (High Drive) and
J7 (Low Drive) supply power to the DUT (Device Under Test), while connectors J5
(High Sense) and J6 (Low Sense) allow the voltage to be measured as close as
possible to the DUT. If a bias voltage is applied, the positive appears at J4/J5.
The PhotoMOS relays U54 to U57, which allow the operational ampli ers U9 to
U12 to be connected, have an ON resistance of about 1 Ohm, so the voltage
measurement must be made at the terminals of the DUT and not with respect to
ground. This is the role of the differential ampli er built around U7A, U7B, U7C. It
must have a high common mode rejection rate (CMRR) whatever the frequency.
An adjustment is therefore necessary, rst by R31 for the low frequencies (10 kHz),
then by C44 for the high frequencies (1 MHz). The integrator built around U27B
allows an automatic offset adjustment.
According to the measurement range, one of the operational ampli ers U9 to U12
is selected: pin DIS/ at high level and ON switching of the associated PhotoMOS
(at input from U54 to U57 and at output from U50 to U53) by one of the signals
SW1 to SW4 at low level.
The signals SW5 (control of U59) and SW6 (control of U58) allow to send to the
measuring circuit either the output voltage of U7C (DUT voltage) or the output
voltage of the I-V converter (image of the DUT current).
The application of a DC bias on the DUT is made at the level of the sinusoidal
generator by an offset of its offset from 0 to 5V. As a 100 Ohms resistor is
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connected in series with the output of this generator, this will also correspond to
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a current of 0 to 50 mA if the DUT is a DC low resistance inductor. For a voltage
across a capacitor, the U7D tracker allows pre-compensation at the differential
ampli er for voltage measurement. For a current through an inductance, it is
absorbed by the direct current source formed around Q8 and Q9. The integrator
built with U27A ensures a DC voltage at the output of the I-V converter close to
0V.
To make the calibrations, precision resistors identical to those used for the I-V
converters can be connected by means of a jumper (J10 to J13).
Sine Generator (Figure 3)
The generator is built around the U24 circuit (DDS AD9834 circuit from Analog
Devices). Its 27 MHz clock is provided by the Y1 oscillator.
Its output (two signals in phase opposition) is ltered then ampli ed by U26A,
U26B and U26D. The ampli er U26C allows an offset voltage to be applied.
Without it, potentiometer R146 is used to adjust the offset of the sinusoidal signal
(measured in TP7).
The phase detector used requires a perfectly square signal, at the same
frequency as the generator, but whose relative phase can be varied. This is
obtained by the U25 circuit (also a DDS AD9834) operating at a double frequency
and followed by a fast comparator (U28) which drives a divider by 2 (U30 ip- op).
PGA (Programmable Gain Ampli er) (Figure 4)
A rst ampli er, consisting of U19 and U23, with a gain of 1, 2, 5 or 10,
compensates for the reduction of the useful signal when the amplitude of the
test signal decreases. Since its gain is not changed during a measurement cycle,
its frequency response is not very signi cant.
The next stage consists of switching on either U20 for a gain of 1, or U21 for a gain
of 3 (3.17 to be exact), or U22 for a gain of 10 (10.1).
U21 is frequency compensated by the setting of C108 and U22 by that of C51. The
calibration procedure will take into account the real response of this PGA, for
each of the frequencies used.
The relative phase of the switch signal to the sine generator allows
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measurements of the in-phase or quadrature components of the input signal to
this PSD.
The time constant for the storage capacitor is adjusted according to the
measurement frequency: eight values are possible by selecting one of the
resistors R121, R122, etc. via U70. An offset of 2V is applied to the input of U37 so
that the signal remains at most within the constant resistance range of the
analog switches (linearity problem of this PSD). When searching for the optimal
measurement conditions (choice of I-V converter and PGA gain) the fast
comparator U31 detects any signal overshoot above 2V peak, and sends this
information to the MCU (start of an interrupt routine).
Its internal oscillator (24.5 MHz) + PLL (coef cient 3) is used to have a clock
frequency of 73.5 MHz.
Connector J15 (JTAG) allows to connect a USB Debug Adapter from Silicon Labs
(e.g. RS part no. 757-0297) to ash the Bootloader in the EEPROM.
Connector J14 is used to connect the Display expansion board.
The LED D12 is used during program setup (e.g. when a button is pressed or
when the encoder is operated) and also to signal certain error conditions :
No interface connected on J14 and no communication via USB: permanent
ashing 0.5s on and 0.5s off.
Error during power supply test: in addition to the error number message,
permanent ashing 0.5s on and 1s off.
Circuits U66 and U67 allow synchronization with the sinusoidal signal of the
voltage and current measurements of the DUT.
A jumper on connector J16 informs the Bootloader of an unconditional rmware
update request.
The push button K1 (RESET) is optional (it is only used during the development
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phase).
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All these voltages are checked by program at start-up (use of the 12-bit ADC and
the multiplexer integrated in the MCU).
Note
An expansion card with a Bluetooth Low Energy (BLE) module is being tested,
identi ed by a 1 kOhm resistor connected between pin 6 (CONFIG2) of J1 and
ground.
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Project Elements
Images (7) Schematics (7)
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