DESIGN PRACTICE NOTE

FOUL TRACKS
L1-NAM-INS-030 Version: 1 Effective from: 21st May 2014

Approval

Amendment Record

Approval Date Version Description

21/05/2014 1 Initial Issue under MTM

Approving Manager: Chief Engineer Approval Date: 21/05/2014 Next Review Date: 21/05/2016
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 DESIGN PRACTICE NOTE
FOUL TRACKS
L1-NAM-INS-030 Version: 1 Effective from: 21st May 2014

Table of Contents

1. Purpose........................................................................................................................ 3

2. Scope ........................................................................................................................... 3

3. Abbreviations and Acronyms ..................................................................................... 3

4. Definitions.................................................................................................................... 3

5. Background ................................................................................................................. 4

6. The Issue ..................................................................................................................... 4

6.1 VRIOGS 012.0 Section 4.1.1 ...................................................................................... 4
6.2 VRIOGS 012.0 Section 4.1.6.4 – Table 6 ................................................................... 4
6.3 VRIOGS 012.0 Section 4.1.8 ...................................................................................... 4
6.4 VRIOGS 012.0 Section 4.1.10.2 ................................................................................. 4
6.5 VRIOGS 012.0 Section 4.1.10.3 ................................................................................. 5
6.6 VRIOGS 012.0 Section 4.1.10.3 ................................................................................. 5
6.7 VRIOGS 012.1 Section 6.10.5(d)................................................................................ 5
6.8 VRIOGS 012.1 Section 6.10.9 .................................................................................... 5

7. The Requirement ......................................................................................................... 5

7.1 Application of Foul Tracks within Point Controls ................................................... 5
7.2 Application of Foul Tracks within Signal Controls ................................................. 5

8. Responsibilities ........................................................................................................... 6

9. References and Legislation ........................................................................................ 6

Approving Manager: Chief Engineer Approval Date: 21/05/2014 Next Review Date: 21/05/2016
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 DESIGN PRACTICE NOTE
FOUL TRACKS
L1-NAM-INS-030 Version: 1 Effective from: 21st May 2014

1. Purpose
To describe foul track principles to be implemented during development of signalling
control tables.
This document supplements and clarifies the requirements of the following VRIOG
Standards in respect to the application of foul tracks in the controls of Signals and Points;
a) 012.0 Section 4.1.1
b) 012.0 Section 4.1.6.4 table 6
c) 012.0 Section 4.1.8
d) 012.0 Section 4.1.10.2
e) 012.0 Section 4.1.10.3
f) 012.0 Section 4.1.11.3
g) 012.1 Section 6.10.5 (d)
h) 012.1 Section 6.10.9 (a)
i) 012.1 Section 6.10.9 (b)

2. Scope
This DPN is aimed at all projects modifying existing and new signalling interlockings.

3. Abbreviations and Acronyms

DPN Design Practice Note
MTM Metro Trains Melbourne
RRL Regional Rail Link
VRIOGS Victorian Rail Industry Operators Group Standards

4. Definitions
For the purpose of this DPN the following terms are defined as follows;
Fouling Route

A fouling route is a route that contains foul track circuits

Foul Track Circuit

When a track circuit is not in the direct line of a signals route (block/overlap) but one of its
extremities is not at the required clearance point for that route then that track circuit is (a)
foul (track) of the route.

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FOUL TRACKS
L1-NAM-INS-030 Version: 1 Effective from: 21st May 2014

5. Background
Foul track circuits have been treated inconsistently during the design of control tables due
to their ommission from or misinterpretation of their application requirements within the
above mentioned VRIOG standards.
Foul track requirements in the control table design has therefore relied on individual
designer’s knowledge and reasoning as to the application requirements in Signal and Point
controls throughout the design of the RRL project.
A clear understanding of what is meant by the terminology “foul” and a general
understanding of their application in Signal and Point controls is therefore required to be
provided to ensure foul tracks are treated consistently throughout the MTM network going
forward.

6. The Issue
The current VRIOGS suite of documents does not provide a clear direction of or have been
misinterpreted in respect to MTM's requirements in relation to the application of foul tracks
in the controls of Signals and Points. The VRIOG references in respect to Signal and Point
controls are as follows;

6.1 VRIOGS 012.0 Section 4.1.1

This section states; to display a normal speed or medium speed proceed aspect on a
signal the following conditions must be satisfied;
Continuously detect that the block is unoccupied
Continuously detect that the overlap is unoccupied
It further states; to display a low speed aspect on a signal;
It is not required to detect the block is unoccupied
It is not required to detect the overlap unoccupied
There is no reference as to the treatment of foul tracks

6.2 VRIOGS 012.0 Section 4.1.6.4 – Table 6

This section states for a Dwarf Signal, Green – Clear Low Speed, ‘The Line is Clear’
Again, no reference as to the treatment of foul tracks

6.3 VRIOGS 012.0 Section 4.1.8

This section caters for Dwarf Signals and there is no mention of tracks in block, overlap or
foul.

6.4 VRIOGS 012.0 Section 4.1.10.2

This section states “for a low speed signal to a terminal station or loop line, the clearing of
the ‘running’ aspect would normally be conditioned upon the tracks in the route being
detected unoccupied”
No reference to block, overlap or foul is made.

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FOUL TRACKS
L1-NAM-INS-030 Version: 1 Effective from: 21st May 2014

6.5 VRIOGS 012.0 Section 4.1.10.3

This section states “the conditions required to allow a home signal to display a normal or
medium speed proceed aspect are;
The block and overlap are continuously detected clear of trains. This requires that
all track circuits in the block and overlap of the signal are detected as energised in
the signal controls
The low speed signal does not usually require the block and overlap clear of
trains”
There is no reference as to the treatment of foul tracks

6.6 VRIOGS 012.0 Section 4.1.10.3

This section states “the conditions required to allow a controlled automatic signal to display
a proceed aspect are;
The block and overlap are continuously detected clear of trains. This requires that
all track circuits in the block and overlap of the signal are detected as energised in
the signal controls”
There is no reference as to the treatment of foul tracks

6.7 VRIOGS 012.1 Section 6.10.5(d)

This section states “Points shall be unconditionally locked by all fouling track circuits”

6.8 VRIOGS 012.1 Section 6.10.9

The design of signal controls require the following conditions to be implemented or
detected before a proceed aspect can be displayed
a) Low Speed – No mention of track circuits in block, overlap or foul
b) Normal and Medium Speed Signals
i. All track sections in the block section, overlap and fouling sections unoccupied

7. The Requirement

7.1 Application of Foul Tracks within Point Controls

Foul track circuit(s) shall be proved clear in the controls for moving the points to a position
that will allow a fouling route to be set unless the foul track circuit(s) control can be
mitigated against (conditioned) by the lie of other points.
In this instance, the other points shall be proved to be set and detected at the time the
points required to be moved are called if the foul track is occupied.

7.2 Application of Foul Tracks within Signal Controls

Normal, Medium, Low Speed and Clear Low Speed proceed aspects shall be inhibited
when the fouling track(s) are not proved clear unless mitigated against (conditioned) by the
lie of another set of points. In this instance the points shall be proved to be set and
detected continuously in the signals aspect controls for as long as the fouling track remains
occupied.

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 DESIGN PRACTICE NOTE
FOUL TRACKS
L1-NAM-INS-030 Version: 1 Effective from: 21st May 2014

8. Responsibilities
All planned works to cater for this design requirement.

9. References and Legislation

This document is to supplement and clearly define MTM’s requirements in relation to
VRIOGS 12.0 and 12.1.

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