MINISTRY OF EDUCATION AND TRAINING

HO CHI MINH CITY

UNIVERSITY OF TECHNOLOGY AND EDUCATION

DO DUC TRI

STUDY ON T-TYPE THREE-LEVEL THREE-PHASE INVERTER

WITH BOOST VOLTAGE ABILITY AND FAULT TOLERANCE

SUMMARY OF THESIS

MAJOR: ELECTRONIC ENGINEERING

CODE: 92520203

Ho Chi Minh City, October 2020

1
 THE DISSERTATION SUMMITED TO

HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION

Advisor 1: TS. NGUYỄN MINH KHAI

Advisor 2: TS. QUÁCH THANH HẢI

A dissertation submitted to

THE COMMITTEE ON GRADUATE STUDIES

OF HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION

October 2020

2
3
 CONTRIBUTIONS OF THE DISSERTATION

In recent years, the traditional three-phase three-level T-type inverter topology

has been used very commonly compared to the two-level inverter topology.
Because the traditional three-phase three-level T-type inverter has many
advantages such as better power quality, smaller output AC filter requirement,
lower voltage stress across the inverter switches, and higher output voltage
compared to the two-level inverter. However, the traditional three-phase three-
level T-type inverter is only a buck converter. On the other hand, to create a high
output voltage from a low input voltage, a DC-DC boost converter needs to be
installed in front of the inverter which the traditional three-level T-type inverter
will work as a two-stage converter. Besides, a shoot-through mode, where both the
upper and lower switches in the same leg can be switched on at the same time, is
forbidden in the traditional inverter. The three-level Z-source inverter topology,
known as a single-stage power converter with a buck-boost capability and ST
immune, is proposed to overcome the limitation of the traditional three-level
inverter. However, the disadvantage of this topology is to have the discontinuous
input current which results in the limitation of applications in PV and fuel cell
systems.
To overcome disadvantages of the three-level Z-source inverters, the three-
level quasi Z-source inverters are proposed. The quasi Z-source inverter topology
has some advantages such as low voltage stress on power switches and continuous
input current. However, the three-level quasi Z-source inverter topology uses a
large number of passive components that increase the weight, size, and loss of the
inverter system.
To improve the aforementioned disadvantages, the three-level quasi switched
boost T-type inverter topology and PWM algorithm is proposed with the following
features:
˗ The input current ripple is reduced compared with the similar topology;
˗ High voltage gain compared with the similar topology;
˗ High modulation index compared with the similar topology.
During its operation, the inverter generates the common-mode voltage (CMV),
which causes a lot of disadvantage problems for inverter, such as bearing currents

4
and shaft voltage in motor drives applications as well as electromagnetic
interference.
To address the common-mode voltage problems of the three-level quasi
switched boost T-type inverter topology, the PWM algorithm with the ability to
eliminate common-mode voltage is proposed.
The stability and reliability of the inverters are important in power distribution
systems such as UPS, high-power medical instruments, and grid-connected
renewable energy conversion systems. In fact, switching device faults are usually
classified as either a short-circuit switch fault or an open-circuit switch fault. The
combination of the fast fuses connected in series with the power switch legs of the
inverter results in converting the short-circuit switch fault into the open-circuit
switch fault.
To ensure the stability and reliability of the three-level quasi switched boost T-
type inverter topology, the PWM algorithm is proposed with the following
features:
˗ Improving control parameters in comparison with the similar topology;
˗ Having the ability to operate in normal and fault modes;
˗ Reducing voltage stress in power semiconductors in comparison with
the similar topology.
In addition, a simulation using PSIM software and a real circuit prototype is
implemented to verify the operating principle of the three-level quasi switched
boost T-type inverter topology with the ability to eliminate common-mode voltage
and to tolerate open-circuit fault of the power switches.

5
 Chapter 1: Overview of boost inverter, fault tolerence ability
and common mode voltage elminate
1. The process of developing renewable energy sources.
Renewable energy is developing strongly because of its sustainability and
environmental friendliness while the application potential is enormous. In recent
years, renewable energy in the world has a significant growth compared with the
growth of energy from wind power each year. Since countries around the world
have focused on exploiting solar energy, the cost of solar cells is decreasing,
which stimulates Asian countries have their plans for the near future. For these
reasons, solar energy is developing strongly as shown in Figure 1.1.

a) b)
Figure 1.1. The world's wind and solar power investment costs
In 2016, the National Assembly of Vietnam canceled the nuclear power
project because of many reasons, which related to environment and financial. In
addition, the traditional energy sources as hydropower and thermal power are
gradually running out, which make a large contribution to the national power
system. So that, finding new sources of energy that can guarantee to making up the
lack of current and future electrical power is an urgent need. As a result,
notification No. 16/2017 / TT-BCT and No. 05/2019 / TT-BCT were issued by
the Ministry of Industry and Trade that announced preferentical polices and
encourage development of solar power projects in Vietnam.
2. Overview of voltage inverter
In recent years, Voltage source inverters (VSIs) play a very important role in
power distribution systems because they convert DC power into AC power sources
for grid connection. Multi-level VSIs have many advantages such as better power
quality, small output filter requirement, low voltage stress across the inverter
switches, higher voltage and power capacities, and lower electromagnetic
interference (EMI). In actual fact, the conventional VSIs provide buck DC–AC
power conversion because the peak AC output voltage cannot be higher than the
DC source voltage. In addition, a shoot-through (ST) mode, where both power
switches in the same leg can be switched on at the same time, is forbidden in the
inverters because it may cause a short circuit across the DC-link capacitors and
destroy the devices.

6
 The first Z source inverter was presented in 2002-2003 by F. Z. Peng to
overcome the limitations of conventional inverters. However, the Z source inverter
configuration still has some disadvantages such as discontinuous input current as
well as high voltage stress across the capacitor. To improve the input current and
reduce the voltage stress across the passive elements, a quasi Z source (qZSI)
network is proposed. However, the Z-source network and the qZSI network, with
using a large number of passive elements, enlarges the volume, weight, and price
of the inverter. Recently, many researchers have developed the quasi-switched
boost inverter (qSBIs) to replace the Z-source network and the qZSI network,
because they used a lower number of passive components that the qSBIs have the
main features such as ST immunity, single-stage power conversion, and buck-
boost voltage capability.
3. Overview of common-mode elminate technique
During operation, the inverter generates the common-mode voltage (CMV),
which causes a lot of problems for the inverter such as bearing currents and shaft
voltage in motor drives applications or electromagnetic interference. The results
showed that, it will reduce the life of the inductor motor or affect other electronic
devices operating near the inverter. A technique to eliminate CMV applied to five-
level inverter based on SVM and sine PWM. However, the above method still has
some disadvantages such as reduce common mode voltage or common mode
eliminate but these converters must operate buck converter.
4. Overview of voltage inverter with fault-tolerant ability
Stability and reliability of inverters are important in power distribution
systems such as UPS, high-power medical instruments, and grid-connected
renewable energy conversion systems. In fact, power switches faults are usually
classified as either a SCS fault or an OCS fault. The fault-tolerant TL qZST 2I is
operated by only changing the modulation scheme after the semiconductor fault
without the need of redundant legs or complex calculations. Moreover, by using
quasi switched boost topology, the converter can operate when a T-Type power
open-circuit switch fault by changing the modulation scheme.

7
Chapter 2: Mathematical analysis of voltage inverter, common
mode voltage, and power open-circuit switch fault-tolerant
ability
2.1. Theoretical basis of three-level T-Type quasi switched boost inverter
2.1.1. Traditional inverter topology
S1a S1b S1c
Vc1 VPN S2a
S2b 3-phase
Vdc S3a
filter &
S2c
S3b load
Vc2
S3c
S4a S4b S4c

Figure 2.1: Traditional three-phase T-Type inverter.

M VPN
v x   M VC . (2.1)
2
2.1.2. Z-source inverter
L1

D1 S1a S1b S1c

Vdc C1 C2 S2a
DC
S2b 3-phase
S3a
filter &
VPN S2c
Vdc S3b load
DC S3c
D2 S4a S4b S4c

L2

Figure 2.2: three-level Z-source T-Type inverter.

The output voltage of three-level Z-source T-Type inverter is defined as
M  VPN M
v x   Vdc (2.2)
2 1  2 D0
2.1.3. Three-level quasi Z-source T-Type inverter (3L-qZST 2I)
L1 C1 L3
D1 S1a S1b S1c

C2 S2a
S2b 3-phase
Vdc S3a
filter &
S2c
S3b load
C3 VPN S3c
L2 D2 L4 S4a S4b S4c
C4

Figure 2.3: Three-level quasi Z-source T-Type inverter (3L-qZST2I).

The output voltage of three-level quasi Z-source T-Type inverter is defined as
M VPN M
v x   Vdc (2.3)
2 2(1  2 D0 )
2.1.4. Three-level quasi switched boost NPC inverter topology.
L1 D1

S1a S1b S1c

Vdc1 + S1 C1
- - +
S2a S2b S2c
D2 D11 D21 D31
n A Three
phase
S3a B S3b C
S3c load
D3 D12 D22 D32
C2
+ -
Vdc2 + S4a S4b S4c
- S2
L2 D4

Figure 2.4: Three-level quasi switched boost NPC inverter topology

8
 The output voltage of three-level quasi switched boost NPC inverter topology
is defined according to the equation (2.4):
M  VPN M .Vdc
v x   M  VC  (2.4)
2  1  2 D0 
2.2 Theoretical basis of space vector modulation technique
Sector II
Vβ
V15 V14
NPN OPN V8 PPN

Sector I
V2 3
Sector III V9 OPO V3 PPO V7
NPO NON OON PON
Vref
2
1 4
V16 V4 V1 V13 Vα
PNN PPP θ POO
NPP NOO NNN OOO ONN PNN
V0

V10 OOP POP V12

Sector IV NOP NNO V5 V6 ONO PNO Sector VI

NNP PNP
V17 V11 ONP V18
Sector V

Figure 2.5. Space vector diagram of three-phase three-level inverter topology

 V
Vref  M . PN .e j (2.5)
3
   
Vref .Ts  V1.Ta  V2 .Tb  V7 .Tc (2.6)
ta  TS  2mTS sin( )

tb  2mTS sin( / 3   )  TS (2.7)
t  T  2mT sin( / 3   )
c S S

2.3 Theoretical basis of boost inverter with fault-tolerant ability

Figure 2.6 system not only operate a single-stage inverter but also has ability
to buck-boost to compensate for the amplitude of faulty phase.
C1
L1 L2 P
S1a S1b S1c
C2 S2a La Ra
A
Vi S2b Lb Rb
B G
O Lc
S2c C Rc Rc Rc
C3 Ca Cb Cc
S3a S3b S3c

L4 L3 N S2x G

C4

Figure 2.6: Three-phase quasi Z-source inverter operate under fault condition
As shown in Figure 2.7 under normal operation the phase angle between phase
B and phase C is 1200. When the fault occurs at phase A, the voltage of Va is zero,
at this time the output line voltage remains unchanged, phase angle of phase B and
phase C is changed by an angle of 600 as shown in Figure 2.7 (b). Figure 2.8
capacitors voltage VC1 and VC2 is defined according to the equation (2.8)
Vdc
VC = VC1 = VC 2 =
2 - 3D0 - d
(2.8)

9
 Vc Vc
Vc'
Vca Vca
'
π
2π 6
3 Va Va' Va
Vbc
o Vbc
' o
π
6
Vab Vab
'
Vb'
Vb Vb
(a) (b)
Vc' Vc
Vc Vca
'
Vbc
'
π
Va' Va
6 Vc' o
π Vab
' π
6 Va 6
Vb' o π Vca
'
6 Va'
Vb Vbc
'
Vab
'
Vb'
Vb
(c) (d)

Fugure 2.7 Reference voltage vectors in (a) normal mode, (b) phase-A fault, (c)
phase-B fault, and (d) phase-C fault.
T1 D1 P S1a S1b S1c
LB C1 Lf
S2a iA R A
iL D2 VC1 A
S2b iB R B
O B
Vdc G
S2c iC R C
D3 VC2 C
C2
S3a S3b S3c Cf
T2
D4 N
S2x (x = a, b, c)
Figure 2.8 3L-qSBT2I topology
Figure 2.7 and Figure 2.8 output peak voltage in open-circuit faulure at switch
S1x condition is defined
M  VPN M VC M/ 3
v x    Vdc . (2.9)
2 3 3 2  3D0  d
From equation (2.9) it can be seen that, output voltage will depend on three
control parameters are M, D0 and d. To compensate for the output voltage under
fault condition, the researcher can be changed by these parameters.

Conlusion:
Traditional inverter topology has simple algorithm. However, in this topology,
there is still a shoot through immunity problem of both power switches in the same
leg of inverter. The Z-source topology, there are two types of configuration such
as a) configuration using passive elements (L, C) to boost and b) configuration
using active elements (D, Sw) to boost. I can seen that, when using the active
element configuration, this configuration reduces many passive elements as well
as the control algorithm is more flexible than traditional algorithm (control
parameters M and D), depending on the output target selection criteria. Therefor,
in this thesis, the author will focus on studying three-level quasi switched boost T-
Type inverter topology.

10
 Chapter 3: Three-level quasi switched boost T-Type inverter
In chapter 2, the author has analyzed and evaluated the topologies and
algorithm of traditional inverters as well as Z-source inverter. However, these
three-level inverter topologies have many disadvantages such as current ripple of
high boost inductor, low voltage gain and modulation index compared to similar
topology. As a result, in this chapter , the author will present three-level quasi
switched boost T-Type inverter with many advantages such as reducing of current
ripple of boost inductor, high voltage gain, and highest possible modulation index
compared to similar topology.
3.1. Three-level quasi switched boost T-Type inverter topology (3L-qSBT 2I)
3.1.1 Topology and principle of 3L-qSBT2I
T1 P
D1 S1a S1b S1c
S3a Lf iA R A
LB D2 CP A
S3b iB R B
iL S2a B
O G
S3c iC R C
Vdc CN S2b C
D3
S2c
T2 D4 S4a S4b S4c Cf
N
Hình 3.1: Cấu hình của 3L-qSBT2I
3.1.2 Operating principle of 3L-qSBT2I
Operating principle of curcuit based on this PWM control algrithm is
presented in Table 3.1 and Figure 3.3.
T1 D1 +Vc T1 D1 +Vc T1 D1 +Vc
LB LB LB
iL D2 C1 iL D2 C1 iL D2 C1
Vdc O Vdc O Vdc O
D3 C2 D3 C2 C2
D3
T2 D4 T2 D4 T2
-Vc -Vc D4 -Vc
(a) (b) (c)

T1 D1 +Vc T1 D1 +Vc
LB LB
iL D2 C1 iL D2 C1
Vdc O Vdc O
D3 C2 C2
D3
T2 D4 -Vc T2 -Vc
D4

(d) (e)

Figure 3.2: Modes of 3L-qSBT2I. (a) non-shoot through mode 1 (NST) 1, (b) NST
2, (c) NST 3, (d) NST 4 and (e) shoot-through mode (ST).

The frequency of the inductor current IL in Fig. 3 can be derived as:

fL = 4 / T = 4 fs , (3.1)
As shown above, the high-frequency current-ripple of inductor of 3L-qSBT2I
is significatly reduced compared with traditional inverter. This is one of the three
advantages proposed in chapter 3 of the thesis.

11
 T 900 vtri1 vtri2
1 vref_a
VST
Vcon1
1–VST
0
t
-VST Vcon2
-1 T/4 -vref_a iL
¨ IL

0 d1T/2
T1 t
0 D0T/2
t
T2 D0T/2
0 d2T/2
S1a t

0
S2a t
0
t
S3a
0
S4a t
0
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t
Trạng thái ngắn mạch

Figure 3.3: PWM control strategy for the three-level qSBT2I for phase-a
Switch
3.2. Steady-state analysis for 3L-qSBT2I
Applying the volt–second balance principle to the inductor LB and the charge–
second balance principle to the capacitors C1 and C2, the capacitor voltages and
inductor current can be calculated as
ìï 2Vdc
ïï VC = VC1 = VC 2 =
ïï 4 - 6 D 0 - d1 - d 2
ïí
ïï 4 ( 1- D0 )
(3.2)
ïï I L = I load .
ïïî 4 - 6 D0 - d1 - d 2
The peak voltage of output is determined as
M  VPN 2M
v x   M  VC  Vdc . (3.3)
2 4  6 D0  d1  d 2
The boost factor of 3L-qSBT2I is determined
VPN 2VC 4
B   . (3.4)
Vdc Vdc 4  6 D0  d1  d 2
As shown in Fig. 3.3, Vcon1 and Vcon2 vary in the range of [1–VST, VST] and
[−VST, VST–1], respectively. Therefore d1 and d2 are changed from D0 to 1–D0 as
D0  d1 , d 2  1  D0 . (3.5)
2
When d1 = d2 = D0, the minimum boost factor of the 3L qSBT I is defined
Bmin  1/  1  2 D0  ; D0  0.5. (3.6)
When d1 = d2 = 1 – D0, the maximum boost factor of the 3LqSBT2I is
determined
Bmax  2 /  1  2 D0   2 Bmin . (3.7)
2
Voltage gain of 3L-qSBT I is defined:
v x
G (3.8)
Vdc / 2
 M
Gmin  M  Bmin  2M  1
 (3.9)
G  M  B  2 M ; M  0.5.
 max max
2M  1

12
 In the traditional impedance source inverters, the modulation index is usually
selected according to the minimum input voltage, and is kept fixed, while the
control parameter is the ST duty cycle D0. As a result, the selected modulation
index in the conventional inverters is not optimal at the minimum ST duty cycle
because M is less than (1 – D0). In the 3L qSBT2I with the proposed PWM control
method, both M and D0 are set to a fixed value, and M = 1 – D 0. Then, the control
parameters of the 3L qSBT2I are d1 and d2. Therefore, the selected modulation
index in tradtional inverters such as three-level impedance network inverters is
lower than 3L-qSBT2I. Therefor, this is also one of three new ideas in chapter 3 of
the thesis to improve the highest modulation index possible.

Figure 3.4: Reducing percentage of the inductor current ripple in the

3L-qSBT2I compared to traditional inverter.
3.3. DC-link voltage regulator and Capacitor Voltage Balance Control for 3L-
qSBT2I
1
VPN_ref err d1 Vcon1
PID
PID 2 h1
VC1 Limiter
vtri2
Khối điều khiển điện áp DC-link
h2
err Δd d2 Vcon2
PID
PID 2
VC2 Limiter 1
Khối điều khiển cân bằng điện áp tụ

Hình 3.5: DC-link voltage controller and capacitor voltage balance controller for
the 3L qSBT2I.
3.4. Simulation and experimental results
3.4.1. Simulation results
Table 3.1: Parameters for simulation and experiment.
Parameter/ Component Value
Input voltage Vdc 90 – 180 V
Desired output voltage Vph 111 Vrms
Output frequency fo 50 Hz
Switching frequency fs 5 kHz
ST duty ratio and modulation D0
0.3
index
Modolation index M 0.7
Boost inductor LB 3 mH/ 20 A
Capacitor C1 = C2 2200 F/400 V
Three-phase LC filter Lf và Cf 3 mH and 10 F
Three-phase resistor load Rload 40Ω

13
 (a) (b)
Figure 3.6: Simulation results for qSBT2I when Vdc = 180 V and d1 = d2 = 0.3.

(a) (b)
2
Figure 3.7: Simulation results for qSBT I when Vdc = 90 V and d1 = d2 = 0.7.
3.4.2. Experimental results
A 1-kW prototype based on the DSP TMS320F28335 microcontroller is built
in the laboratory to verify the effectiveness of the 3L qSBT 2I with the proposed
PWM control technique.

Figure 3.8: A laboratory prototype of proposed 3L-qSBT2I topology.

14
 (a) (b)

(c) (d)

(e) (f)
2
Figure 3.9 Experimental results for 3L-qSBT I when Vdc = 180 V và d1 = d2 = 0.3

(a) (b)

(c) (d)

15
 (e) (f)
2
Figure 3.10 Experimental results for 3L-qSBT I when Vdc = 90 V và d1 = d2 = 0.7.
In Fig. 3.9(a) and Fig. 3.10(a), the top waveform is the output phase voltage
VAG and the bottom waveform is the pole voltage VAO. In Fig. 3.9(b) and Fig.
3.10(b), the top waveform is the output line-to-line voltage VAB and the bottom
waveform is the load current IR. In Fig. 3.9(c) and Fig. 3.10(c), the waveforms
from the top to the bottom are the ST control signal, VS0 for the T-type circuit
switches, and the VS90, VT1 and VT2 control signals. In Fig. 3.9(d) and Fig. 3.10(d),
the waveforms from the top to the bottom are the inductor current, diode VD1
voltage, diode VD4 voltage, and dc-link voltage. In Fig. 3.9(e) and Fig. 3.10(e), the
waveforms from the top to the bottom are the input voltage, capacitor C2 voltage,
capacitor C1 voltage, and input current. Fig. 3.9(f) and Fig. 3.10(f) show the
harmonics of the load current. In Fig. 3.9 and Fig. 3.10, the input and output
currents are measured through a current transducer LEM- LA 25-P.

Conlusion:
Based on the analysis of boost inverter and researched on the boost inverter in
Viet Nam as well as in the world, the author has proposed single-stage boost
inverter topology that has low power and reducing power switches. Above single-
stage boost inverter is proposed with suitable control technique as:
a) Reduced input current-ripple;
b) Achieved high voltage gain compared to similar topology;
c) Achieved highest possible modulation index compared to similar
topology.

16
 Chapter 4: Space vector modulation technique for three-level
T-Type quasi switched boost inverter with ability common
mode elimination
In chapter 3, the author has presented quasi-switch boost three-level T-type
inverter topology which has some advantages such as: reducing inductor current
ripple, high voltage gain and enable to operate with highest modulation index as
high as possible. However, during operation, the inverter generates the common-
mode voltage (CMV), which is the main reason leading some problems such as:
leakage current, shaft voltage in some motor drive applications as well as
Electromagnetic interference (EMI). Therefore, in section 4 introduces the control
method which eliminates the CMV based on the space vector PWM technique.
Furthermore, this scheme also reduces inductor current ripple as well as operating
with highest modulation index.
4.1. Operating principle of 3L-qSBT2I to eliminate CMV.
T1 D1 P S1a S1b S1c
LB C1 Lf
S2a iA RA
iL D2 VC1 A
S2b iB RB
O B G
Vdc iC R C
D3 VC2 S2c C

C2
S3a S3b S3c Cf
T2
D4 N
S2x (x = a, b, c)
Figure 4.1 3L-qSBT2I topology
T1 D1 +Vc T1 D1 +Vc T1 D1 +Vc
LB LB LB
iL D2 C1 iL D2 C1 iL D2 C1
Vdc O Vdc O Vdc O
D3 C2 D3 C2 C2
D3
T2 D4 T2 D4 T2
-Vc -Vc D4 -Vc
(a) (b) (c)

T1 D1 +Vc T1 D1
LB LB
iL D2 C1 iL D2 C1
Vdc O Vdc O
D3 C2 C2
D3
T2 D4 -Vc T2 D4

(d) (e)
Figure 4.2: Modes of 3L-qSBT2I. (a) non-shoot through mode 1 (NST) 1, (b) NST
2, (c) NST 3, (d) NST 4 and (e) shoot-through mode (ST).
4.1.1. Operating principle of 3L-qSBT2I.
4.1.1.1. NST mode.
In NST1, switch T1 is triggered on, while switch T2 is triggered off, as shown
in Figure 4.2 (a). Diode D1 is reserved bias, while diode D2, D3 và D4 forward bias.
Inductor LB and capacitor C1 are discharged, while capacitor C2 is charged.
17
 In NST2, switch T1 is turned off, while switch T2 is triggered on, as shown in
Figure 4.2 (b). Diode D1, D2, và D3 are forward bias, while diode D4 is reserved
bias. Inductor LB and capacitor C2 are discharged, while capacitor C1 is charged.
In NST3, switches T1 và T2 are triggered on, as shown in Figure 4.2 (c). Diode
D1, and D4 are reserved bias, while diodes D2 and D3 are forward bias. Inductor LB
is stored energy, while capacitor C1 and C2 are discharged. The time interval of
this mode is D0.T, where D0 is ST duty ratio in each switching period T.
In NST4, switches T1 and T2 are turned off, as shown in Figure 4.2 (d). Diodes
D1, D2, D3 and D4 are forward bias. Capacitors C1 and C2 is stored energy from dc
input source Vdc. Whereas inductor LB transfer energy from input source to the
main circuit, while capacitor C1 and C2 are discharged. The time interval of this
mode is D0.T, with D0 is ST duty ratio in each switching period T.
4.1.1.2 ST mode (ST)
In ST mode, switches S1x-S3x of inverter leg are triggered on simultaneously,
while switches T1 and T2 is turned off, as shown in Figure 4.2 (e).
4.1.2. Steady-state analysis for 3L-qSBT2I
M .VC M Vdc
Vx , RMS   . . (4.1)
2 2 2  3D0  d
4.1.3. The space vector control method 3L-qSBT 2I to eliminate common-mode
voltage.
VAO  VBO  VCO
VCMV  VGO  . (4.2)
3
During operation, ST state is inserted to zero vector in order not to affect the
output voltage as well as ensuring the boost capability.
Vβ
V3 [OPN]

Sector III Sector II

V4 V2
[NPO] [PON]

Vref
[PPP] V0 Sector I
Sector IV [OOO] θ
[NNN] Vα

V5 V1
[NOP] [PNO]

Sector V Sector VI
V6 [ONP]

Figure 4.3: Space vector diagram of 3LT2I

The Switching sequence for sector I is selected as: [OOO]-[PON]-[PNO]-
[OOO]-[PNO]-[PON]-[OOO].
In order to achieve ST state, all switches of inverter leg are triggered on
simultaneously. As a result, the output voltage is zero which is the same as zero
18
vector. Therefore, ST vector is added to vector zero, thus vector zero is changed
which is expressed as equation (4.3):
  
V0.T0  V0T0  VST .TST
 . (4.3)
T0  T0  TST  T0  D0TS
In order to obtain the goal of the thesis, author combined the ST vector and the
switching sequence as shown in Figure Hình 4.3. The switching sequence is
rewritten as: [FFF]-[OOO]-[PON]-[PNO]-[OOO]-[FFF]-[OOO]-[PNO]-[PON]-
[OOO]-[FFF]. Where [FFF] is ST vector.
IL
Δ IL

0
TS
dTs/2
S1
0
S2 TST
0
D0Ts/2
A Ts/4

0 [FFF]
B
0

C
0

T0/4 TM/2 TL/2 T0/2 TL/2 TM/2 T0/4

[OOO] [PON] [PNO] [OOO] [PNO] [PON] [OOO]

Figure 4.4: Switching sequence and control signal of S1 and S2 for 3L-qSBT2I-
ECMV
4.2. Simulation and experimental results of 3L-qSBT2I-ECMV.
4.2.1. Simulation results.
Table 4.1: Parameters for simulation and experiment of 3L-qSBT2I-ECMV.
Parameter/ Components Values
DC input voltage Vdc 150 V
Desired output voltage VXG 110 Vrms
Output frequency fo 50 Hz
Switching frequency fs 5 kHz
ST duty ratio and modulation index D 0, M 0.2, 0.8
Boost inductor LB 3 mH/ 20 A, 0.12 Ω
Capacitors C1 = C2 2200 F, 44 mΩ
Three-phase LC filter Lf and Cf 3 mH and 10 F
Three-phase resistor load Rload 40Ω

19
 Figure 4.5: Simulation results input voltage (Vdc), capacitor voltages (VC1 và VC2)
and inductor current (IL) of 3L-qSBT2I-ECMV.
Figure 4.5 from top to bottom: input voltage (Vdc), capacitor voltages (VC1 and
VC2) and inductor current (IL) of 3L-qSBT2I-ECMV. The simulation is conducted
with the parameter shown in Table 4.1. As a result, the capacitor voltage is
boosted to 194.8 V based on equation (4.1) and the simulation results of VC1 và
VC2 are 196 V and 193 V. The peak value of DC-link voltage (the sum of capacitor
voltages C1 and C2) is measured as 389 V. the average value of input current
(inductor current) is 6.1 A as shown in Figure 4.5. In one period of output voltage
the maximum and minimum value of input current are 7 A and 5.2 A.

Figure 4.6: Simulation results of DC-link voltage, output phase voltage (VAG) and
CMV of (a) method 1, (b) method 2 and (c) 3L-qSBT2I-ECMV method.
As shown in Figure 4.6, the magnitude of CMV of method 1 is highest which is
VC/3 as 130 V. The magnitude of CMV of method 2 is varied from +VC/3 (65 V)
to -VC/3 (-65 V). The value of 3L-qSBT2I-ECMV method is approximately 0V.

Figure 4.7: Simulation results of output line-line voltage (VAB), output load voltage
(VRA) and output load current (IA) of (a) method 1, (b) method 2 and (c) 3L-
qSBT2I-ECMV method.
20
 Figure 4.7 shows the simulation results of output line-line voltage (VAB), output
load voltage (VRA) and output load current (IA). The THD value of output line-line
voltage of these method are 42%, 67.3%, and 77.1%.
4.2.2. Experimental results.

Figure 4.8: experimental results of dc input voltage (Vdc), capacitor voltages C1 and
C2 (VC1 and VC2) and inductor current of 3L-qSBT2I-ECMV.

Figure 4.9: Experimental results of DC-link voltage, output phase voltage (VAG)
and CMV of (a) method 1, (b) method 2 and (c) 3L-qSBT2I-ECMV method.
As shown in Figure 4.9, 3L-qSBT2I-ECMV method reduces 91.5% and 85.7%
compared to method 1 and method 2.

Figure 4.10: Experimental results of output line-line voltage (VAB), output load
voltage (VRA) and output load current (IA) of (a) method 1, (b) method 2 and (c) 3L-
qSBT2I-ECMV method.
21
 Figure 4.10 the RMS value of output load voltage and output load current for
thses method are the same as each other which are 105 VRMS, 104 VRMS và 104 VRMS.

Figure 4.11: Experimental results of FFT analysis of output phase voltage (VAG).
(a) method 1, (b) method 2 and (c) 3L-qSBT2I-ECMV method.

Figure 4.12: Experimental results of FFT analysis of output load current (IAG). (a)
method 1, (b) method 2 and (c) 3L-qSBT2I-ECMV method.
Figure 4.11 and Figure 4.12 shows the FFT analysis of output phase voltage
(VAG) and output load current (IAG) for these methods. FFT spectrum of VAG and IA
are considered, the magnitude of first harmonic of output phase voltage and output
load current of these methods are the same as each other which are 104.5 V and
2.55 A.
Conclusion:
Based on the analysis of 3L-qSBT2I-ECMV and researched on 3L-qSBT2I-
ECMV, author has proposed medium power 3L-qSBT2I-ECMV topology, with
eliminating CMV capability. Although the THD value is higher than method 1 and
2, however, the THD value as 3.3% is obtained the standard 5% [87].

22
 Chapter 5: Three-level quasi switched boost T-Type inverter
with open-curcuit power switches fault-tolerant ability
In chapter 3, the author presented quasi-switch boost three-level T-type
inverter topology which has some benefits such as: reducing current ripple of input
power source and using highest modulation index compared to other single-state
converter. In chapter 4, author has introduced quasi-switch boost three-level T-
type inverter topology which has some advantages such as the space vector control
method eliminating the common-mode voltage. However, stability and reliability
of the converter in power electronic system is very important such as:
uninterruptable power supply system, high capacity medical system and grid
connection system. Therefore, in chapter 5, author introduces control method
which handles the open circuit fault of any switches of the inverter. This control
method not only handle open-circuit fault of inverter switches, but also handle the
open-circuit fault of impedance active switches. Moreover, the parameters used in
simulation and experiment have been improved to reduce voltage stress on power
devices in normal and post fault operation. This method does not require any extra
power component which reduces the cost and size of system.
5.1. Operation principle and fault-tolerant strategy for 3L-qSBT 2I.
T1 D1 P S1a S1b S1c
LB C1 Lf
S2a iA RA
iL D2 VC1 A
S2b iB RB
O B
Vdc G
S2c iC RC
D3 VC2 C
C2
S3a S3b S3c Cf
T2
D4 N
S2x (x = a, b, c)
Figure 5.1 3L-qSBT2I topology
5.1.1. Operation principle of fault-tolerant 3L-qSBT2I.
The fault-tolerant operation of TL qSBT2I can be divided into three cases: S1x
or S3x failure, S2x failure (x = a, b or c), and T1 hoặc T2 failure. Fig. 5.2 presents
three phase-A fault modes. Fig. 2.7 shows the reference voltage vectors of the
inverter in normal operation (⃗ V a, ⃗ V c ) and in fault operation (⃗
V b, and ⃗ V 'a, ⃗
V 'b và ⃗
V 'c ).
When a fault in S1x or S3x occurs, the reference voltage vectors of the inverter must
be modified to (⃗ V 'a, ⃗
V 'b và ⃗
V 'c ) as shown in Figs. 5.3(b)-5.3(d). Table 5.1 shows the
phase angle of the reference voltage vectors of the inverter in normal and fault
conditions

23
 T1 D1 S1a S1b S1c
LB C1 Lỗi S1a
Lf iA RA
VC1 S2a A
iL D2
S2b B iB RB
O G
Vdc iC RC
D3 S2c C
VC2
Lỗi S3a
C2 Cf
T2 D4 S3a S3b S3c

(a)
T1 D1 S1a S1b S1c
LB C1 Lỗi S2a
Lf i A RA
S2a A
iL D2 VC1
S2b i B RB
O B G
Vdc iC RC
D3 S2c C
VC2
C2 Cf
T2 D4 S3a S3b S3c

(b)
Lỗi T1 D1 P Lỗi T1 D1 P D1 P D1 P
T1 S1x T1 S1x T1 T1
LB C1 LB C1 LB C1 LB C1
iL D2 VC1 S iL D2 VC1 S iL D2 VC1 S iL D2 VC1 S
O 2x O 2x O 2x O 2x

D3 X D3 VC2 X D3 X D3 VC2 X
VC2 VC2
Vdc Vdc Vdc Vdc
C2 C2 Lỗi T2 C2 S3x Lỗi T2 C2 S3x
T2 N T2 D4 N T2 N T2 D4 N
D4 D4
(c) (d) (e) (f)

Figure 5.2 Operation of 3L-qSBT2I in OC fault condition. (a) OC fault of S1a or

S3a, (b) OC fault of S2a and (c) NST5 of OC fault of T1 or T2 and (d) NST6 of OC
fault of T1 or T2.
Table 5.1: Corrective angles in normal and fault conditions.
Modulating signal ⃗
V 'a ⃗
V 'b ⃗
V 'c ⃗
V 'ab ⃗
V 'bc ⃗
V 'ca
Normal operation -2π/3 2π/3 π/6 -π/2 5π/6
Phase A fault 0 -5π/6 5π/6 π/6 -π/2 5π/6
Phase B fault π/6 0 π/2 π/6 -π/2 5π/6
Phase C fault -π/6 -π/2 0 π/6 -π/2 5π/6

5.1.1.1. Fault-tolerant control when S1x or S3x is faulty

If the OCS failure occurs in switch S1a or S3a in Fig. 2(a), the output phase-A
voltage, VAO is not able to produce either +VC or -VC, which results in the load
current asymmetrical and distorted. To maintain continuous output voltage by
triggering middle-point switch S2a while switches S1a and S3a are turned off. On the
other hand, the reference voltage vectors ⃗V a, ⃗
V b,và ⃗
V c are modified as described in
Figs. 5.3(b)-5.3(d) to keep balanced line-to-line voltages.
5.1.1.2. Fault-tolerant control when S2x is faulty
If the OCS failure occurs at switch S2a as shown in Figure 5.2, the output pole
voltage of the phase-A leg (VAO) cannot be connected to the neutral point of the
AIS network. To solve this problem, switches S1a and S3a in the fault-tolerant TL
qSBT2I
is used to generate a two-level voltage for the phase-A leg, while the switches of
the phase-B and phase-C legs are used to generate a three-level voltage for phase-
B and phase-C.
5.1.1.3. Fault-tolerant control when T1 or T2 is faulty
When an OCS failure occurs at switch T 1 or T2 of the switched boost network,
capacitor C1 and C2 voltages are unbalanced. As a result, the output phase voltage
and load current are distorted and their amplitudes are reduced. Figs. 5.2(c) and
5.2(d) show two new NST states of the inverter when the OCS T1 fault occurs
24
5.1.2. Circuit Analysis for the Fault-Tolerant TL qSBT2I.
5.1.2.1 NST Mode
In the NST1 mode. The boost inductor voltage is obtained as
diL
LB
dt
= Vdc - VC 2 . (5.1)
In the NST2 mode. The boost inductor voltage is obtained as
diL
LB
dt
= Vdc - VC1 . (5.2)
In the NST3 mode. The boost inductor voltage is obtained as
diL
LB
dt
= Vdc . (5.3)
In the NST4 mode. The boost inductor voltage is obtained as
diL
LB
dt
= Vdc - VC1 - VC 2 . (5.4)
5.1.2.2 ST mode
In this ST mode. The boost inductor voltage is obtained as
diL
LB = Vdc . (5.5)
dt
5.1.3. PWM Control Method for the Fault-Tolerant TL qSBT2I.
T T/4 vtri1 vtri2
1 VST
Vcon1
0
t
Vcon2
-1 -VST
S1b
0
S2b t
0 t
S3b
0
S1c t
0
S2c t
0 t
S3c
0
T1 t
0
T2 t
0 t
D0T/2 dT/2 dT/2 D0T/2 Trạng thái ngắn mạch
(a)
T vtri1 vtri2
1 va vb vc
VST
0 t
-VST
-1
S1a=S2a
0
S3a t
0 t
S1b=S2b
0
S3b t
0 t
S1c=S2c
0
S3c t
0 t
T2 D0T/2
0 t
D0T/2 = S2x kích dẫn đồng thời
S1a
0
t
S2a=S3a
T1 t
D0T/2
0 t
(b)

Figure 5.3 PWM control method for the fault-tolerant TL-qSBT2I under conditions
of (a) OCS S1a or S3a fault and (b) OCS T1 fault.

25
5.1.4. Steady-State Analysis for the Fault-Tolerant TL qSBT 2I.
Vdc
VC = VC1 = VC 2 =
2 - 3D0 - d
(5.6)
Output voltage is determined
M  VPN M  VC M/ 3
v x    Vdc . (5.7)
2 3 3 2  3D0  d
The boost factor B of fault-tolerant 3L qSBT2I is defined:
VPN 2VC 2
B   . (5.8)
Vdc Vdc 2  3D0  d

5.1.5. Steady-State Analysis for the Fault-Tolerant TL qSBT 2I When AIS T1

Switch is Faulty.
Vg
VC 2 = (5.9)
1- 2 D0
Output peak voltage is defined
M  VC 2 M
v x   Vdc . (5.10)
2 2.(1  2 D0 )
5.1.6. Fault-tolerant control scheme for TL qSBT2I.
 2v x
G1N  in normal mode
 Vg
  (5.11)
G  2 3 v x in faulty mode
 1F
Vg

Begin

Vdc, Vx, d = 0.5, D0 = 0, M = 1, k = 0.02

N Fault = ?
Y
G1N = 2Vx/Vg G1F = 2¥3Vx/Vg

G2 = 2M/(2–3D0–d)

N
G2<(G1N, G1F)
Y
d = d+k
N d == 1
Y
M = d = d – k, D0 = D0+k,
G2 = 2M/(2–3D0–d)

N
(G1N, G1F) = G2
Y
End
Output: D0, M and d

Hình 5.4 Flow chart of the control method before and after fault.

26
5.2. Simulation and experimental results
5.2.1. Simulation results
Table 5.2: Parameters used in simulation and experiment.
Parameter/ Component Value
Output power Po 1 kW
Input voltage Vg 165 V
Desired output voltage VXG 110 Vrms
Output frequency fo 50 Hz
Switching frequency fs 5 kHz
Boost inductor LB 3 mH/ 20 A, 0.12 Ω
Capacitors C1 = C2 2200 F, 44 mΩ
Three-phase LC filter Lf and Cf 3 mH and 10 F
Three-phase resistor load Rload 40Ω
Diodes DSEI60-12A D1 – D4 1200 V, 52 A
IGBTs FGL40N150D S1x–S3x, T1, T2 1500 V, 40 A

With proposed method is applied for fault-tolerant 3L-qSBT 2I. As a result, the
voltage across two capacitors C1 and C2 are boosted, output load current is
recovered.

Figure 5.5. Simulation result of fault-tolerant TL qSBT2I under normal and

fault conditions of S1a when reconstructing the topology and compensating by
control parameters

27
 Figure 5.6. Simulation result of fault-tolerant TL qSBT2I under normal and
fault conditions of S2a when changing modulation method
Figure 5.6 shows the results of the proposed modulation scheme is applied
after the fault. As a result, the distortion of the load currents is removed perfectly.

Figure 5.7. Simulation results of fault-tolerant TL qSBT2I under normal and

fault condition of T1

28
 Figure. 5.7 shows the simulation results of the power switch T 1 of AIS
network occurs an OCS fault. The capacitor C1 voltage is held constant at 181 V,
while the capacitor C2 voltage is boosted to 458 V after the OCS T 1 fault. The
output current is balanced and recovered
5.2.2. Experimental results

Figure 5.8. Experimental result of fault-tolerant TL qSBT2I under normal and

fault conditions of S1a when reconstructing the topology and compensating by
control parameters

(b)
Figure 5.9. Experimental result of fault-tolerant TL qSBT2I under normal and
fault conditions of S2a when changing modulation method
Figure 5.8 shows the experimental results of the fault-tolerant TL qSBT 2I with
the proposed PWM scheme when an OCS S1a is faulted with reconfigurating
circuit and compensating voltage are employed. The amplitudes of load currents
and voltages of the fault-tolerant TL qSBT2I with the proposed PWM scheme are
effectively recovered to their pre-fault values.
The waveforms in Figure. 5.9 show that the compensation scheme under the
fault condition helps to maintain the output waveforms as in the normal condition.

29
In this situation, the distortion of the output currents can also be mitigated in this
failure mode.

(a)

(b)
Figure 5.10. Experimental results fault-tolerant 3L-qSBT2I under normal and OCS
fault conditions of T1.
Figure 5.10 shows the experimental results of the fault-tolerant TL qSBT 2I
with the proposed PWM scheme under OCS T1 fault. When switch T1 is failed, the
capacitor C2 and DC-link voltages are boosted to 436 V, while the capacitor C 1
voltage is unchanged. As shown in Figure 5.10 (b), the amplitude of load currents
is recovered in pre-fault value.
Table 5.3: THD of load current and voltage in normal and fault conditions
Method in [84] Proposed method
Condition
THDi THDv THDi THDv
Normal 3.19% 70.1% 2.77% 62.42%
S1a fault with reconfiguration circuit 5.38% 119.8% 4.58% 91.68%
S2a fault with changing modulation 4.74% 125.8%
3.37% 86.96%
scheme
T1 fault with reconfiguration circuit NA NA 4.43% 119.8%

Conlusion:
On the basic of analysis of fault-tolerant 3L-qSBT2I, researches on fault-
tolerant 3L-qSBT2I domestic and foreign. The author proposed the fault-tolerant
3L-qSBT2I topology has low power, reducing power switches. Above fault-
tolerant 3L-qSBT2I proposed suitable control technique
a) The boost inverter has open-circuit fault of T-Type inverter and
intermediate network switches operation capability;
b) Improving control parameters compared to similar topologys;
c) Proposing fault-tolerant algorithm of two switches of intermediate
network (T1 và T2) without requiring any power components.

30
 Chapter 6: Conlusion and devolopment of thesis
6.1. Results
In this thesis, the author has presented the power converter including the
following chapters: Chapter 1, the author presents an overview of the three-level
quasi-switch boost T-type inverter in Viet Nam as well as in the world. Chapter 2
focus on theoretical basis of three-level quasi-switch boost T-type inverter with
eliminating common-mode voltage capability and three-level quasi switched boost
T-Type inverter with open-circuit fault-tolerant capability. In chapter 3, the author
presented three-level quasi-switch boost T-type inverter topology. In chapter 4,
three-level quasi-switch boost T-type inverter topology with eliminating common-
mode voltage capability is introduced and chapter 5, the author presents three-
level quasi-switch boost T-type inverter topology with open-circuit fault-tolerant
capability.
Based on theorical analysis, simulation and experiment of this topology and
control algorithm mentioned above, the author gave some comments as follows:
In chapter 3, with some disadvantages about size, weight and cost of the
conventional inverters are so high, thus the three-level quasi-switch boost T-type
inverter is better on size, weight and cost of the inverter. In chapter 3, the author
proposed the PWM control method with some advantages as: a) shifting the
original carrier to 900 and combine to alternating pulse insertion technique to help
the converter reduce the boost inductor current ripple; b) Achieving high voltage
gain compared compared to similar topology; c) Highest possible modulation
index compared to similar topology as shown in paper 01.
In chapter 4, the common-mode voltage eliminating is very important in the
multi-level inverters. Because the common-mode voltage causes leakage current,
electromagnetic interference, and shaft voltage in motor driver which it will affect
the life of the motor. In order to eliminate common-mode voltage without
affecting buck-boost operation of the converter and reducing the inductor current
ripple is a big challenge of researchers as shown in paper 03.
In chapter 5, the stability and reliability of the inverter is very important in
power distribution system because it helps uninterruptable power supply systems,
high-power medical systems and grid-connected energy conversion systems.
Therefore, for the system to operate in fault-tolerant conditions is a problem that
researchers around the world are very interested, today. In this chapter, the author
not only handle open-circuit fault of inverter switches, but also handle the open-
circuit fault of impedance active switches. Moreover, the control parameters have
been improved to reduce voltage stress on power devices, as shown in paper 02.
6.2. Devolopment of thesis
In order to exploited and transfered technology of the thesis effectively, the
author suggest to research more and imlemented with the following sections:

31
 Applying the three-level quasi switched boost T-Type inverter to control 3-
phase asynchronous motors in pratice.
Combine the PV system to three-level quasi switched boost T-Type inverter to
connect grid.

32