Al-Balqa’ Applied University

Electronics Lab

:Prepared by
Eng. Mo'men Alattar

1 ELECTRONICS LAB
 Table of contents
Experiment 1:Diode Characteristics…………………………..(3-7)
Experiment 2:Half-Wave And Full-Wave Rectifiers……….(8-15)
Experiment 3: Limiters And Clampers………………………...(16-24)
Experiment 4: Zener Diodes……………………………………..(25-30)
Experiment 6: common-emitter………………..………………..(31-36)
Experiment 7: JFET………………………………………………..(43-47)
Experiment 8: Data Acquisition…………………..……………..(48-52)

2 ELECTRONICS LAB
 Al-Balqa’ Applied University

Electronics Lab

Experiment 1
Diode Characteristics
/ / Experiment Date
Group No ( )

Student Name:……………………………………..
……………………………………..

.……………………………………………………………:Supervisor

3 ELECTRONICS LAB
Objectives:
The purpose of this experiment is to examine characteristics of a silicon diode.
When the diode’s anode is at a higher potential than is the cathode. The diode is
forward biased. For conventional current flow, Current will flow through the
diode from anode to cathode.
For electron flow, current will flow from cathode to anode. Unlike re-sister. In
which the current is directly proportional to the voltage across it. The diode is
nonlinear device. When the diode is forward biased, a small but measurable
voltage drop called the barrier potential across the diode.
For germanium diodes, this value is typically 0.3V, for silicon diode, it is
approximately 0.7V.

EXPERIMENT:

The determination of Rf, the diode forward resistance, is shown graphically in Fig
1.

Rf =∆Vd /∆Id Id

∆Id

∆Vd

Vb Vd
Fig 1

1. Construct the circuit shown in fig 2, adjust the dc power supply to give the
voltages across the 1kohm resistor shown in table 1, for each voltage,

4 ELECTRONICS LAB
 measure and record the dc voltage drop (vd) across the diode. The diode
current is also the current flowing through the 1kohm resistor. Determine
the diode current by using ohm’s law in each case.
D1

1N914

V1
R1
15V
1.0kohm

Fig 2

Table 1

Voltage across Diode Diode forword

1-kΩ Resistor (V) voitage Current (mA)
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
2
3
4
5
6
7
8
9
10

5 ELECTRONICS LAB
 The characteristic diode curve graphiclly

Rf =Vd /∆Id = (0.7-0.5)V/(5-0.8)mA

= 46.7Ω
2.Construct the circuit in fig 3 and draw by the oscilloscope the characteristic
diode curve.

XSC1

G
T
A B

R3 D1

V2 100ohm 1N914
1V 100Hz 0Deg R2
10ohm

fig 3

6 ELECTRONICS LAB
Id

VB Vd

The characteristic diode curve by the oscilloscope

7 ELECTRONICS LAB
 Al-Balqa’ Applied University

Electronics Lab

Experiment 4
Half-WaveAnd Full-Wave Rectifiers
/ / Experiment Date
Group No ( )

Student Name:……………………………………..
……………………………………..

.……………………………………………………………:Supervisor

8 ELECTRONICS LAB
 PURPOSE:

The purpose of the experiment is to demonstrate the characteristics of three

different diode rectifier circuits: half-wave rectifier, center tapped full-wave
rectifier, and full-wave bridge rectifier.
Each type causes an ac input voltage to be converted into a pulsed waveform
having an average or dc voltage output.

REQUIRED PARTS AND EQUIPMENT:

1. 1KΩ resistor.1/2W.
2. Four 1N4001 silicon rectifier diodes.
3. 12.6-V rms secondary center tapped transformer.
4. Dual trace oscilloscope.
5. VOM or DMM.
6. Bread boarding socket.

EXPERMEMINT:
 HALF-WAVE RECTIFIERS:
Diodes are used in rectifier circuits, because of their unique ability to contact current
in only one direction. Rectification is the process of converting ac to pulsating dc.
In the half-wave rectifier circuit, when the input sine wave goes positive, the diode is
forward-biased and conducts current to the load resistor .the current produces a
voltage across which the load which has the same shape as the positive half-cycle of
the input voltage.

9 ELECTRONICS LAB
 When the input voltage goes negative during the second half of the cycle, the diode is
reveres-biased. There is no current, so that the voltage across the load resistor is 0.
The net result is that only the positive half-cycles of the ac input voltage appear
across the load, making the output a pulsating dc voltage as shown in Fig 1.

XSC1

XFG1
G
T
A B
D1
T2
. .

1N4001GP

Vp R1
NLT_PQ_4_10 1.0kohm

Fig 1: the Half-wave rectifier circuit

For half-wave rectifier:

1.Dc voltage output=(VS-VB)/∏ (sine wave input)

2.Diode PIV=Vp.
3.Output frequency=input frequency.

10 ELECTRONICS LAB
 The output voltage wave for a half-wave rectifier

If Vp input =3.7*5 = 18.5 V.

Dc voltage output = (VS-VB)/∏

= (18.5 – 0.7)/3.14 = 5.67 V.
Diode PIV=Vp
= 18.5 V.

 FULL-WAVE RECTIFIERS:
I. Center-Tapped Rectifier:
A first popular full-waveRectifier appears in Fig 2, with only two diodes but
requiring a center-tapped transformer to establish the input signal across each
section of the secondary of the transform.
During the positive portion of vi applied to the primary of the transformer, will
appear as shown in Fig 2 D1 assumes the short-circuit equivalent and D2 the open-

11 ELECTRONICS LAB
 circuit equivalent, as determined by the secondary voltages and the resulting
current direction.
During the negative portion of the input the network appears as shown in Fig 2.
Reversing the roles of the diodes but maintaining the same polarity for the voltage
across the load resistor R.
The net effect is the same output as that appearing in fig 2.

XSC1

XFG1
G
T
A B
T1 D1

1N4001GP
R1
TS_PQ4_10 Vp 1.0kohm

D2

1N4001GP

Fig 2: Center-Tapped Rectifier circuit.

For Center-Tapped full-wave rectifier:

1.Dc voltage output=2(VS-VB)/∏ (sine wave input)

2.Diode PIV=2Vp.
3.Output frequency=2*input frequency.

12 ELECTRONICS LAB
 The output voltage wave forCenter-Tapped full-wave rectifier.

If Vp input =3.7*5 = 18.5 V.

Dc voltage output =2 (VS-VB)/∏

= 2*(18.5 – 0.7)/3.14 = 11.34 V.
Diode PIV=2*Vp
= 37 V.

Bridge rectifier:
A second full-waveRectifier appears in Fig 3,with its four diodes in abridge
configuration. During the positive period the polarity of the input as shown in fig
3 .the resulting polarities across the diode are also shown in fig 3 to reveal that D2
and D3 are conducting while D1 and D2 are in the “off” state.
The net result is the configuration of fig 3, with its indicated current and polarity
across R.
For the negative region of the input the conducting diodes are D1 and D4,
resulting in the configuration of fig 3. the important result is that the polarity
across the load R is the same as in the positive case.

13 ELECTRONICS LAB
 XSC1
XFG1
G
T
A B

T1
. . 2 D1

4 1

NLT_PQ_4_10
1B4B42
R1
3
Vp 1.0kohm

Fig 3: Bridge Rectifier circuit.

For Bridge full-wave rectifier:

1.Dc voltage output=2(VS-2VB)/∏ (sine wave input)
2.Diode PIV=Vp.
3.Output frequency=2*input frequency.

The output voltage

wave forBridge
full-wave rectifier.

If Vp input =3.7*5
= 18.5 V.

Dc voltage output
=2 (VS-2VB)/∏

= 2*(18.5 –2*
0.7)/3.14 = 10.9
V.
Diode PIV=Vp

14 ELECTRONICS LAB
 = 18.5 V.

Al-Balqa’ Applied University

15 ELECTRONICS LAB
 Electronics Lab

Experiment 3
Limiters
/ / Experiment Date
Group No ( )

Student Name:……………………………………..
……………………………………..

.……………………………………………………………:Supervisor

PURPOSE:

The purpose of the experiment is to demonstrate the operation of a diode limiter .

The diode limiters are wave-shaping circuits in that they are used to prevent signal
voltages from going above or below certain levels. The limiting level may be
either equal to the diodes barrier potential or made variable with a dc source
voltage.

REQUIRED PARTS AND EQUIPMENT:

1. 15-k Ω, 10-k Ω, 1/4 W.

16 ELECTRONICS LAB
 2. IN4001 silicon rectifier diode.
3. 0-15 V dc power supply.
4. Signal generator.
5. Dual trace oscilloscope.
6. Breadboarding socket.

EXPERMEMINT:

 THE Diode LIMITER:

For the circuit show in Fig 1,when the input waveform goes positive at a level grater
than the barrier potential of the diode. The diode is forward biased, the equivalent of
a short circuit in series with a small dc voltage source. Thus approximately 0.5 to 0.7
V, (the barrier potential for a silicon diode) is dropped across the diode. When the
input waveform goes negative, the diode looks like an open circuit, and essentially
all of the input appears at the output.
Such an arrangement is called a positive limiter because the circuit limits the positive
peaks of the input waveform.

XSC1

G
T
A B
R1

V1 15kohm
3V 200Hz 0Deg
Vout
D1
1N4009

Fig 1
The positive limiter circuit

17 ELECTRONICS LAB
 Fig. 2
Output voltage wave for positive limiter

For the circuit in Fig 2, when the input waveform goes positive, the diode is reveres
biased, the equivalent of an open circuit and essentially all of the input appears at the
output. When the input waveform goes negative, at a level grater than the barrier
potential of the diode. The diode is forward biased, the equivalent of a short circuit in
series with a small dc voltage source. Thus approximately -0.5 to -0.7 V, (the barrier
potential for a silicon diode) is dropped across the diode.
Such an arrangement is called a negative limiter because the circuit limits the
negative peaks of the input waveform.

XSC1

G
T
A B
R1

V1 15kohm
3V 200Hz 0Deg
Vout
D2
1N4009

Fig .3
The negative limiter circuit

18 ELECTRONICS LAB
 Fig .3
Output voltage wave for negative limiter

The positive clipping level is the dc source voltage plus the diode’s barrier
potential.
For the diode to become forward biased, the positive peaks of the input signal
must be greater than the dc source voltage and the diode’s barrier potential.

19 ELECTRONICS LAB
 XSC1

G
T
A B
R1

15kohm
Vout
D1
V1 1N4009
3V 200Hz 0Deg

V2
1V

Fig .5
The positive clipper circuit

Fig.6
Output voltage wave for positive clipper

The negative clipping level is the dc course voltage plus the diode’s barrier
potential.
For the diode to become forward biased, the negative peaks of the input signal
must be greater than the dc source voltage and the diode’s barrier potential.

20 ELECTRONICS LAB
 XSC1

G
T
A B
R1

15kohm
Vout
D2
V1 1N4009
3V 200Hz 0Deg

V3
1V

Fig.7
The negative clipper circuit

Fig.8
Output voltage wave for negative clipper

Al-Balqa’ Applied University

21 ELECTRONICS LAB
 Electronics Lab

Experiment 4
Clampers
/ / Experiment Date
Group No ( )

Student Name:……………………………………..
……………………………………..

.……………………………………………………………:Supervisor

PURPOSE:

The purpose of the experiment is to demonstrate the operation of a clamper like

the diode clipper Because of this clipping the limiter capability the limiter is also
called a clipper.

22 ELECTRONICS LAB
 The clamper is a wave-shaping circuit, but it adds a dc level to the input
waveform. Thus the clamper is often referred to as a dc resistor. However, unlike
that of the clipper. The shape of the input signal of a clamper is not changed.

REQUIRED PARTS AND EQUIPMENT:

1. 15-k Ω, 10-k Ω, 1/4 W.
2. IN4001 silicon rectifier diode.
3. 0-15 V dc power supply.
4. Signal generator.
5. Dual trace oscilloscope.
6. Breadboarding socket.

 THE DIODE CLAMPER:

The clamping network is one that will ‘clamp’ a signal to a different dc level. The
network must have a capacitor, a diode, and a resistive element, but it can also
employ an independent dc supply to introduce an additional shift. The magnitude
of R and C must be chosen such that the time constant τ = RC is large enough to
ensure that the voltage across the capacitor does not discharge significantly during

23 ELECTRONICS LAB
the interval the diode is nonconduting. Throughout the analysis we will assume
that for all practical purpose the capacitor will fully charge or discharge in five
times constant.

XSC1

G
T
A B
C1

10uF Vout
V1
2.5V 1kHz 0Deg D1 R1
1N4009 10kohm

Fig .9
The negative clamper circuit

24 ELECTRONICS LAB
 Fig .10
Output voltage wave for negative clamper

XSC1

G
T
A B
C2

10uF Vout
V1
2.5V 1kHz 0Deg D2 R1
1N4009 10kohm

Fig .11
The positive clamper circuit

25 ELECTRONICS LAB
 Fig .12
Output voltage wave for positive clamper

26 ELECTRONICS LAB
 Al-Balqa’ Applied University

Electronics Lab

Experiment 4
Zener Diodes

/ / Experiment Date
Group No ( )

Student Name:……………………………………..
……………………………………..

.……………………………………………………………:Supervisor

27 ELECTRONICS LAB
PURPOSE:
The purpose of this experiment is to demonstrate the characteristics of a zener
diode and its use as a simple voltage regulator unlike rectifier diodes.
Zener diodes are normally reverse biased, so they maintain a constant voltage
across their terminals over a specified range of current. Like rectifier diode, a
zener diode can be approximated by a ΩΩ constant dc voltage source in series
with a resistor.
When used as a regulator, the zener diode maintains a dc output voltage that is
essentially constant even though the load current may very.

REQUIRED PARTS AND EQUIPMENT:

1. 100 Ω, ¼ W.
2. Tow 220 Ω, ½ W.
3. 1N753, 6.2-V, 400 Mw zener diode.
4. 0-15 dc power supply.
5. Signal generator.
6. Tow DMMs (preferred) or VOMs.
7. Dual trace oscilloscope.
8. Breadboarding socket.

EXPERMEMINT:
The analysis of networks employing zener diode is quite similar to that applied to
the analysis of semiconductor diodes in previous section. First the state of the
diode must be determined following by a substitution of the appropriate model
and a determination of the other unknown quantities of the network. Unless
otherwise specified the zener model to be employed for the “on” state, for the
“off” state as defined by a voltage less than V z but greater than 0V with the
polarity indicate in fig. The zener equivalent is the open circuit.

イ PART 1:

Construct the circuit shown in fig 1 then complete the table after it.

28 ELECTRONICS LAB
 XMM1

A
Rs

220ohm Iz XMM2

V1 V
15V Vz
D1
1N4753A

Fig 1.

Vin ( V ) Zener voltage Zener Current

Vz ( V ) Iz( mA )

1 1 0
2 2 0
3 3 0
4 4 0
5 5 0.6
7 5.1 1.0
9 5.2 3
11 5.3 25
15 5.4 43

Zener knee voltage 5.28

Iz =20 mA
Internal zener resistance 264 Ω

ロ PART 2:

29 ELECTRONICS LAB
Construct the circuit shown in fig 2 then complete the table after it.

Rs

220ohm
Iz IL Vout
Is D2 RL
Vin 1N4753A 220ohm
15V
Vz

Fig 2.

Parameter Measured Value Expected Value % Error

Is
Iz
IL
VFL

 PART 3:

Construct the circuit shown in fig 3 then complete the table after it.

30 ELECTRONICS LAB
 XSC1

G
T
A B

Rs

220ohm
B
A
V1
15V RL
D1
1N4753A 220ohm

0.5V 1kHz 0Deg

R
100ohm
V2

Parameter Measured Expected % Error

Value Value
IS
IZ
VNL
% Load regulation
% VR
Dc input voltage
VIN (dc)
Ac input ripple
voltage, Vin (ripple)
peak to peak
Dc output voltage V0
(dc)
Ac output ripple
voltage, V0 (ripple)
peak to peak

31 ELECTRONICS LAB
Results And Conclusion:
In the experiment we studying the characteristic of a zener diode, it is
normally reverse biased ,so they maintain a constant voltage across their terminals
over a range of current.
The zener diode current essentially Zero for diode voltage less than knee
voltage.
We can note from data the output voltage remains essentially constant after
many times.
You can see the curve of characteristic for zener diode and theoretical results
in the next page.

32 ELECTRONICS LAB
 Al-Balqa’ Applied University

Electronics Lab

Experiment 5
common-emitter

/ / Experiment Date
Group No ( )

Student Name:……………………………………..
……………………………………..

.……………………………………………………………:Supervisor

33 ELECTRONICS LAB
PURPOSE:

The purpose of this experiment are to demonstrate the operation and

characteristics of the small-signal common-emitter amplifier and investigate what
influences its voltage gain The common-emitter amplifier is characterized by
application of the amplifier input signal to the base lead while its output is taken
in the collector. Which always gives an 180ْ phase shift.

REQUIRED PARTS AND EQUIPMENT:

9. Resistors: 150 Ω, 2.7k Ω, tow 3.9 k Ω, 4.7 k Ω, 10 k Ω ¼ W.
10. Capacitors: tow 2.2µF, 10µF.
11. 2N3904 npn silicon transistor.
12. 0-15 dc power supply.
13. Signal generator.
14. DMM (preferred) or VOM.
15. Dual trace oscilloscope.
16. Breadboarding socket.

USEFUL FORMULAS:

1. Transistor ac emitter resistance:

re = 25mV/IE.
2. Quiescent dc base voltage:
VB = (R2/(R1+R2)) VCC.
3. Quiescent dc emitter voltage:
VE = VB-VBE.
4. Quiescent dc emitter current:
IE = VE/(RE1+RE2).
5. Quiescent dc collector voltage:
VC = VCC-ICRC.
6. Quiescent dc collector-emitter voltage:
VCE = VCC-IC (RC+RE1+RE2).

34 ELECTRONICS LAB
EXPERMEMINT:
 First constructthe circuit shown in fig 1, then determine the gain voltage
of circuit measuring using oscilloscope and calculating using this
equation: AV = (RC\\RL)/(RE1+re).
Then compare between tow values.

XSC1

VCC 15V T
A B

Rc
R1 3.9kohm
10kohm C2
2.2uF

C3 Q1
2N3904
Vout
Vin
2.2uF
RL
0.2V 5kHz 0Deg R2 RE1 3.9kohm
4.7kohm 150ohm
V1

RE2 C1
2.7kohm
10uF

Fig1.common-emiter amplifier circuit (normal circuit)

Graph1.input and output ac voltage for circuit in fig1

35 ELECTRONICS LAB
  Second constructthe circuit shown in fig2 (without load resistor R L), then
determine the gain voltage of circuit measuring using oscilloscope and
calculating using this equation: AV = RC /(RE1+re).
Then compare between tow values.

XSC1

VCC 15V T
A B

Rc
R1 3.9kohm
10kohm C2
2.2uF

C3 Q1 Vout
2N3904
Vin
2.2uF
0.2V 5kHz 0Deg R2 RE1
4.7kohm 150ohm
V1

RE2 C1
2.7kohm
10uF

Fig2.common-emiter amplifier circuit (without load resistor)

Graph2.input and output ac voltage for circuit in fig2

36 ELECTRONICS LAB
  Third constructthe circuit shown in fig3 (without bypass capacitor C 1),
then determine the gain voltage of circuit measuring using oscilloscope
and calculating using this equation: AV = (RC\\RL)/(RE1+RE2+re).
Then compare between tow values.

XSC1

VCC 15V T
A B

Rc
R1 3.9kohm
10kohm C2
2.2uF

C3
Vout
Q1
2N3904
Vin R3
2.2uF 3.9kohm
0.2V 5kHz 0Deg
RE1
R2 150ohm
4.7kohm
V1

RE2
2.7kohm

Fig3.common-emiter amplifier circuit (without bypass capacitor)

Graph3.input and output ac voltage for circuit in fig3

37 ELECTRONICS LAB
 Parameter Measured value Expected value
VB 4.6V 4.8V
VE 3.9V 4.1V
VC 9.2V 9.38V
TABLE 1.

Parameter Value
IE (calculated) 1.44mA
re (calculated) 17.36 Ω
TABLE 2.

Condition Vin Vout Measured Expected

Gain Gain
Normal circuit 0.2V(P-P) 2.2V(P-P) 11 11.65
(fig1)
No load (fig2) 0.2V(P-P) 4.4V(P-P) 22 23.3
No bypass 0.2V(P-P) 0.12V(P-P) 0.6 0.68
capacitor (fig3)
TABLE 3.

38 ELECTRONICS LAB
 Al-Balqa’ Applied University

Electronics Lab

Experiment 6
Operation Of Common-Emitter

/ / Experiment Date
Group No ( )

Student Name:……………………………………..
……………………………………..

.……………………………………………………………:Supervisor

39 ELECTRONICS LAB
PURPOSE:

The purpose of this experiment is to demonstrate the operation of a class A

common-emitter power amplifier. The class A amplifier is biased such that
collector current always flows during the entire cycle of the input waveform.
Ideally the amplifier’s Q point should be biased at the center of the ac load line so
that the output signal can have the maximum possible swing in both directions.
Consequently clipping will occur simultaneously on both peaks of the output
signal if the amplifier is overdriven. If the Q point is not centered on the ac load
line, output waveform clipping will occur first, either at saturation or at cutoff.
Despite the simplicity of the class A amplifier, the maximum efficiency that can
be expected for it with a capacitively coupled load is only 25 percent.

REQUIRED PARTS AND EQUIPMENT:

17. Resistors: 220 Ω, 560 Ω, 1 k Ω, 4.7 k Ω, 10 k Ω ,100kΩ ¼ W.
18. 5- k Ω potentiometer.
19. Capacitors: tow 2.2µF, 100µF.
20. 2N3904 npn silicon transistor.
21. 0-15 dc power supply.
22. Signal generator.
23. DMM (preferred) or VOM.
24. Dual trace oscilloscope.
25. Breadboarding socket.

USEFUL FORMULAS:

1. Quiescent dc base voltage:

VB = (R2/(R1+R2)) VCC.
2. Quiescent dc emitter voltage:
VE = VB-VBE.
3. Quiescent collector current:
ICQ = VE/RE.
4. Quiescent dc collector-emitter voltage:
VCEQ = VCC-ICQ (RC+RE).
5. Collector saturation current:
Icsat = ICQ+(VCEQ/Rc).

6. Collector-emitter cutoff voltage:

40 ELECTRONICS LAB
VCEcutoff = VCEQ+ICQRc .
7. For centered Q point:
Icsat = 2ICQ
VCEcutoff = 2VCEQ
Rc= VCEQ/ICQ
Where: Rc = RC//RL.
8. rms output (load) power:
Pο = (Vο(rms))2 /RL.
9. dc power supplied to amplifier:
Pdc = VCCICQ.
10. Amplifier percent efficiency:
ξ = (Pο(rms)/ Pdc)*100%.

EXPERMEMINT:

Procedure:
1. Wire the circuit shown in figure 1, omitting the signal generator and the
power supply.

XSC1

VCC G
15V
T
A B

R1 Rc
1.0kohm
10kohm
C2

C1 2.2uF
Q1 RL
2N3904 5.1kohm
2.2uF
V2
R2
4.7kohm RE C3
30mV 5kHz 0Deg 560ohm 10uF

Fig 1.
2. After you have checked all connections. Apply only the 15-V supply
voltage to the breadboard. With the VOM or DMM, individually measure

41 ELECTRONICS LAB
 the transistor dc base and emitter voltages with respect to ground, as will as
VCEQ .Recording your results in table 1. Based on the resistor values of fig 1,
determine the expected values of these three voltages. Assuming a base-
emitter voltage drop of 0.7V, and compare them with the measured values
in table 1.
3. Measured the quiescent dc collector current I CQ, comparing it with the
expected value (ICQ = VE/RE.), record your values in table 1.

Parameter Measured value Expected value

VB 4.5 V 4.8 V
VE 4V 4.1 V
VCEQ 3.4 V 3.58 V
ICQ 7.2 mA 7.32 mA
Table 1, class A amplifier bias parameters.

4. Connect channels 1 of your oscilloscope at point I (vin) and

channel 2 to point O (vout). Adjust your oscilloscope to the following
approximate settings:
Channel 1: 10 mV/division, ac coupling
Channel 2: 1 mV/division, ac coupling
5. From equation (Rc = VCEQ /ICQ, ), determine the value of the load resistor RL
that gives a centered Q point on the ac load line.
6. Connect the signal generator to the breadboard, and adjust the sine wave
output level of the generator at 30mV peak to peak, at the frequency of
5KHz. If your signal generator cannot be adjusted to 30mV, any value
higher than this can be used as long as the output signal is not clipped. You
should observe that the peak-to-peak output voltage is much larger than the
input, in addition to having a phase shift of 180`.
Increases the positive and negative peaks become clipping. Note that if the
Q point is placed very near the center of the ac load line, both peaks become
clipped at approximately the same time consequently the transistor reaches
cutoff and saturation at the same input level.

7. Now reduce the input signal level to zero and replace the
Potentiometer with a 220 Ω resistor, increase the input signal
Level so that one peak slips off much either than the other. As
Shown in fig 2.

42 ELECTRONICS LAB
 Fig 2.

We should observe that now only the negative peaks are clipped. This
condition is characteristic of secretion clipping because the Q point is closer to the
ac load line’s collector saturation current than to the collector-emitter’s cutoff
voltage. Confirm this saturation by drawing the ac load line with the Q point on
the graph page provided.
8. now carefully increase the peak-to-peak input signal just before
both output peaks clip off. With your DMM measure the rms
voltage across the load resistor, and compute the rms output
power of the amplifier (Pο = (Vο(rms))2 /RL.),
Record these results in table 2.
8. Using equation (Pdc = VCCICQ. ) to calculate the dc power supplied
Record this value in table 2.
9. Compute the percent efficiency of your amplifier using equation(ξ =
(Pο(rms)/ Pdc)*100%.), and compare it with the theoretical maximum of
25%, record your result in table 2.

Parameter Measured value

Vο(rms) 11.5 V
Parameter Calculated value

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 Pο(rms) 26.45 mW
Pdc 109.8 mW
ξ 24%
Table 2, class A amplifier efficiency.

Al-Balqa’ Applied University

44 ELECTRONICS LAB
 Electronics Lab

Experiment 7
JFET

/ / Experiment Date
Group No ( )

Student Name:……………………………………..
……………………………………..

.……………………………………………………………:Supervisor

PURPOSE:

The purpose of this experiment is to use the oscilloscope to display the drain
curve for the MPF102 JFET. This curve shows the variation of drain current as a
function of drain-to-source voltage with a constant gate-to-source voltage. Thus,

45 ELECTRONICS LAB
with the special case of having zero gate-to-source voltage, it is possible to
estimate JFET parameters such as drain current with gate shorted to source I DSS, as
will as gate-to-source cutoff voltage, VGScutoff.

REQUIRED PARTS AND EQUIPMENT:

1. Resistors: 100Ω ¼ W.
2. MPFI02 n-channel JFET.
3. 1N914 silicon rectifier diode.
4. 0-15V dc power supply.
5. Signal generator.
6. DMM (preferred) or VOM.
7. Dual trace oscilloscope.
8. Breadboarding socket.

USEFUL FORMULAS:

gm0 = (2 IDSS )/ VGscutoff.

EXPERMEMINT:
Procedure:

46 ELECTRONICS LAB
1.wire the circuit shown in the schematic diagram of figure 1, in this part, the
oscillator is set up to function as an X-Y Plotter. Set the oscilloscope controls to
the following approximate settings:
Vertical (Y) input sensitivity: 0.2 V/division, dc coupling.
Horizontal (X) input sensitivity: 1 V/division, dc coupling.

XSC1

G
T
A B

V1
D 15V
D1 G Q1
BF245A

V2 1N914 S
R1
10V 500Hz 0Deg 100ohm

Fig 1.
2. After the oscilloscope has warmed up, move the trace dot to the upper right-
hand corner of the oscilloscope’s screen so that it is centered on the intersecting
scale division of the display. Now apply power and the signal generator to the
breadboard.
3. Adjust the frequency of the signal generator to 500 Hz and at a signal level
sufficient to produce a display similar to that shown in fig 1.
The horizontal input measure the JFET’s instantaneous gate-to-source (V GS).
The diode allows only negative voltage variations, which serve as the drain-to-
source voltage. The vertical input measures the voltage drop across the 100Ω
resistor. As shown on the display, the vertical axis increases downward, which is

47 ELECTRONICS LAB
inverted from the normal sense. Using Ohm’s law, we can make the vertical input
read the JFET’s instantaneous drain current (I DSS). If the vertical sensitivity is
resistors (which is the same as the drain current).
Vertical sensitivity = (0.2 V/division)/100Ω
= 2 mA/division.

Fig 2
4. Using figure2 as a guide, estimate from the oscilloscope’s display both I DSS
and VGS(off), for the MPF102 JFET you are using. Record these values in table 1.
5. From the values for IDSS and VGS(off) measured in step 4, calculate the MPF102
JFET forward transconductance at zero gate-to-source voltage g m0 and record this
value in table 1.

IDSS 1.39 mA
VGS(off) 3.37 V
gm0 824.9µS
Table 1.

48 ELECTRONICS LAB
 Al-Balqa’ Applied University
49 ELECTRONICS LAB
 Electronics Lab

Experiment 8
low-frequency response of a common-emitter

/ / Experiment Date
Group No ( )

Student Name:……………………………………..
……………………………………..

.……………………………………………………………:Supervisor

PURPOSE:
The purpose of this experiment is to demonstrate the factors that contribute to the
low-frequency response of a common-emitter transistor amplifier. The low-
frequency response of a typical common-emitter amplifier is determined in part by
the input and output coupling capacitors and the emitter bypass capacitor. The
result is essentially a combination of three high-pass filter networks that allow

50 ELECTRONICS LAB
signals having frequencies greater than the cutoff frequency of the dominant
network to pass through while attenuating all others. Although the cutoff
frequencies associated with these three paths can be made equal, such is rarely the
case.
This experiment examines individually the effect of each capacitor on the
common-emitter amplifier’s low-frequency response. In all cases, the values of
the capacitors are intentionally made abnormally small in order to allow the
frequency response to be easily measured.

REQUIRED PARTS AND EQUIPMENT:

26. Resistors: 150 Ω, tow 2.7kΩ, 3.9kΩ, 4.7 k Ω, 100 k Ω ¼ W.
27. Capacitors: tow 0.033µF, 1µF, tow 2.2µF, 10µF.
28. 2N3904 npn silicon transistor.
29. 0-15 dc power supply.
30. Signal generator.
31. DMM (preferred) or VOM.
32. Dual trace oscilloscope.
33. Breadboarding socket.

USEFUL FORMULAS:
1. Quiescent dc base voltage:
VB = (R2/(R1+R2)) VCC.
2. Quiescent dc emitter voltage:
VE = VB-VBE.
3. Quiescent dc emitter current:
IE = VE/(RE1+RE2).
4. Amplifier ac input impedance:
Rin= R1//R2//β (re+RE1).
Av = vout/vin.
Av = (RC//RL)/(re+RE1).

5. Decibel voltage gain:

dB = 20log(Av).
6. Frequency response due to input coupling capacitor C1:
f1 = 1/(2πC1Rin ).
7. Frequency response due to emitter bypass capacitor C2:
f2 = 1/2πC2[((Rin. /β)+ re+RE1)// RE2].

51 ELECTRONICS LAB
 8. Frequency response due to output coupling capacitor C3:
f3 = 1/(2πC3 (RC+RL)).

EXPERMEMINT:

Procedure:
4. Wire the circuit shown in figure 1, omitting the signal generator and the
power supply.

XSC1

G
T
A B
VCC
15V

Rc
R1 3.9kohm
10kohm C2
2.2uF

C3 Q1 Vout
Vin 2N3904

2.2uF RL
RE1 3.9kohm
0.2V 5kHz 0Deg
R2 150ohm
4.7kohm

V1
RE2 C1
2.7kohm
10uF

Fig 1.

5. After you have checked all connections. Apply only the 15-V supply
voltage to the breadboard. With the VOM or DMM, individually measure
the transistor dc base and emitter voltages with respect to ground, determine
the transistor’s ac internal emitter resistance re (re = 25mV/IE). Then
determine the expected mid-band voltage gain of the amplifier in decibel
(Av = (RC//RL)/(re+RE1)) and (dB = 20log(Av)).Record the results in table 1.

52 ELECTRONICS LAB
 3. Connect channels 1 of your oscilloscope at point I (vin) and
channel 2 to point O (vout). Adjust your oscilloscope to the following
approximate settings:
Channel 2: 0.5 mV/division, ac coupling
Then connect the signal generator to the breadboard, and adjust the sine at the
frequency of 50KHz. Measure the input voltage level, and determine the
amplifier’s dB voltage gain (dB=20log(Av)). Record this value in table 1.

Parameter Value
VE(measured) 4.1V
re(measured) 17.3 Ω
Vin 0.4V
Vout 4V
Av(dB)(measured) 18dB
Av(dB)(expected) 20dB
Table1 amplifier midband response.

4. In order to determine the amplifier’s low-frequency 3-dB point due solely to

the effects of the input coupling capacitor C1, replace C1 with a 0.033µF
capacitor. Adjust the sine wave output level of the generator at a frequency of
50kHz so that the peak-to-peak output voltage of the amplifier spans 7.1
vertical divisions when channel 2 is set at sensitivity of 0.5V/division. Then
slowly reduce the input frequency until the peak-to-peak output voltage drops
to 5 vertical divisions. Measure the frequency at which this value occurs, and
record this frequency (f1) in table 2 along with the expected value (f 1=
1/(2πC1Rin )) for comparison.

5. In order to determine the amplifier’s low-frequency 3-dB point due solely to

the effects of the bypass coupling capacitor C2, replace C2 with a 10µF
capacitor. Adjust the sine wave output level of the generator at a frequency of
50kHz so that the peak-to-peak output voltage of the amplifier spans 7.1
vertical divisions when channel 2 is set at sensitivity of 0.5V/division. Then
slowly reduce the input frequency until the peak-to-peak output voltage drops
to 5 vertical divisions. Measure the frequency at which this value occurs, and
record this frequency (f2) in table 2 along with the expected value (f 2 =
1/2πC2[((Rin. /β)+ re+RE1)// RE2) for comparison.

53 ELECTRONICS LAB
 6. In order to determine the amplifier’s low-frequency 3-dB point due solely to
the effects of the input coupling capacitor C1, replace C1 with a 0.033µF
capacitor. Adjust the sine wave output level of the generator at a frequency of
50kHz so that the peak-to-peak output voltage of the amplifier spans 7.1
vertical divisions when channel 2 is set at sensitivity of 0.5V/division. Then
slowly reduce the input frequency until the peak-to-peak output voltage drops
to 5 vertical divisions. Measure the frequency at which this value occurs, and
record this frequency (f1) in table 2 along with the expected value (f 1=
1/(2πC1Rin )) for comparison.

Frequency Measured Expected

f1 2.3kHz 2.5kHz
f2 1.9kHz 2kHz
f3 1.6kHz 1.4kHz

54 ELECTRONICS LAB