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SECTION 7
GPIO
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GPIO

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

7.2 GPIO PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . 7-3
7.3 GPIO REGISTER (GPIOR) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
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GPIO
Introduction

7.1 INTRODUCTION

The General Purpose Input/Output (GPIO) pins are used for control and handshake
functions between the DSP and external circuitry. The GPIO port has eight I/O pins
(GPIO0–GPIO7) that are controlled through a memory-mapped register. Each GPIO
pin may be individually programmed as an output or as an input.

7.2 GPIO PROGRAMMING MODEL

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The GPIO pins are controlled through the GPIO control/data Register (GPIOR),
which is illustrated in Figure 7-1. The register is described in the following
paragraphs.

7 6 5 4 3 2 1 0
GPIOR
GD7 GD6 GD5 GD4 GD3 GD2 GD1 GD0
X:$FFF7

15 14 13 12 11 10 9 8
GDD7 GDD6 GDD5 GDD4 GDD3 GDD2 GDD1 GDD0

23 22 21 20 19 18 17 16
GC7 GC6 GC5 GC4 GC3 GC2 GC1 GC0

AA0441.11

Figure 7-1 GPIO Control/Data Register

7.3 GPIO REGISTER (GPIOR)

The GPIO Register (GPIOR) is a 24-bit read/write control/data register used to

operate and configure the GPIO pins. The control bits in the GPIOR select the
direction of data transfer for each pin, whereas the data bits in the GPIOR are used to
read from or write to the GPIO pins. Hardware reset and software reset clear all the
bits in GPIOR. The GPIOR bits are described in the following paragraphs.

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GPIO
GPIO Register (GPIOR)

7.3.1 GPIOR Data Bits (GD[7:0])—Bits 7–0

The read/write GPIO Data bits (GD[7:0]) are used to read from or write to the
corresponding GPIO[7:0] pins. If the GPIOx pin is defined as an input, the GDx bit
will reflect the logic value present on the GPIOx pin. If the GPIOx pin is defined as an
output, the GPIOx pin will reflect the value written to the GDx bit. The GD[7:0] bits
are cleared during hardware reset and software reset.

7.3.2 GPIOR Data Direction Bits (GDD[7:0])—Bits 15–8

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The read/write GPIO Data Direction bits (GDD[7:0]) select the direction of data
transfer for each of the GPIO[7:0] pins (see Table 7-1). When the GDDx bit is cleared,
the corresponding GPIOx pin is defined as an input. When the GDDx bit is set, the
corresponding GPIOx pin is defined as an output. The GDD[7:0] bits are cleared
during hardware reset and software reset.

Table 7-1 GPIO Pin Configuration

GDDx GCx GPIO Pin Definition

0 0 Disconnected

0 1 Input

1 0 Standard active high/active low output

1 1 Open-drain output

7.3.3 GPIOR Control Bits (GC[7:0])—Bits 23–16

The read/write GPIO Control bits (GC[7:0]) select the type of output buffer for each
of the GPIO[7:0] pins when the pins are defined as outputs, and select whether or not
the input buffer is connected to the pin when the pin is defined as an input.

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GPIO
GPIO Register (GPIOR)

• When the GCx bit is cleared and the GDDx bit is cleared (the pin is defined as
an input), the corresponding GPIOx pin input buffer is disconnected from the
pin and does not require an external pull-up (see Table 7-1 and Figure 7-2).
• When the GCx bit is set and the GDDx bit is cleared (the pin is defined as
input), the corresponding GPIOx pin input buffer is connected to the pin (see
Table 7-1 and Figure 7-2).
• When the GCx bit is cleared and the GDDx bit is set (the pin is defined as
output), the corresponding GPIOx pin output buffer is defined as a standard
active high/active low type (see Table 7-1 and Figure 7-2).
• When the GCx bit is set and the GDDx bit is set (the pin is defined as output),
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the corresponding GPIOx pin output buffer is defined as an open-drain type

(see Table 7-1 and Figure 7-2).
The GC[7:0] bits are cleared during hardware reset and software reset.

GDD
GC
GDD

GD0–GD7 Buffer
Control* PIN

GDD

* See Table 7-1 GPIO Pin Configuration. AA0442k

Figure 7-2 GPIO Circuit Diagram

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GPIO
GPIO Register (GPIOR)
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