UNIT-1

Higher dose of boron implemented into base collector region. This causes contact resistance
&

extrinsic base region resistance [ ]

a) Decreased b) Increased c) not effected d) Inversed

2. Chan stop regions implemented in silicon to increase [ ]

a) Isolation b) Resistance c) Capacitance d) conduction

3. Starting material for bipolar IC Technology is

a) <111> b) <101> c) <011> d) <110> [ ]

4. Starting material for CMOS Technology is

a) <100> b) <101> c) <110> d) <111> [ ]

5. Decomposing of BJT in CMOS Technique results ------- latch up

a) Prevention b) Formation [ ]

c) PNPN structure function b) Formation of BJT

6. ------------ is used as gate material

a) Polysilicon b) Si c) Cu d) Al [ ]

7. Trench isolation effectively ---------------- bipolar transistors

a) Decouples b) Couples c) Forms d) Lower resistance [ ]

8. Purpose of Pad oxide is

a) Improve adhesiveness b) Decrease adhesiveness [ ]

c) Coupling d) De-coupling

9. Self aligned structure results

a) Decrease the overlap capacitance b) increase the overlap capacitance [ ]

c) Increase Capacitance & Resistance d) Decrease Capacitance & Resistance

10. NMOS starting material

a) <100> b) <111> c) <101> d) <110> [ ]

11. Hot electron effect cause

a) Degradation of gate material b) Increase the life of gate [ ]

c) Decrease Capacitance d) Decrease inductance

12. Boron used to adjust the

a) Threshold voltage b) Current c) Power d) Inductance [ ]

13. Which MOS transistor passes strong logic ‘1’ [ ]

a) pMOS b) nMOS c) (a) & (b) d) None

14. Pinchoff occurs in ---------------------- region [ ]

a) Non saturation b) Saturation c) cutoff d) linear

15. The drain current flow in ideally independent of drain –source voltage when the channel
is --------------- [ ]

a) strongly depleted b) weakly depleted c) strongly inverted d) weakly inverted

16. ------------------------- process is used to transfer the layout pattern from masks to wafer. [ ]

a) Diffusion b) Isolation c) photolithographic d) metallization

17. According to Moore’s law, the number of transistors that could be manufactured on a
chip [ ]

a) linearly decreases b) grows exponentially c) grows linearly d) decreases exponentially

18. The transistor threshold voltage, VT is ----------------------- for P type transistor.

a) positive b) negative c) zero d) Infinity [ ]

19. The present feature size of a transistor is ----------------- [ ]

a) 0.5 m b) 0.13 m c) 0.75 m d) 1 m

20. Pick out the advantage of IC [ ]

a) Smaller physical size b) Low power consumption c) Reduced cost d) All

21. In the MOSFET, as width of channel increases Id [ ]

a) Increases b) decreases c) Constant d) none

22. Latch – up is caused by [ ]

a) Parasitic R b) Parasitic BJT’s c) (a) & (b) d) Parasitic C

23. Pick up latch-up resistant CMOS process [ ]

a) n well b) p well c) silicon on Insulator d) all

24. Cascaded inverters are used to drive large _____________ loads [ ]

a) Capacitive b) resistive c) inductive d) all

25. In which process (CMOS) pFETs are embedded in n well [ ]

a) p well b) n well c) SOI d) all

26. In the Pseudo-nMOS logic ----------- transistor is used as pull-up resistor [ ]

a)pMOS b) nMOS c) Bipolar d) Unijunction

27. Latch structure is used in ------------ Logic [ ]

a)Pseudo-nMOS b) DCVS c) Domino d) all

28. Routing channel is spacing between [ ]

a)cell rows b) cells c) wires d) None

29. Feed throughs are used during [ ]

a)Placement b) Routing c) Floor planning d) Synthesis

30. For n-type transistor threshold voltage is ______________ [ ]

a) Positive b) negative c) zero d) none

31. In the twin tub process ____________ wafer is used [ ]

a) p-doped b) n-doped c) undoped d) none

UNIT-2

1.The smallest feature size of a transistor is [ ]

a) 4 x 4 b) 2 x 2 c) 8 x 8 d) 1 x 1

2.The on resistance of pulling transistor in an nmos inverter is [ ]

a) 10K b) 50K c) 40K d) 20K

3.The inverter pair delay for inverter having 4:1 ratio is [ ]

a) 4 b) 1 c) 2  d) 5

4.The rise time to fall time ratio is given by ----------------------

5.Metal to metal contact is called --------------- [ ]

a) Buried contact b) Butting contact c) Via d) contact out

6.The capacitance that is caused by the edges of conductor is --------------- capacitance.

a) Fringing field capacitance b) Diffusion capacitance [ ]

c) Gate to channel capacitance d) Area capacitance.

7.Measure of quality of logic circuit family is [ ]

a) Speed power product b) Voltage c) Days d) Current

8.Elmore delay model E =

9.------------------ model is used to compute delay [ ]

a) RC Transmission line b) R model c) L model d) C model

10.The following is one of the method for CMOS Technology

a) Twin tub b) Three tub c) Four tub d) Five tub [ ]

11.In Bi-polar Technology ----------- is used to get small diffusion coeffecient

a) Antimony b) Phosphorous c) Gold d) Copper [ ]

12.Base Collector capacitance can be minimized is n epitaxial layer is

a) Lightly doped b) Heavily doped c) Moderate d) no doping [ ]

13.Burried layer sheet resistance is

a) 5 to 15  / Sq b) 1 to 3  / Sq c) 1 to 5/Sq d) none [ ]

14.---------------- is used as Passivation layer [ ]

a) Si3N4 b) Si c) Si N d) Si2O2

15. In CMOS inverter to have equal raise & fall times , Wp is approximately equal to

a) (23) Wn b) Wn c) (34) Wn d) Wn/2 [ ]

16. Power Consumption of CMOS circuits depends on [ ]

a) Switching frequency b) load capacitance c) Supply voltages d) all

17. Quality of logic circuit family is [ ]

a) Delay X power dissipation b) delay / power dissipation

c) power dissipation / delay d) Delay + power dissipation.

18. Cascaded inverters are used to drive large _____________ loads [ ]

a) Capacitive b) resistive c) inductive d) all

19. In which process (CMOS) pFETs are embedded in n well [ ]

a) p well b) n well c) SOI d) all

20. Latch – up is caused by [ ]

a) Parasitic R b) Parasitic BJT’s c) (a) & (b) d) Parasitic C

UNIT-3

1. Electromigration of metal leads to _____ circuit. [ ]

a) Open b) short c) Amplifier d) Rectifier

2. Design rules are geometrical constraints on [ ]

a) stick diagram b) Layout c) circuit d) program

3. Circuit extractor extracts [ ]

a) Component b) wire c) (a) & (b) d) Nothing

4. In which gates operation is independent of stored charge [ ]

a) Dynamic b) static c) Complementary d) all

5. If pullup network consist of series connected nFETs, the gate is [ ]

a) NAND b) NOR c) NOT d) None

6. Dual of parallel connection is [ ]

a) Parallel b) Series c) Series-parallel d) none

7. In CMOS inverter to have equal raise & fall times , Wp is approximately equal to

a) (23) Wn b) Wn c) (34) Wn d) Wn/2 [ ]

8. Power Consumption of CMOS circuits depends on [ ]

a) Switching frequency b) load capacitance c) Supply voltag

9 Microelectronic technology cannot be characterized by

a) minimum feature size
b) power dissipation
c) production cost
d) designing cost

10. Which model is used for scaling?

a) constant electric scaling
b) constant voltage scaling
c) costant electric and voltage scaling
d) costant current model

11 α is used for scaling

a) linear dimensions
b) vdd
c) oxide thickness
d) non linear

12. For constant voltage model,

a) α = β
b) α = 1
c) α = 1/β
d) β = 1

13. For constant electric field model,

a) β = α
b) α = 1
c) α = 1/β
d) β = 1

14. Gate area can be given as

a) L/W
b) L * W
c) 2L/W
d) L/2W

7. Gate area is scaled by

a) α
b) 1/α
c) 1/α2
d) α2

8. Gate capacitance per unit area is scaled by

a) α
b) 1
c) 1/β
d) β

9. Current density J is scaled by

a) α/β
b) β/α
c) α2/β
d) β2/α

10. In constant voltage model, the saturation current is scaled by

a) α
b) β
c) 1
d) β2

11. In constant electric field model, power dissipation per unit area is scaled by
a) α
b) β
c) 1
d) β2

12. As the channel length is reduced in a MOS transistor, depletion region width must be

a) increased
b) decreased
c) must not vary
d) exponentially decreased

13. If doping level of substrate Nb increases then depletion width

a) increases
b) decreases
c) does not change
d) increases and then decreases

14. The size of a transistor is usually defined in terms of its

a) channel length
b) feature size
c) width
d) thickness ‘d’

15. Drift velocity can be given as

a) E/µ
b) µ/E
c) µ * E
d) E

16. The transit time can be given as

a) 2d
b) 2d/µE
c) µE/d
d) µE/2d

17. Maximum transit time occurs when the size of the transistor is
a) minimum
b) maximum
c) does not depend on size
d) double

18. The breakdown voltage can be reduced by _____ electric field strength
a) increasing
b) decreasing
c) does not depend
d) exponentially decreasing

19. The increase in operating frequency results in ______ in cross-talk noise

a) increase
b) decrease
c) no change
d) doubling

20. Scaling affects _____ generate noise

a) internally
b) externally
c) internally and externally
d) does not generate

UNIT-4

1. The subsystem of the circuits should have ______ interdependence

a) minimum (b) maximum (c) no (d) more

2. Switch logic is based on

a) pass transistors (b) transmission gates (c) pass transistors and transmission gates
d) design rules

3. The switch logic approach takes _____ static current

a) low (b) more (c) no (d) very less

4. Power dissipation in switch logic is

a) less (b) more (c) high (d) very less

5. Features of switch logic approach

a) occupies more area (b) no undesirable threshold voltage (c) low power dissipation
d) all of the mentioned

6. Pass transistor can be driven through _____ pass transistors

a) one (b) no (c) more (d) two

7. Switch logic approach is fast for

a) large arrays (b) small arrays (c) very large arrays (d) not at all fast for any type

8. Switch logic is designed using

a) complementary switches (b) silicon plates (c) conductors (d) resistors

9. Gate logic is also called as

a) transistor logic (b) switch logic (c) complementary logic (d) restoring logic

10. The CMOS inverter has _____ power dissipation

a) low (b) more (c) no (d) very less

11. As the number of inputs increases, the NAND gate delay

a) increases (b) decreases (c) does not vary (d) exponentially decreases

12. In CMOS NAND gate, p transistors are connected in

a) series (b) parallel (c) cascade (d) random

13. BiCMOS is used for ____ fan-out

a) less (b) more (c) no (d) very less
14. Which can handle high capacitance load?
a) NAND (b) nMOS NAND (c) CMOS NAND (d) BiCMOS NAND

15. Which gate is faster?

a) AND (b) NAND (c) NOR (d) OR

16. In Pseudo-nMOS logic, n transistor operates in

a) cut off region (b) saturation region (c) resistive region (d) non saturation region

17. The power dissipation in Pseudo-nMOS is reduced to about ____ compared to nMOS
device

a) 50% (b) 30% (c) 60% (d) 70%

18. In dynamic CMOS logic _____ is used

a) two phase clock (b) three phase clock (c) one phase clock (d) four phase clock

19. In clocked CMOS logic, output in evaluated in

a) on period (b) off period (c) both periods (d) half of on period

20. In clocked CMOS logic, rise time and fall time are
a) faster (b) slower
c) faster first and then slows down (d) slower first and then speeds up

21. In CMOS domino logic _____ is used

a) two phase clock (b) three phase clock
c) one phase clock (d) four phase clock

22. CMOS domino logic is same as ______ with inverter at the output line
a) clocked CMOS logic (b) dynamic CMOS logic
c) gate logic (d) switch logic

23. CMOS domino logic occupies

a) smaller area (b) larger area
c) both of the mentioned (d) none of the mentioned
24. CMOS domino logic has
a) smaller parasitic capacitance (b) larger parasitic capacitance
c) low operating speed (d) very large parasitic capacitance

25. In CMOS domino logic _______ is possible

a) inverting structure (b) non inverting structure
c) inverting and non inverting structure (d) very complex design

27. Clocked sequential circuits are

a) two phase overlapping clock (b) two phase non overlapping clock
c) four phase overlapping clock (d) four phase non overlapping clock

26. CMOS domino logic can be expressed diagramatically as

a) 

b) 
c) 

d)

28. Which are easier to design?

a) clocked circuits (b) asynchronous sequential circuits
c) clocked circuits with buffer (d) asynchronous sequential circuits with buffers

29. _____ is used to drive high capacitance load

a) single polar capability (b) bipolar capability
c) tripolar capability (d) bi and tri polar capability

30. For signals which are updated frequently _____ is used

a) static storage
b) dymanic storage
c) static and dynamic storage
d) buffer

31. Clock line drivers has ____ source of drive

a) one (b) two (c) three (d) none

32. Low L:W ratio results in ____ transistors

a) smaller (b) bigger (c) size doesnt depend on ratio (d) less effective

33. Which device is frequency dependent?

a) nMOS (b) CMOS (c) BiCMOS (d) pMOS
34. The below circuit belongs to which logic

a) PMOS logic for complement of (AB+C) (b) NMOS logic for complement of (AB+C)
c) PMOS logic for complement of (A+B).C (d) NMOS logic for complement of (A+B).C

35. The below symbol corresponds to

a) CMOS Transmission gate (b) NMOS Pass transistor logic

c)PMOS Transmission gate (d) NMOS Transmission gate

37. The CMOS gate circuit of NOR gate is:

a)

b)

c)
d)

37. The CMOS gate circuit of Nand gate is:

a)

b)

c)

d)
38. IR drops brings ______ in noise margin
a) increase (b) decrease (c) does not affect (d) stabilisation

39. The CMOS gate circuit of NOT gate is:

a) 

b) 

c) 

d) 

40. In CMOS logic circuit the n-MOS transistor acts as:

a) Load (b) Pull up network (c) Pull down network (d) Not used in CMOS circuits

UNIT-5
1. The circuit should be tested at
a) design level (b) chip level (c) transistor level (d) switch level

2. ……………. cannot be fabricated on an IC

a) Transistors
b) diodes
c) Resistors
d)Inductors and tranformers

3. Partitioning into subsystems are done at

a) design stage (b) prototype stage (c) testing stage (d) fabrication stage

4. ICs are generally made of ……………

a) Silicon (b) Germanium (c) Copper (d) All

5. Stuck open (off) fault occur/s due to _________

a) An incomplete contact (open) of source to drain node
b) Large separation of drain or source diffusion from the gate
c) Both a and b
d) None of the above

6. In testability, which terminology is used to represent or indicate the formal evidences of
correctness?
a) Validation (b) Verification (c)Simulation (d) Integration

7. What are the dominant faults in diffusion layers?

a) short citcuit faults (b) open circuit faults (c) short and open circuit faults
d) power supply faults

8. Test pattern generation is assisted using

a) automatic test pattern generator (b) exhaustive pattern generator
c) repeated pattern generator (d) loop pattern generator

9. _________ is the fundamental architecture block or element of a target PLD.

a) System Partitioning (b) Pre-layout Simulation (c)Logic cell (d) Post-layout Simulation

.

10. In Net-list language, the net-list is generated _______synthesizing VHDL code.

a) Before (b) At the time of (during) (c)After (d) None of the above

11. Which IC technology is very complex to design
a) Full Custom (b) Semi custom (c) Standard cell design (d) FPGA

12. Which model is used for pc board testing?

a) stuck at (b) stuck in (c) stuck on (d) stuck through

13. The input signal combination in exhaustive testing is given as

where N is number of inputs

a) 2N
b) 21/N
c) 2(M+N)
d) 1/2N

14. Observability is the process of

a) checking all inputs (b) checking all outputs (c) checking all possible inputs
d) checking errors and performance

15.The design flow of VLSI system is

1. architecture design 2. market requirement 3. logic design 4. HDL coding
a) 2-1-3-4 (b) 4-1-3-2 (c) 3-2-1-4 (d) 1-2-3-4

16.Which among the following operation/s is/are executed in physical design or layout
synthesis stage?
a) Placement of logic functions in optimized circuit in target chip
b) Interconnection of components in the chip
c) Both a and b (d) None of the above

17. what is the logic implemented using below look up table

a) AND (b) OR (c) EXOR (d) EXNOR

18. In floorplanning, placement and routing are __________ tools.

a) Front end (b) Back end (c) Both a and b (d) None of the above

19. Infloorplanning, which phase/s play/s a crucial role in minimizing the ASIC area
and the interconnection density?
a) Placement (b) Global Routing (c) Detailed Routing (d) All of the above

20. ASIC stands for…

A) application-specific integrated circuit (B) array-specific integrated circuit
C) application-scientific integrated circuit (D) array-scientific integrated chip

21. Which constitutes the test vectors in sequential circuits?

a) feedback variables (b) delay factors (c) test patterns (d) all input combinations

22. below diagram belongs to which category

a) Standard cell based (b)FPGA (c)FULL CUSTOM (d) All

23. Routing technique used in below diagram belongs to which IC technology

a) ASIC (b)FPGA (c)FULL CUSTOM ( d) All

24. Routing technique used in below diagram belongs to which IC technology [L2]
a) Channelled gate array (b)Channel less gate array (c)Structured gate array (d) Channelling
Gate array

25. Routing technique used in below diagram belongs to which IC technology

a) Channelled gate array (b)Channel less gate array (c)Structured gate array (d) Channelling
Gate array

26. Routing technique used in below diagram belongs to which IC technology

a) Channelled gate array (b)Channel less gate array (c)Structured gate array (d) Channelling
Gate array

27. What is the correct flow of FPGA

1. HDL coding 2. Netlist 3. bit stream 4. Synthesis 5. routing 6. Placement 7.Mapping 8.
Programming FPGA
a) 1-4-2-6-7-3-5-8 (b) 1-4-2-6-7-5-3-8 (c) 1-4-6-7-2-5-3-8 (d) 1-4-2-7-6-5-3-8

28. below diagram belongs to which category [L3]

a) ASIC (b)FPGA (c)FULL CUSTOM (d) All

29. Which IC technology is very easy to design

a) Full Custom (b) Semi custom (c) Standard cell design (d) FPGA

30. The sequential circuit operates in _____ mode/modes of operation

a) only one (b) two (c) three (d) four

31. The efficiency of the test pattern generation is improved by

a) adding buffers (b) adding multipliers (c) partitioning (d) adding power dividers

32Which IC technology is Fastest

a) Full Custom (b) Semi custom (c) Standard cell design (d) FPGA

33. ATPG stands for:

a) Attenuated Transverse wave Pattern Generation (b) Automatic Test Pattern Generator
c) Aligned Test Parity Generator (d) None of the mentioned

34. What is the inputs in the PLD is given through_______

a). OR gates b) NAND gates c). AND gates d). NOR gates

35. PAL stands for…

A. Programmable Array Logic (B) Programmable Logic Array

C. Programmable Array Loaded (D) None of these
36 Which IC technology consumes large area
a) Full Custom b) Semi custom c) Standard cell design d) FPGA

37. Which IC technology is configurable

a) Full Custom b) Semi custom c) Standard cell design d) FPGA

38. FPGA device are __________ type.

A) PLD (B) EPROM (C) SROM (D) SLD

39. FPGA stands for…

A. Field Program Gate Array (B). First Program Gate Array

C. Field Programmable Gate Array (D) First programmable Gate Array

40. Which IC technology performs placement and routing tasks

a) Full Custom (b) Semi custom (c) CPLD (d) FPGA