Solar Energy 199 (2020) 645–656

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Solar Energy
journal homepage: www.elsevier.com/locate/solener

Grid-connected photovoltaic system employing a single-phase T-type T

cascaded H-bridge inverter
Aamir Amir, Asim Amir, Jeyraj Selvaraj, Nasrudin Abd Rahim
⁎

UM Power Energy Dedicated Advanced Centre (UMPEDAC), HICoE, Level 4, Wisma R&D, University of Malaya, Jalan Pantai Baharu, 59990 Kuala Lumpur, Malaysia

ARTICLE INFO ABSTRACT

Keywords: This paper presents the control and application of a single-phase T-type nine-level cascaded H-Bridge (TCHB)
T-type cascaded H-bridge multilevel inverter (MLI) topology. This paper focuses on the effectiveness of the TCHB and its control by
Photovoltaic (PV) system presenting the inverter operation based on a PI current controller along with a Maximum Power Point Tracking
Pulse Width-Modulation (PWM) (MPPT) scheme to realize a grid-tied photovoltaic (PV) system and a novel PWM method offering self-balancing
Nine-level inverter
at the DC-link capacitors. In order to attain gating signals for power transistors (IGBTs), the TCHB employs a
Grid-connected
PWM with one triangular carrier signal and eight reference signals. In addition, a mathematical modelling of the
PWM method, along with a theoretical explanation of the self-balancing process has also been provided. To
prove the effectiveness of the proposed TCHB topological design, it has been comparatively analysed against
other fundamental MLI and symmetric CHB topologies. In addition, to corroborate the working of the control
and the PV system application, employing TCHB inverter offering nine output voltage levels
( ± 2Vdc, ± 2¾Vdc, ± Vdc, ± ½Vdc, 0), simulation and hardware results have been presented.

1. Introduction
Solar energy attains a credible position as a renewable energy
source due to its reliability and cleanliness (Kabir et al., 2018; Hansen
and Vad Mathiesen, 2018; Lazzarin and Noro, 2018). PV systems in-
volving grid-connected inverters can deliver such electrical energy to
the power distribution networks (Mirhosseini, 2019; Al-Shetwi et al.,
2019). Such systems can also employ MPPT techniques to harness op-
timum amount of energy from the PV modules (Elmelegi et al., 2019;
Öztürk et al., 2018; Cortajarena et al., 2017). Moreover, various MPPT
schemes and their working has been explained in (Amir et al., 2018;
Amir et al., 2016). Owing to the enhanced power quality, near sinu-
soidal outputs, high voltage capability, reduced common mode vol-
tages, number of semiconductor devices (transistors and diodes) and
number of gate driver the concept of MLI has attained central im-
portance for grid-integrated PV systems (Fernão Pires et al., 2018.;
Sinha et al., 2018; Ravi et al., 2011/11/01/ 2011.). Such inverters have
also been implemented in three phase (Shi et al., 2017).
The fundamental MLI topologies remain the diode clamped or
neutral point clamped (NPC) (J. Alonso-Martı́nez et al., 2010.;
Tsengenes and Adamidis, 2011/11/01/ 2011.); capacitor clamped or
flying capacitor (FC) (Sinha et al., 2018; Aly and Ramadan, 2019;
Prabaharan et al., 2019), and the CHB (Kaliamoorthy et al., 2014; Ma
et al., 2019). The shortcomings of the NPC include the prerequisite of a
BVS control circuitry and an increased voltage across clamped diodes.
Transformerless operation and redundant phase leg states remain the
advantage of the FC topology (Prabaharan et al., 2019; Antoniewicz
et al., 2016). However, shortcomings include a high number capacitors
for increased voltage levels. In addition, CHB inverter is connection of a
number of H-bridges with symmetric or asymmetric dc power supplies.
Asymmetric MLI have been presented in (Kim and “A, , 2010/08/01/
2010.; Busarello et al., 2017; Boora et al., 2010). Here, unequal dc
voltage sources are employed to attain increased output voltage levels
with reduced size and cost. However, utilization of various asymmetric
MLI designs results into the loss of modularity and restricts the mod-
ulation and control method. For symmetric H-bridge topology, the
voltage sources are kept equal (Rodriguez et al., 2002). Owing to its
simplicity of control this MLI topology remains preferable for high level
applications. Fig. 1(a) presents the classification of the fundamental
MLI topologies based on common or separate dc sources and Fig. 1(b)
presents the classification of the modulation strategies for the MLI.
Symmetric MLI bring an additional requirement of DC-link capacitor
voltage balancing in order to ensure a better harmonic profile of the
output-current and voltage (Lee et al., 2018; Khoucha et al., 2011).
The most conventional MLI topology remains the full-bridge three-
level inverter. It can offer a multilevel output, while switching at a high

⁎
Corresponding author.
E-mail addresses: aamir.a@siswa.um.edu.my (A. Amir), jeyraj@um.edu.my (J. Selvaraj), nasrudin@um.edu.my (N. Abd Rahim).

https://doi.org/10.1016/j.solener.2020.02.045
Received 20 June 2019; Received in revised form 2 December 2019; Accepted 10 February 2020
Available online 24 February 2020
0038-092X/ © 2020 International Solar Energy Society. Published by Elsevier Ltd. All rights reserved.
A. Amir, et al. Solar Energy 199 (2020) 645–656

Nomenclature Voutp Inverter output voltage for positive cycle

I0 Reverse saturation current
MLI Multilevel Inverter Vout Inverter output voltage
PV Photovoltaic Am Peak-to-Peak amplitude of reference
TCHB T-type, nine-level, Cascaded H-Bridge l Number of voltage level synthesized
PWM Pulse Width-Modulation Vinv Inverter voltage before filter
CHB Cascaded H-Bridge Sn Number of Switches
BVS Balanced Voltage Sharing Ac Peak-to-Peak amplitude of carrier
FC Flying Capacitor Ig Grid Current
NPC Neutral Point Clamped Iref Reference current
PPV PV power Ma Modulation Index
VPV PV voltage VT Thermal voltage of diode
IPV PV current Vg Grid voltage
A Alternate path Z Summation of MPPT Variables
MPPT Maximum Power Point Tracking Zn MPPT variables
Phase angle Cn DC bus capacitor
Angular frequency Ln Boost Inductor
P&O Perturb and Observe Lf Filter Inductor
Impp Current at MPP KP Proportional constant
Ish Short circuit current Ki Integral constant
Voutn Inverter output voltage for negative cycle e Tolerance error
Voc Open circuit voltage

MLI

Separate DC sources Common DC sources

Modular Cascaded
CHB MLI NPC MLI FC MLI
Inverters

Multilevel
Modulation

Fundamental High Switching

Switching Frequency Frequency

Optimal Minimization Optimized Harmonic Space Vector Selective Harmonic

Space Vector Sinusoidal Pulse
of Total Harmonic Nearest Level Control Elimination Stepped Modulation – Pulse Elimination – Pulse
Modulation Width Modulation
Distortion Waveform Width Modulation Width Modulation

Carrier Based Reference Based 2D algorithm 3D algorithm

`
Single Carrier Multiple Carrier
3-leg Inverter 4-leg Inverter

Phase Shift Level Shift Hybrid Multiple

Sine PWM
Reference
Constant Frequency Variable Frequency Advanced PWM
Single
Reference
Alternative Phase Phase Opposition and Others
Phase Disposition Carrier Overlapping Variable Amplitude
Opposition and Disposition Disposition

b
Fig. 1. Classification of MLI topologies. (a) Fundamental MLI topologies, (b) Modulation Control Schemes.

frequency. However, the acoustic noise, power losses, and device in-
terferences leave the three-level inverter with huge demerits.
This paper recounts the development of the conventional three-level
MLI by proposing the single-phase T-type, nine-level, cascaded H-
Bridge (TCHB) multilevel inverter (MLI) topology, along with its con-
trol and application for a PV system. The TCHB utilizes two T-type
bidirectional switches as presented in Fig. 2, consequently declining
number of semiconductor switches and diodes. It has been
comparatively analysed against other fundamental MLI topologies to
display its effectiveness by considering the parameters of number of
IGBTs utilized, number of diodes employed, DC buses utilized and the
balancing capacitors involved in each topology. Objectives of the re-
search article are:
1. To present a single-phase T-type cascaded nine-level (TCHB) grid
connected inverter.

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A. Amir, et al. Solar Energy 199 (2020) 645–656

DC-DC Table 1
PV Strings Converter TCHB
Comparison of TCHB against NPC, FC, and CHB inverter topologies.
PV1 S1 S2 Sg
L1 D1 C1 Inverter Number of IGBTs Number of diodes Balancing Capacitors DC bus
Lf
S1 * TCHB 12 0 0 2
SB1
Vgrid NPC 16 28 0 1
S3* FC 16 0 28 1
C2 CHB 16 0 0 4
S3 S4

PV2 L2 S6
D2 C3 S5 Vout , o = abVc (3)

S5*
SB2 3b 2 + 2b
Vstand = + 4b V forb: even
S7 * 8 c (4)
C4 S7 S8 Vstand, i = aVstand (5)

Fig. 2. Proposed single-phase TCHB grid-tied inverter topology. where Vc is voltage on each capacitor, Nlevel output-voltage levels, NIGBT
semiconductor switches employed, b capacitors in each cascade, a the
number of cascades, Vout , o is the optimum output voltage, Vstand semi-
2. Comparatively analyse TCHB against other fundamental MLI
conductor switches standing voltage of each cascade and Vstand, i
topologies.
standing voltage of all switches of the inverter. Fig. 3(a) presents the
3. State a novel PWM switching technique with one triangular carrier
graphical plot of Nlevel against NIGBT , Fig. 3(b) the plot of Nlevel against
and eight references.
Ndevice (number of switches and diodes) and Fig. 3(c) the plot of Nlevel
4. Provide mathematical modelling of the inverter operation and PWM
against Vstand, i , while comparing the TCHB with the Symmetric Switch
method.
Capacitor H-Bridge Topology (SCHB) (Samanbakhsh and Taheri, 2016)
and the Symmetric Conventional Cascaded H-Bridge (CCHB). Con-
The following paper is as follows: Section 2 introduces the proposed
sidering the CCHB, TCHB offers higher levels of output-voltage at re-
MLI design and comparatively analyses it against other MLI topologies.
duced number of devices, while CCHB attains the best standing voltage
Section 3 investigates the proposed PWM switching technique and
characteristics. By contrast, the SCHB can provide higher output-vol-
theoretically analyses its effectiveness for self-voltage balancing.
tage levels at fewer numbers of devices, yet the SCHB has higher
Section 4 discusses the entire control system with an MPPT algorithm
standing voltage on the switches.
based on P&O technique, and a PI based current controller. In addition,
Reduced number of switches and diodes with effective high power
the performance parameters of the PV module employed have also been
application and improved current and voltage harmonic levels makes
given. Here a SIEMENS SP-75 module has been utilized. Simulation and
the TCHB an effective choice for a PV system application. To boost the
experimental results are presented in Section 5 and Section 6, respec-
voltage to the grid requirements, two Dc–Dc boost converters were
tively, to corroborate the effective performance of the proposed TCHB
utilized. Various high voltage boost converters have been presented in
PV system. Lastly, Section 7 presents the conclusion of the work.
(Amir et al., 2018; Amir et al., 2019.), here two basic boost converters
are employed. The converters were placed between the PV arrays and
2. Proposed MLI topology
each cascade of the inverter. A filtering inductance Lf was employed at
the output. Table1 presents a comparative analysis of TCHB against the
For symmetric MLI the basic necessity is to maintain the equivalent
conventional, nine-level, inverters, based on the number of IGBTs,
dc sources values. For TCHB inverter, two H-bridges, two T-Type bi-
diodes, balancing capacitors and DC buses involved.
directional switches, and four voltage-dividing capacitors have been
Therefore, by utilizing a suitable PWM control for the cascaded
utilized. Each cascade possesses one T-type bidirectional switch and
inverter, nine output-voltage levels were produced. Nine switching
two capacitors, as presented in Fig. 2. The proposed inverter design can
states define the operation for the proposed inverter, as presented in
be modelled as:
Fig. 4(a)–(d) for Vout > 0 and in Fig. 5(a)-(d) for Vout < 0 . The proposed
Vc1 = Vc 2 = Vc TCHB MLI operates through eight modes. The modes are described as:
Nlevel = 2ab + 1 (1) Mode1: 0 < t 1 and 6 t , Mode2: 1 t 2 and 5 t
NIGBT = 2a (b + 1) (2) 6

Fig. 3. Comparative analysis of TCHB against CCHB and SCHB. (a) Nlevel against NIGBT , (b) Nlevel against Ndevice , (c) Nlevel against.Vstand,i

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Fig. 4. Modes of operation for Vinv > 0. (a) 2Vdc (S1, S4, S5 and S8 are ON, with S5 and S5* alternating), (b) 2¾Vdc (S1, S4, S8 and the bidirectional T-type switch
formed by S5* and S7* is ON, with S7 and S7* alternating), (c) Vdc (S1, S4, S7 and S8 are ON, with S1 and S1* alternating), (d) ½Vdc (S4, S7 and S8 and the
bidirectional T-type switch formed by S1* and S3* is ON, with S3 and S3* alternating).

Fig. 5. Modes of operation for Vinv < 0. (a) -½Vdc (S2, S5, S6 and the bidirectional T-type switch formed by S1* and S3* is ON, with S1 and S1* alternating), (b)
-Vdc (S2, S3, S5 and S6 are ON, with S3 and S3* alternating), (c) −2¾Vdc (S2, S3, S6 and the bidirectional T-type switch formed by S5* and S7* is ON, with S5 and
S5* alternating), (d) −2Vdc (S2, S3, S6 and S7 are ON, with S7 and S7* alternating).

Table 2
Input capacitor current, linked with the output current, against switching states for the TCHB converter.
Iout S1 S1* S3 S3* S2 S4 S5 S5* S7 S7* S6 S8

Ic2 = -Iout ^ 0 OFF ON A A OFF ON OFF ON ON OFF OFF ON

Ic1 = Ic3 = Ic4 = 0
Ic1 = -Iout ^ 0 A A OFF ON OFF ON OFF ON ON OFF OFF ON
Ic3 = Ic4 = 0, Ic2 = -Iout
Ic4 = -Iout ^ 0 ON OFF OFF ON OFF ON OFF ON A A OFF ON
Ic3 = 0, Ic1 = Ic2 = -Iout
Ic3 = -Iout ^ 0 ON OFF OFF ON OFF ON A A OFF ON OFF ON
Ic1 = Ic2 = Ic4 = -Iout
Ic1 = Ic2 = Ic3 = Ic4 = 0 OFF ON ON OFF OFF ON OFF ON ON OFF OFF ON
Ic4 = Ic3 = Ic2 = Ic1 = 0* ON OFF OFF ON ON OFF ON OFF OFF ON ON OFF
Ic4 = Iout ^ 0 OFF ON ON OFF ON OFF OFF ON A A ON OFF
Ic1 = Ic2 = Ic3 = Iout
Ic3 = Iout ^ 0 OFF ON ON OFF ON OFF A A OFF ON ON OFF
Ic4 = 0, Ic1 = Ic2 = Iout
Ic2 = Iout ^ 0 OFF ON A A ON OFF ON OFF OFF ON ON OFF
Ic3 = Ic4 = 0, Ic1 = Iout
Ic1 = Iout ^ 0 A A OFF ON ON OFF ON OFF OFF ON ON OFF
Ic2 = Ic3 = Ic4 = 0

Mode3: 2 < t 3 and 4 t 5, Mode 4: 3 t 4 Table.2 shows the input-capacitor-current, linked with output-cur-
rent, against switching states. The notation “A” represents the alternate
Mode5: < t 7 and 12 t 2 , Mode6: 7 t 8 and 11 t switching state during a specified mode of operation. For Fig. 4 and
12 Fig. 5, the red track represents the current path for the specific mode of
operation to attain the desired maximum voltage output, while the blue
Mode7: < t 9 and 10 t 11, Mode8: t
8 9 10
track represents the alternating path for the particular mode. Required

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Table 3
Range of Modulation Index and Phase Angle Displacement.
Range Ma < 0.25 0.25 < Ma < 0.5 0.5 < Ma < 0.75 Ma > 0.75
of Ma

θ1 sin 1 ( Ac ) sin 1 ( Ac ) sin 1 ( Ac )

2 Am Am Am
θ2 sin 1 ( 2Ac ) sin 1 ( 2Ac )
2 2 Am Am
θ3 sin 1 ( 3Ac )
2 2 2 Am
θ4 π- 3
2 2 2
θ5 π- 2 π- 2
2 2
θ6 π- 1 π- 1 π- 1
2
θ7 3 π+ 1 π+ 1 π+ 1
2
θ8 3 3 π+ 2 π+ 2
2 2
θ9 3 3 3 π+ 3
2 2 2
θ10 3 3 3 2π- 3
2 2 2
θ11 3 3 2π- 2 2π- 2
2 2
θ12 3 2π- 1 2π- 1 2π- 1
2

Fig. 6. Nine-Level Inverter PWM. (a) PWM Switching Signal Generation, (b)
Phase Angle for Vout.
output-voltage with nine-levels was attained as:
1) 2Vdc positive output - S1, S4, S5 and S8 are ON, with S5 and S5*
alternating. Here, S1 connects load positive terminal to VC1, and S8
forms a path to connect load negative to ground terminal of VC4.
Current path in red of Fig. 4(a) displays when the output voltage is
2Vdc and the alternating path in blue when the output is 2¾Vdc.
2) 2¾Vdc positive output - The bidirectional T-type switch formed by
S5* and S7* is ON, with S7 and S7* alternating. Here, switching
states for the first cascade remain unchanged from the preceding
state. However, the load negative terminal, through S8, connects to
the ground of Vdc2. Current completes its path through the bidir-
ectional switch, which offers a trimmed voltage. Fig. 4(b) shows the
current paths in red when the output voltage is 2¾Vdc and the al-
ternating path in blue when the output is Vdc.
3) Vdc positive output - S1, S4, S7 and S8 are ON, with S1 and S1*
alternating. Switches S7 and S8 form a closed circuit path through
the second cascade. Fig. 4(c) presents current path in red when the
output voltage is Vdc and the alternating path in blue when the
output is ½Vdc.
4) ½Vdc positive output - Bidirectional T-type switch formed by S1*
and S3* is ON, with S3 and S3* alternating. Here, switching states
for the second cascade remain unchanged from the preceding state.
The load positive terminal connects to Vdc1 via the bidirectional
switch offering a trimmed voltage. Fig. 4(d) shows the current paths
in red when the output voltage is ½Vdc and the alternating path in
blue when the output is Zero.
5) -½Vdc negative output - Bidirectional T-type switch formed by S1*
and S3* is ON, with S1 and S1* alternating. However, S5 and S6
offer a short circuit path in the second cascade. The load terminal
connects to Vdc1 via the bidirectional switch, completing its path
through S2. Fig. 5(a) shows the current paths in red when the output
voltage is -½Vdc and the alternating path in blue when the output is
Zero.
6) -Vdc negative output - S2, S3, S5 and S6 are ON, with S3 and S3*
alternating. Here, switching states for the second cascade remain
unchanged from the preceding state. The current passing from S2
completes its path through S3. Fig. 5(b) shows the current paths in
red when the output voltage is -Vdc and the alternating path in blue
when the output is -½Vdc.
7) −2¾Vdc negative output - The bidirectional T-type switch formed
by S5* and S7* is ON, with S5 and S5* alternating. Here, switching
states for the first cascade remain unchanged from the preceding
state. However, the load positive terminal, through S6, connects to
the ground terminal of Vdc1. The current completes its path through
the bidirectional T-type switch formed by S5* and S7*, which offers
a trimmed voltage. Fig. 5(c) shows the current path in red when the
output voltage is −2¾Vdc and the alternating path in blue when the
output is -Vdc.
8) −2Vdc negative output: S2, S3, S6 and S7 are ON, with S7 and S7*
alternating. Here, S3 forms a path to connect positive terminal of
load to VC1. In addition, S6 connects negative terminal of the load to
VC3. Fig. 5(d) shows the current paths in red when the output vol-
tage is −2Vdc and the alternating path in blue when the output is
−2¾Vdc.
3. PWM with Self-Voltage balancing
Fig. 6(a) presents the PWM switching signal generation introduced
for the TCHB topology. Eight reference signals, operating at equivalent
amplitude, frequency and phase, except for an offset value equal to that
of the carrier signal, were utilized and compared for intersections with
one carrier signal. Fig. 6(b) presents the Nine-Level Output-Voltage Vinv .

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A. Amir, et al. Solar Energy 199 (2020) 645–656

c
Fig. 8. Siemens SP-75 PV Module Characteristic Curves at constant temperature
and varying irradiance. (a) P-V curve, (b) I-V curve.

Table 4
Performance parameters of the PV Module
(Siemens SP-75).
Parameter Value

d VMPP 17.0 V
VOC 21.7 V
Fig. 7. Proposed Control System. (a) Control System, (b) P&O MPPT flowchart, IMPP 4.4 A
(c) Control System employed, (d) Switching Signal Generation. ISC 4.8 A
PMPP 75 W
No. of Panels 5in series
Here, S2, S4, S6 and S8 would operate at fundamental frequency and
Switches S1, S3, S1*, S3*, S5, S5*, S7 and S8 at the rate of carrier signal
frequency. The modulation index, Ma is given by (Lezana et al., 2008) Table 5
as: System parameters.

Am Parameter Value
Ma =
A c (l 1) (6) Switching Frequency 20 kHz
Sampling Frequency 78 kHz
where Ac remains the Peak-to-Peak amplitude of the carrier, Am re-
C1,2,3,4 2200 μF
mains the Peak-to-Peak amplitude of the reference signal, and l being L1,2 3 mH
number of voltage levels synthesized. Here, l = 5. Table.3 presents the Lf 5 mH
range on modulation index and phase angle displacement. At KP 10
Ma > 0.5&&Ma < 0.75, seven-levels of the output-voltage is attained, Ki 0.1
with lesser Ma five and three output-voltage levels can be achieved.
All signals are to be compared with the carrier signal to attain nine-

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A. Amir, et al. Solar Energy 199 (2020) 645–656

Signal
FFT window: 1 of 50 cycles of selected signal

100

-100

0.7 0.705 0.71 0.715

Time (s)

FFT analysis

Fundamental (50Hz) = 156.1 , THD= 15.46%

14

12
Mag (% of Fundamental)

10

0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Frequency (Hz) 4
x 10
a
S1 S2 Standing Voltage S1 Standing Voltage S2/S6
1 1 100 100

0.5 0.5
50 50
0 0
0 0.005 0.01 0.015 0.02 0 0.005 0.01 0.015 0.02
S3 S4 0 0
0 0.005 0.01 0.015 0.02 0 0.005 0.01 0.015 0.02
1 1
Standing Voltage S3 Standing Voltage S4/S8
0.5 0.5 100 100

0 0 50 50
0 0.005 0.01 0.015 0.02 0 0.005 0.01 0.015 0.02
S1* S3*
1 1
0 0
0 0.005 0.01 0.015 0.02 0 0.005 0.01 0.015 0.02
0.5 0.5
Standing Voltage S1* & S3* Standing Voltage S5
50 100
0 0
0 0.005 0.01 0.015 0.02 0 0.005 0.01 0.015 0.02
S5 S7 0 50
1 1

0.5 0.5 -50 0

0 0.005 0.01 0.015 0.02 0 0.005 0.01 0.015 0.02
0 0 Standing Voltage S7 Standing Voltage S5* & S7*
0 0.005 0.01 0.015 0.02 0 0.005 0.01 0.015 0.02
100 50
S5* S7*
1 1
50 0
0.5 0.5

0 0 0 -50
0 0.005 0.01 0.015 0.02 0 0.005 0.01 0.015 0.02 0 0.005 0.01 0.015 0.02 0 0.005 0.01 0.015 0.02
Time(s) Time(s) Time(s) Time(s)
b c
Fig. 9. Nine level TCHB. (a) Switching Frequency of Output-Voltage, (b) Switching Signals, (c) Standing Voltage on the Switches.

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A. Amir, et al. Solar Energy 199 (2020) 645–656

Vinv < Vgird

200
Voutn = Vc1 [ (S2 )(S1 )] + Vc 2 [ (S3 )(S2)] + Vc3 [ (S6 )(S5 )]
+ Vc 4 [ (S6 )(S7)] (11)
100
where Vc is voltage on each capacitor, Vout , o is the optimum output vol-
Vinv

0
tage, Voutp inverter output voltage for positive cycle, Voutn inverter output
-100 voltage for negative cycle, Sn is the switch.
The switching frequency of switches S8 = S4 = S6 = S2 , while oper-
-200 ating at fundamental frequency, and rest operate at switching fre-
0.7 0.702 0.704 0.706 0.708 0.71 0.712 0.714 0.716 0.718 0.72
quency of the output-voltage. In addition, S1 and S3 are 180 degrees
phase shifted, similarly S5 and S7 are phase shifted. Equations (10) and
4
consequently (11) offer complementary functions where each function
2 is represented as fn = (Si )(Sj ), wherei = 2, 4, 6, 8andj = 1, 3, 5, 7 . Such
a complementary switching operating at the switching frequency of the
0 output-voltage allows self-voltage balancing attaining BVS at the DC-
Ig

-2
Link capacitors.

-4
0.7 0.702 0.704 0.706 0.708 0.71 0.712 0.714 0.716 0.718 0.72
4. Control system of the proposed topology
Time(s)
a Fig. 7(a) displays the entire control system of the grid-tied T-type
Vinv > Vgird inverter. Fig. 7(b) presents the MPPT utilizing the P&O algorithm. In
200 addition, Fig. 7(c) presents the PI based current controller employed for
100
the grid-tied control system. Fig. 7(d) presents the switching signal
generation with eight reference signals compared with one carrier
signal.
Vinv

0
The employed MPPT algorithm is based on the P&O method. Where,
-100
the input PV current and the input PV voltage are measured as input
-200 values. Two separate MPPT algorithms, one for each cascade, are uti-
0.7 0.702 0.704 0.706 0.708 0.71 0.712 0.714 0.716 0.718 0.72 lized in the control system. In order to obtain the reference signal the
utility grid voltage Vg is transformed by multiplying it with the
4 variableZ . Where, the variable Z is attained by the summation of Z1 and
Z2 which are attained by separately applying the P&O MPPT scheme for
2
the two PV strings, respectively. By (12):
0
(12)
Ig

Z = Z1 + Z2
-2 Here, PV power has been taken as the deterministic parameter to in-
crement or decrement the variables Z1 and Z2 depending upon the input
-4
0.7 0.702 0.704 0.706 0.708 0.71 0.712 0.714 0.716 0.718 0.72 values measured. The variations in the input values are directly affected
Time(s)
by the atmospheric conditions. Fig. 8 presents the effects of changes in
b ambient irradiance and varying temperature on the input values, by
graphically displaying the Power-Voltage and Current-Voltage PV
Fig. 10. Output-Current and Voltage Results. (a) Simulation for Vout < Vgrid , (b)
characteristic curves.
Simulation for Vout > Vgrid .
The control system is employed for the optimum transference of
energy from the PV system to grid, while attaining a better output-
level output at Ma > 0.75&&Ma < 1. Considering modulation strategy current and voltage harmonic profile. Here, current injected into the
presented in Fig. 5, output-voltage of the inverter can modelled as: grid, Ig is the feedback signal for comparison with reference current Iref .
The error signal attained is provided to the PI controller.
Vout = Vc1 [(S1 )(1 S2 )(1 S1 ) (S2 )(1 S1 )(S1 )]
Subsequently the error signal Z , after passing through an antiwindup
+ Vc 2 [(S4 )(1 S3 )(S3 ) (S3 )(1 S4 )(1 S3 )] process forms reference signals. Here, the required PWM switching
+ Vc3 [(S5 )(1 S6 )(1 S5 ) (S6 )(1 S5 )(S5 )] signals are attained by the intersection of one carrier and the attained
reference signals. Such an approach offers almost-unity power factor for
+ Vc 4 [(S8 )(1 S7 )(S7 ) (S7 )(1 S8 )(1 S7 )] (7)
the inverter operation where Ig and Vg are in-phase. Here, the
(S1) = not (S1 ), (S2) = not (S4 ), (S3) = not (S3 ), (S5) = not (S5 ), (S6) Trapezoidal sum approximation is used for discrete-time domain
transformation. The utility grid voltage Vg is transformed into the re-
= not (S8), &(S7) = not (S7 ) ference signal by multiplying it with the variableZ as (13):

Vout = Vc1 [(S1 )(S4 )(S1) (S2 )(S1 )(S1 )] + Vc2 [(S4 )(S3 )(S3 ) (S3 )(S2 )(S3)] Iref = Vg Z (13)
+ Vc3 [(S5 )(S8 )(S5) (S6 )(S5 )(S5 )] + Vc 4 [(S8 )(S7 )(S7 ) (S7 )(S6 )(S7)] To ensure current injection into grid, a voltage level higher than
(8) 2 ofVgrid is required at the DC-bus. One the one hand, considering the
case where Vout < Vgrid current injection reverses from the grid into the
AsSn {0, 1}, (Sn )2 = Sn inverter. On the other hand, when the Vout increases or is made higher
than Vgrid for the case Vout > Vgrid the current is injected into the grid and
Vout = Vc1 [(S4 )(S1) (S2 )(S1 )] + Vc 2 [(S4 )(S3 ) (S3 )(S2)]
the Vgrid and Igrid are completely in-phase. Therefore, two boost con-
+ Vc3 [(S8 )(S5) (S6 )(S5 )] + Vc 4 [(S8 )(S7 ) (S6 )(S7 )] (9) verters, one for each individual cascade, are employed to step up in-
verter voltage Vinv . In addition, a 1:2 ratio transformer, after the filter
Voutp = Vc1 [(S4 )(S1)] + Vc 2 [(S4 )(S3 )] + Vc3 [(S8 )(S5)] + Vc 4 [(S8 )(S7 )] inductor, has also been place to ensure isolation from the grid and re-
(10) duce the common mode leakage current to a negligible level. Moreover,

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A. Amir, et al. Solar Energy 199 (2020) 645–656

Inverter Voltage, Nine-level with 0.75 < ma < 1.0

200

Vinv(V)
0

-200
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Inverter Output Current, Nine-level with 0.75 < ma < 1.0
2
Iload(A)

-2
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Inverter Output Voltage, Nine-level with 0.75 < ma < 1.0
200
Vo(V)

-200
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
time(s)
a
Signal Signal
Selected signal: 1 cycles. FFT window (in red): 1 cycles Selected signal: 1 cycles. FFT window (in red): 1 cycles

100 100

0 0

-100 -100

0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time (s) Time (s)

FFT analysis FFT analysis

Fundamental (50Hz) = 173.5 , THD= 2.56% Fundamental (50Hz) = 173.5 , THD= 2.56%
0.3

2 0.25
Mag (% of Fundamental)
Mag (% of Fundamental)

0.2
1.5

0.15
1

0.1

0.5
0.05

0 0
0 1 2 3 4 5 6 0 5 10 15 20 25 30 35 40 45 50
Frequency (Hz) 4 Harmonic order
x 10
b c
Fig. 11. Output-Current and Voltage Results. (a) TCHB on RL load, (b) FFT analysis with frequency, (c) FFT analysis with harmonic order.

Table 6
Comparative analysis of the proposed TCHB against various inverter topologies with an RL load, based on the parameters of THD and η.
Inverter Topology Level R (Ω) L (mH) Voltage THD % Current THD % %

Proposed in (Ebrahimi et al., 2012) 13 20 55 5.90 0.64 Not given

Proposed in (Samanbakhsh and Taheri, 2016) 23 115 100 4.23 2.74 92.8
TCHB 9 100 5 2.56 2.57 90.7

653
A. Amir, et al.
Fig. 12. Experimental Results. (a) Switching signals S1, S2, S3, S4, (b) Switching signals S5, S6, S7, S8, (c) Vout < Vgrid (Scale CH3 5.00A, CH4 50.0 V), (d) Vout > Vgrid
(Scale CH3 5.00A, CH4 50.0 V).
a passive anti-islanding scheme has been employed to ensure safety and
security of the inverter. Here, switch Sg has been utilized to realize the
anti-islanding.
5. Simulation results
MATLAB/SIMULINK was utilized to simulate the proposed TCHB in
accordance with the proposed switching scheme. Here, Table.4 presents
the performance parameters of the PV module employed have also been
given. Here a SIEMENS SP-75 module has been utilized, the char-
acteristic curves of which have been displayed by Fig. 8.
In addition, Table.5 presents the systems parameters and Fig. 9(a)
shows the output voltage switching frequency in order to display the
effectiveness of the balanced switching. The switching signals in
Fig. 9(b) are displayed for S1-S8, which have been attained by the in-
tersection of the carrier and reference signals. Standing voltages on the
semiconductor switches including the T-Type bidirectional switches are
shown in Fig. 9(c). Here, a 1:2 ratio transformer has been utilized to
step up inverter voltage Vinv .
In addition, a boost converter for each individual cascade is em-
ployed, as higher than 2 ofVgrid at the DC-bus is required for current
injection into grid. Where Vout < Vgrid current injection reverses from the
grid into the inverter. When the Vout increases or is made higher than
Vgrid for the case Vout > Vgrid the current is injected into the grid and the
Vgrid and Igrid are completely in-phase.
Fig. 10(a) display the case where the Vout < Vgrid showing simulation
result, and the opposite has been presented in Fig. 10(b). For the
modulation index (Ma ) set to exceed 0.75 but below 1, the proposed
TCHB MLI generated a nine-level output-voltage waveform to form the
pre-filtered voltage Vin.
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Solar Energy 199 (2020) 645–656
In order to measure the efficiency of the proposed TCHB inverter, it
has been compared against (Samanbakhsh and Taheri, 2016) and
(Ebrahimi et al., 2012), while operating off-grid on an RL load.
Fig. 11(a) shows the inverter-voltage, output-current and the output-
voltage waveforms of the proposed TCHB inverter when the Ma was set
to be between 0.75 and 1. The post filtering output voltage waveform
and the output current waveform were sinusoidal at the load terminal,
but pre-filtering, the output voltage waveform was quasi sinusoidal.
Fig. 11(b) and Fig. 11(c) show the harmonic content of the output-
voltage. Here, the output-voltage THD was observed to be 2.56%. At
these conditions the output current THD was also 2.57%. Moreover, the
simulation was performed for 0.02 s to attain one cycle of operation at
50 Hz output frequency. For comparative analysis Table 6 compares the
proposed TCHB against various inverter topologies with an RL load,
based on the parameters of THD and η.
6. Experimental results
A hardware prototype of the propose TCHB MLI was built and tested
to authenticate its validity. Here, the switching frequency of 20 kHz and
the fundamental frequency of 50 Hz were used for the TCHB grid
connection. A TMS320F28335 DSP was utilized to validate the simu-
lation outcomes. For each cascade, PV solar arrays of 375 W are em-
ployed as inputs. A series connection of five SIEMENS SP75 modules
produced 375 W of PMPP for each cascade. The intersection of eight
reference signals and one carrier, permissible in the DSP, obtained the
switching signals.
Fig. 12(a) displays PWM switching signals for S1, S2, S3 and S4
switches, whereas, Fig. 12(b) displays the PWM switching signals for
the switches S5, S6, S7 and S8. The dc-bus voltage was set greater than
A. Amir, et al.
Fig. 13. Experimental Results. (a) Output-Voltage THD, (b) Output-Current
THD.
2 ofVgrid and Igrid had been filtered by a filter inductor Lf to resemble a
nearly sinewave. Vinv consists of nine-levels of output-voltage as,
Ma > 0.75&& < 1 was chosen for current injection into the gird. On one
hand, in case where Vout < Vgrid , the grid injects current into the in-
verter, the Igrid and Vinv for this case have been displayed in Fig. 12(c).
On the other hand, for the case where Vout > Vgrid grid-current and
output-voltage are in phase. This condition with nearly-unity power
factor is sufficient for current injection into the grid. The Igrid and Vout
for this case have been displayed in Fig. 12(d). The corresponding
output-voltage waveform THD being 3.0% is shown in Fig. 13(a) and
the corresponding output-current waveform THD being 4.0% is as
Fig. 13(b).
7. Conclusion
This paper recounts the development of the conventional three-level
MLI by proposing the single-phase T-type, nine-level, cascaded H-
Bridge (TCHB) multilevel inverter (MLI) topology, along with its con-
trol and application for a PV system. The control for the inverter op-
eration is based on a PI current controller along with a Maximum Power
Point Tracking (MPPT) scheme to realize a grid-tied photovoltaic (PV)
system. In order to attain gating signals for power transistors (IGBTs),
the TCHB employs a novel PWM with one triangular carrier signal and
eight reference signals. Here, the effectiveness of the TCHB is displayed
by analysing the TCHB against other MLI topologies by showing re-
duced voltage THD of 2.56% and reduced current THD of 2.57%, lower
switching devices being 12, reduced power losses, improved efficiency
at 90.7% and self-balancing at the 4 DC-link capacitors.
655
Solar Energy 199 (2020) 645–656
Declaration of Competing Interest
The authors declare that they have no known competing financial
interests or personal relationships that could have appeared to influ-
ence the work reported in this paper.
Acknowledgements
The authors thank the technical and financial assistance of UM
Power Energy Dedicated Advanced Centre (UMPEDAC) and the Higher
Institution Centre of Excellence (HICoe) Program Research Grant,
UMPEDAC - 2016 (MOHE HICOE - UMPEDAC), Ministry of Education,
Malaysia, HICoe - the High Impact Research Grant (H-16001-00-
D000032), Fundamental Research Grant Scheme FP103-2018A, as well
as the University of Malaya, IPPP, RU007-2018 grant.
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