Experiment #10

8259 Programmable Interrupt Controller Application

Birzeit University
Faculty of Engineering and Technology
Department of Electrical and Computer Engineering

Abstract
This experiment aims at understanding and expanding 8086 Interrupt capabilities using Intel 8259
PIC that includes reviewing Intel 8259 control, its initialization and operational modes. Also, in this
experiment we will use PPI 8255, and PIT 8253/4.

1
 PART I Theoretical Introduction
The 8259A programmable interrupt controller chip accepts interrupts from up to eight different devices. If
any one of the devices requests service, the 8259 will toggle an interrupt output line (connected to the
CPU) and pass a programmable interrupt vector to the CPU. We can cascade the device to support up to 64
devices by connecting nine 8259s together: eight of the devices with eight inputs each whose outputs
become the eight inputs of the ninth device. A typical PC uses two of these devices to provide 15 interrupt
inputs. In this experiment we will focus on a single PIC (no cascading). Figure 2 shows the pin-out of the
8259A. [Refer to the datasheet for more info ]

Interrupt request inputs (IR0-IR7) are used to

request an interrupt and to connect to a slave in a
system with multiple 8259As.

The interrupt output (INT) connects to the

INTR pin on the microprocessor from the master
and is connected to a master IR pin on a slave.

Interrupt acknowledge (INTA) is an input that

connects to the signal on the system. In a system
with a master and slaves, only the master signal Figure 1: Path of an interrupt, from hardware to CPU
is connected.

The A0 address input selects different command

words within the 8259A.

Chip select (CS) enables the 8259A for

programming and control.

Slave program/enable buffer (SP/EN) is a

dual-function pin. When the 8259A is in buffered
mode, this is an output that controls the data bus
transceivers in a large microprocessor-based
system. When the 8259A is not in the buffered
mode, this pin programs the device as a master
(1) or a slave (0).

Figure 2: The pin-out of the 8259A programmable

interrupt controller
(PIC).

The 8259A is programmed by initialization and operation command words. Initialization command
words (ICWs) are programmed before the 8259A is able to function in the system and dictate the basic
operation of the 8259A. Operation command words (OCWs) are programmed during the normal course
of operation. The OCWs control the operation of the 8259A.
2
PART II Pre-Lab
(This part should be handed on to the teaching assistant in your Lab)

1. Review Intel 8259 Programmable Interrupt Controller and its modes of operation. Make
sure you read the datasheet.
2. What would be the I/O ports for the 8259 if direct addressing mode is used with only 8086
A4 being “1” and 8086 A1 being connected to A0 of 8259?
3. Study the TO-DO Practices and write down the values for ICW1, ICW2, and ICW4?
4. What values of OCWs are needed?

3
 PART III Practices
Study the following Figure carefully and Find the addresses for all Peripherals inside, then study the code and understand the configuration for each Component.

U8
1 15
A6 A Y0 CS8259
2 14
A5 B Y1
3 13
A3 C Y2
12
Y3 CS8255
11
Y4
6 10
A4 E1 Y5
4 9
U3 ADR[0..19] A0 A7 E2 Y6
5 7
U7 E3 Y7 CS8253
AD0 3 2 A0
AD[0..15] D0 Q0 M/IO
AD1 4 5 A1 74LS138
D1 Q1
AD2 7 6 A2 OR
D2 Q2
AD3 8 9 A3
D3 Q3
AD4 13 12 A4
D4 Q4
AD5 14 15 A5
AD[0..15] D5 Q5
AD6 17 16 A6
D6 Q6
AD7 18 19 A7
U1 D7 Q7
21 11
RESET AD[0..15] AD[16..19] CLK
22 1
READY A[16..19] MR
24 U6
INTA INTA/QS1 U2
18 25 74273
INTR INTR ALE/QS0 U4 AD[0..7]
31 34 AD0 34 4
HOLD/GT1 BHE D0 PA0
30 27 AD8 3 2 A8 AD1 33 3
HLDA/GT0 DT/R/S1 NOT D0 Q0 D1 PA1
23 26 AD9 4 5 A9 AD2 32 2
TEST DEN/S2 D1 Q1 D2 PA2
17 32 AD10 7 6 A10 AD3 31 1
NMI RD RD D2 Q2 D3 PA3
33 29 AD11 8 9 A11 AD4 30 40
MN/MX WR/LOCK WR D3 Q3 D4 PA4
19 28 AD12 13 12 A12 AD5 29 39
CLK M/IO/S0 M/IO D4 Q4 D5 PA5
AD13 14 15 A13 AD6 28 38
D5 Q5 D6 PA6
8086 AD14 17 16 A14 AD7 27 37
D6 Q6 D7 PA7
AD15 18 19 A15
D7 Q7
5 18
RD RD PB0
11 36 19
CLK WR WR PB1
1 9 20
MR A1 A0 PB2
8 21
A2 A1 PB3
74273 35 22
U5 RESET PB4
23
AD[16..19] PB5
AD16 3 2 A16 6 24
D0 Q0 CS8255 CS PB6
AD17 4 5 A17 25
D1 Q1 PB7
AD18 7 6 A18
D2 Q2
AD19 8 9 A19 14
D3 Q3 PC0
13 12 15
14
D4
D5
Q4
Q5
15
BHE
PC1
PC2
16 0
17 16 17
D6 Q6 PC3
18 19 13
D7 Q7 PC4
PC5
12 0
11 11
CLK PC6
1 10
MR PC7 0
74273
8255A
0

4Mhz Clock

U9
AD[0..7] AD[0..7]
AD0 8 9
D0 CLK0 U11
AD1 7 11
D1 GATE0
AD2 6 10 18
D2 OUT0 D[0..7] IR0
AD3 5 1 19
D3 CS8259 CS IR1
AD4 4 15 2 20
D4 CLK1 WR WR IR2
AD5 3 14 3 21
D5 GATE1 RD RD IR3
AD6 2 13 27 22 R1
D6 OUT1 A1 A0 IR4
AD7 1 16 23
D7 SP/EN IR5 PULLDOWN
18 24
CLK2 IR6
22 16 17 25
RD RD GATE2 INTR INT IR7
23 17 26
WR WR OUT2 INTA INTA CAS[0..2]
19 8259
A1 A0
20
A2 A1
21
CS8253 CS
8253A
CODE SEGMENT PARA 'CODE'
ASSUME CS:CODE, DS:DATA, SS:STAK

STAK SEGMENT PARA STACK 'STACK'

DW 20 DUP(?)
STAK ENDS

DATA SEGMENT PARA 'DATA'

; 0 for lighting, 1 otherwise
DIGITS DB 0C0h, 0F9h, 0A4h, 0B0h, 99h, 92h, 82h, 0F8h, 80h, 90h, 088h, 083h, 0C6h, 0A1h, 86h, 8Eh
, 00 ; 0 to F
DATA ENDS

START PROC
MOV AX, DATA
MOV DS, AX

CALL INSERT_ISR_INTO_VECTOR_TABLE
CALL SETUP_8259
;; Address of 8253: 78h
;; Addrss of 8255: 70h
;; Address of 8259: 10h
MOV AL, 80h ; 1000 0000b
OUT 76h, AL ; Setup 8255 as all ports mo0 output
CALL SETUP_8253

STI
XOR AX,AX
ENDLESS:
CALL SHOW_AX

CMP AX, 10h

JNZ ENDLESS
MOV AX, 0h ; MAke AX 0 after reaching 16

JMP ENDLESS
RET
START ENDP

;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Common Anode Seven Segmeent ; 0 for lighting, 1 otherwise

SHOW_AX PROC NEAR
PUSH AX

XOR BX, BX
MOV BL, AL
MOV AL, DIGITS[BX]
OUT 72h, AL ; 8255's Port B at 72h

POP AX
RET
SHOW_AX ENDP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

5
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
SETUP_8253 PROC NEAR
;; SETUP 8253

; --> Used to Divide 4Mhz Clock to 2000 so that we get 2Khz Output
MOV AL, 00110111b ; 00 [counter 0], 11[ 2 byte data], 010 [ with mod 3], 1 [BCD]
OUT 7Eh, AL ; configure the counter 0 of 8253

; --> Pulse Wave :: MOD 2 of 8253

MOV AL, 01110111b ; 01 [counter 1], 11[ 2 byte data], 010 [ with mod 3], 1 [BCD]
OUT 7Eh, AL ; configure the counter 1 of 8253

MOV AL, 00h

OUT 78h, AL ; Send first byte of Counter 0
MOV AL, 20h
OUT 78h, AL ; Send second byte of Counter 0
;;--> Counter0 : 2000h ; send BCD 2000 to counter 0

MOV AL, 00h

OUT 7Ah, AL ; Send first byte of Counter 1
MOV AL, 5h
OUT 7Ah, AL ; Send second byte of Counter 1
;;--> Counter1 : 5h ; send BCD 5 to counter 1
RET
SETUP_8253 ENDP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
SETUP_8259 PROC NEAR

MOV AL, 00010011b ; ICW1 : Edge Triggered - 1 Master - ICW4 Needed

OUT 10h, AL ; SET InputControlWord1

MOV AL, 40h ; ICW2 : 40h

OUT 12h, AL ; SET InputControlWord2

MOV AL, 03h ; AEOI(Automatic Interrupt) = 1, 8086= 1

OUT 12h, AL ; SET InputControlWord4

RET
SETUP_8259 ENDP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
INSERT_ISR_INTO_VECTOR_TABLE PROC NEAR
XOR AX, AX
MOV ES, AX
MOV AL, 40H
MOV AH, 4
MUL AH
MOV BX, AX
LEA AX, INC_AX_PER_15_SEC
MOV WORD PTR ES:[BX], AX
MOV AX, CS
MOV WORD PTR ES:[BX+2], AX
RET

6
INSERT_ISR_INTO_VECTOR_TABLE ENDP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Interrupt Routine

INC_AX_PER_15_SEC PROC FAR
INC AX
IRET
INC_AX_PER_15_SEC ENDP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

CODE ENDS
END START

7
DATA SHEETS
PIT Control Register:

8
PIC Command Words:

9
PPI:

10